Resistance analysis and device design guideline for graphene RF transistors

Graphene has attracted enormous attention in recent years because of its high carrier mobility and saturation velocity. High-performance graphene transistors for radio-frequency (RF) applications are especially attractive. Synthesis of high quality graphene sheets and application of various materials for gate dielectrics and substrates have been demonstrated. However, very few studies have been performed on the effects of graphene transistor parameters, such as parasitic resistances and graphene quality, in relation to RF applications. Here we report a systematic study of those effects on electrical performance depending on the transistor structure. It is found that the access resistance and contact resistance are the dominant factors leading to degradation of the device performance, especially in deep scaled devices. A guideline for device structural parameter design for required RF performance is discussed. Furthermore, we demonstrate that the newly proposed self-aligned structure can minimize access resistance component, resulting in 6 times higher cut-off frequency compared to that of the conventional structure, when the gate length is 50 nm. The findings of this study can be used to predict the device RF performance and thus help the design of graphene transistor structures to meet specific requirements.


Introduction
Graphene is considered one of future channel materials in high speed semiconductor devices because of its high carrier mobility, high saturation velocity, high current density, and ultra-thin geometry structure [1][2][3][4][5][6][7]. Within the past few years, significant progress has been made in the areas of graphene synthesis, device fabrication, and integration for graphene radio-frequency (RF) electronic applications [8][9][10]. These achievements have led to demonstration of cut-off frequency (f T ) of 100 GHz and higher [11,12] and further improvement can be achieved by enhancing graphene quality and/or device integration techniques. At the early stage of graphene device research, significant efforts were focused on investigating the charge carrier transport property, which is affected by the graphene quality, substrate materials, graphenedielectric stacks, and fabrication process [8][9][10][11]. Despite these efforts, the device performance of graphene RF electronics is still far from the ideal level that graphene promises [2]. Recent reports on graphene RF devices claim that device integration often generates undesirable parasitic components. In particular, the parasitic resistances of the graphene transistors are the critical factor degrading performance in graphene RF devices [13]. The total resistances (R TOTAL ) in the MOS transistors consist of the channel resistance (R CH ) and parasitic resistances, which mainly include contact resistance (R C ) and access region resistance (R A ), as shown in figure 1. The access resistance, R A , is the series resistance of the graphene between the gate electrode edge and the source/drain electrode edge. R A is an undesirable resistance component that degrades the device performance, as the resistance is beyond the control of the gate bias. R A and R C become more prominent as the device is scaled down below the sub-micrometer regime because they are not scaled proportionally to the R CH , and eventually the parasitic resistance can dominate the total resistance in deep scaled devices. It is therefore very timely and necessary to study these parasitic Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI. resistances and understand their impact on the device performance, especially for graphene RF devices. In this work, we identify the critical device structural parameters in both a long channel device and a scaled device. This is an important step to expedite successful realization of graphene RF devices.

Experiment
CVD growth of graphene was carried out by an inductively coupled plasma enhanced chemical vapor deposition process. A 4 inch SiO 2 /Si wafer with a 300 nm thick Cu film was used for the substrate for graphene growth. During the synthesis of graphene, the wafer was heated to 750°C at 50 mTorr in an Ar ambient, and H 2 plasma was supplied to the process chamber for sample treatment. After purging with Ar for 2 min, a mixture of C 2 H 2 and Ar (C 2 H 2 : Ar = 1: 40 sccm) was then flowed into the chamber with 150 W RF plasma; this is the main step of graphene growth. Subsequently, the wafer was cooled in a vacuum ambient for 2 h. Synthesized graphene on the metal film was transferred onto 100 nm thick SiO 2 on a p + silicon wafer using PMMA. The transferred graphene layer was then annealed in a H 2 ambient at 400°C for 30 min to remove residues on the graphene layers. A graphene channel was defined with standard lithography. For the metal electrode of the device, an Au (50 nm)/Pd (10 nm) layer was deposited by a thermal evaporator and patterned by a lift-off process. The graphene area under source/drain electrode is 10 × 6 μm. The device was then annealed in a vacuum ambient (∼1 × 10 −7 Torr) for 12 h to remove possible adsorbates on graphene. The electron beam lithography was used to form short channel device. Gate dielectric consist of 0.5 nm Al seed layer deposited by thermal evaporation and a 20 nm Al 2 O 3 layer by atomic layer deposition. A stack of gate dielectric and 50 nm Au deposited by thermal evaporation was patterned by a lift off process. To form a self-aligned structure, a thin Pd layer (10 nm) was also deposited and patterned by a lift-off process.
The current-voltage characteristics of the graphene transistor were determined using a parameter analyzer (Agilent B1500). A vector network analyzer (Anritsu 37397D) with standard ground-signalground probes was used to study high-frequency scattering parameters (S) of the graphene transistors. The system was calibrated using the short-open-loadthrough (SOLT) method, and on-chip open and short structures were used to de-embed parasitic effects such as the pad capacitance and interconnection resistance. The 'open' test structure only consisted of large photolithography-defined pads, while the short test has additional metal to short the gate, source, and drain pads. The mobility was extracted from the current-voltage characteristics and Hall effect measurement.

Results and discussion
In order to evaluate the impact of various resistances on the RF performance of graphene devices, the values of R CH , R C , and R A in the given devices must be extracted. In this work, for better accuracy in the resistance measurement, the transfer length method [14][15][16][17], which can define the various channel lengths (L CH ) and access region lengths (L A ), was used. Figure 2(a) shows the measured total resistance plotted as a function of L A . Since the total resistance is R CH + 2R C + 2R A , the extrapolation of the data points down to L A = 0 nm gives the value of R CH + 2R C and the sheet resistance of the access region can be found from the slope of the line, which value is 1.17 kΩ/□. The R CH + 2R C values extracted from figure 2(a) were again plotted as a function of L CH with different gate voltages in figure 2(b). Again, the extrapolation down to L CH = 0 nm gives the value of 2R C . In this plot, the corresponding R C was found to be 136.5 Ω μm. The slope in figure 2(b) represents the resistivity of L CH depending on different gate voltages, which modulate the charge carrier density in the channel. R CH is changed from ∼1.6 KΩ/□ to ∼1.9 KΩ/□ at V G = −3 to 3 V. Using this method, the resistance components, R CH , R A , and R C , were extracted through a large data set of more than 150 devices. This systematic analysis enables us to evaluate the effects of these resistances on the RF performance of graphene devices with various device dimensions.
The dependence of resistance components (R CH , R A , and R C ) on different device dimensions is illustrated in figure 3. First, the ratio of each resistance component was plotted as a function of L A when L CH is fixed at 50 nm and 1000 nm, in figures 3(a) and (b), respectively. The device with L CH = 1000 nm ( figure 3(b)) shows that R CH is the dominant resistance term and thereby the charge carrier transport is well controlled by the gate voltage, as is normally expected in field effect transistors. However, in the case of the short channel devices, as shown in figure 3(a), the R CH term is merely a small portion of the total resistance and R C and R A dominate the total resistance. In this case, the charge carrier transport becomes insensitive to R CH , and consequently the device loses gate controllability. For example, when L CH = 50 nm and L A = 300 nm, R CH is only around 10% of the total resistance. This means that only 10% of the modulation of the channel carrier density is reflected to the change of the drain current. This result vividly shows how R C and R A are the critical performance killers in graphene transistors, especially when L CH is below 100 nm. In addition, it also should be noted that for short channel devices, when L A decreases, R C increases in a quadratic manner. Figures 3(c) and (d) show the resistance ratio as a function of L CH when L A is fixed at 10 and 500 nm, respectively. This result shows that under a high R A (L A = 500 nm), in figure 3(d), the short channel device can never be properly operated because the R A term accounts for more than 80% of the total resistance. On the other hand, under a low R A (L A = 10 nm), in figure 3(c), R C is recognized as a critical factor for the short channel devices of L CH < 100 nm. The resistance ratio in figure 3 clearly shows that as the device is scaled down, more effort should be given to minimizing parasitic resistances rather than charge carrier transport.
Next we extended this analysis to the RF performance of a graphene FET. Figures 4(a) and (b) show the cut-off frequency of graphene devices as a function of L CH at different R C and R A , which were extracted from figure 2. The cut-off frequency (f T ) is given by f T = g M /2πC G , where C G is the total gate capacitance (in this experiment, 330 nF cm −2 ) and g M is the maximum transconductance [18], which was extracted from the current-voltage (I D -V G ) characteristics. I D -V G characteristics is given by I D = V D /R TOTAL (R TOTAL = R CH + 2R C + 2R A ). The R C and R A are unaffected by the gate voltage, so they cannot be changed by L CH . The R C and R A are already extracted in figure 2. The R CH has linear relationship with L CH, and reference values of R CH (L CH at 100, 500 and 1000 nm) for each V G are also extracted in figure 2. The R TOTAL at this point for each L G are found to be summation of calculation values.
Here, the top straight curve in figures 4(a) and (b) indicates the maximum achievable (f T ) at the given channel length when the parasitic resistances R C and R A do not exist. According to this, f T of 1 THz is achievable when the channel length is 90 nm with a CVD graphene channel if R C and R A = 0. However, in the real situation, as can be seen in the result, when R C is larger than 250 Ω, f T is weakly correlated to L CH . This means, in this situation, even though the device L CH is shortened, the RF performance of the graphene devices would not be improved. f T becomes inversely correlated to L CH in a logarithm scale only when R C approaches zero. Similar results can be observed in figure 4(b), which shows f T as a function of L CH with different L A at R C = 0 Ω. The extracted f T is again weakly linked to L CH at L A > 1 μm, while f T becomes inversely proportional to L CH in a logarithm scale as L A approaches zero. Figures 4(c) and (d) show f T as a function of L CH with a parameter of graphene channel mobility at L A = 250 nm and L A = 0 nm, respectively, under 2R C = 50 Ω, which is a low parasitic resistance situation. This result shows that under such low parasitic resistances, improvement of graphene quality can have a direct impact on the RF performance of the device. The intrinsic mobility of graphene is known to be as high as 200 000 cm 2 V −1 s −1 , while the field-effect mobility of CVD graphene devices is reported to be around 1000 cm 2 V −1 s −1 . This difference results in a more than two orders of magnitude difference in f T [2,[19][20][21][22].
Low R A and R C values appear to be beneficial to f T , However, the contact resistance R C has a fundamental limit [23] and is often determined by metal selection and the deposition method. Also, it is desirable to minimize L A as much as possible, in order to reduce R A , but at the same time it cannot be zero because the gate electrode must be electrically isolated from the S/ D electrodes. Therefore, optimization of these parameters is extremely important. The results in figure 4 can be used as an RF device design guideline as f T can be projected at the given device structure. As a practical solution to minimize L A in order to improve the RF performance, we propose a new process scheme for a self-aligned graphene RF device. The schematic fabrication process of a graphene transistor with a self-aligned gate is illustrated in figure 5. Large area monolayer graphene was synthesized and transferred onto a Si substrate with a 90 nm thick top SiO 2 layer, as done in previous reports [6,24,25]. The channel length of the fabricated self-aligned graphene RF devices is ∼50 nm which shown in figure 5(h). For comparison, a conventional graphene RF device with the same channel length was fabricated as well. By adopting the self-aligned structure, L A becomes as short as 10 nm, while the conventional graphene RF device has a L A of 250 nm. The self-aligned structure proposed here differs from that provided by previous methods to fabricate self-aligned transistors [25][26][27], where lift-off techniques were used to achieve the gate stack. The current gain of the self-aligned gated graphene device and the conventional graphene device are plotted as a function of frequency in figure 6(a). The frequency characteristics of the two graphene devices were obtained in a range of gate voltage from −3 to 3 V at V DS = 0.5 V. In addition, the standard onchip S-parameter measurements were used with a vector network analyzer over a frequency range of 1-40 GHz. The measurements were first calibrated to the probe tips using an off-chip calibration substrate by a SOLT procedure. A de-embedding procedure was then used to eliminate the effect of the co-planar waveguide pads on the RF performance by measuring onchip 'open' and 'short' test structures [28,29]. The current gains denoted as 'none' and 'de-embedded' are the results before and after the de-embedding procedure, respectively.
The conventional graphene devices with L CH / L A = 50/250 nm show a f T of 25 GHz, whereas the selfaligned gated graphene devices with L CH /L A = 50/ 10 nm show a f T of up to 150 GHz. Since all other device parameters of the two devices are identical except L A , these experimental results clearly show the significance of reduction of the access resistance in terms of RF performance. The inset shows maximum frequency of self-aligned gated graphene devices, and it is up to 30 GHz. Figure 6(b) shows a comparison between the results in figure 6(a) and the calculated f T from the analysis from figures 1 to 4. The measured f T. matches very well with the calculated f T. , which strongly supports the accuracy of our analysis in figures 1-4. This confirms the analysis results here can successfully be used as a design guideline for graphene RF devices.

Conclusions
In summary, we have analyzed the resistance ratio of R CH , R A , and R C in a graphene RF device and discussed its impact on RF performance. This analysis will help design graphene RF device structures according to the target operating frequency. The proposed self-aligned structure can be a solution to minimize the parasitic resistance, thereby improving the RF performance of the graphene device.