Carrier statistics and quantum capacitance effects on mobility extraction in two-dimensional crystal semiconductor field-effect transistors

In this work, the consequence of the high band-edge density of states on the carrier statistics and quantum capacitance in transition metal dichalcogenide two-dimensional semiconductor devices is explored. The study questions the validity of commonly used expressions for extracting carrier densities and field-effect mobilities from the transfer characteristics of transistors with such channel materials. By comparison to experimental data, a new method for the accurate extraction of carrier densities and mobilities is outlined. The work thus highlights a fundamental difference between these materials and traditional semiconductors that must be considered in future experimental measurements.

Two-dimensional (2D) semiconductor crystals, such as the transition metal dichalcogenides (TMDs), are attractive for atomically thin field-effect transistors (FETs) with no broken bonds. 1,2 Coupling the electrostatic advantages with appreciable transport properties in these materials indicates a possibility of high-performance device applications. [3][4][5] As with graphene, the weak interlayer coupling allows TMD individual layers to be isolated and studied. In contrast to graphene, however, the large energy bandgap of 2D semiconductors enables high on/off current ratio FETs. 6,7 Most properties of interest in FETs originate in the statistics of electrons in the conduction band (CB) and holes in the valence band (VB). The electrostatic field-effect control of these mobile carriers by gates, and their transport properties completely determine the device characteristics. Consequently, the methods employed to extract various parameters from the device characteristics, such as the carrier density and mobility must pay careful attention to the carrier statistics and its link with transport. 8 This has not been done for 2D crystal semiconductors yet. This work presents these fundamental results and identifies a number of errors that arise if the carrier statistics effects are neglected, and provides methods for accurate parameter extractions.
For a single-gate FET with a single-layer (SL) 2D semiconductor channel, the electron density in the channel is usually written as: 9 where C ox = ε ox t ox is the gate oxide capacitance per unit area, and ε ox and t ox are the dielectric constant and thickness of the dielectric layer respectively. V gs is the gate voltage, V th the threshold voltage, and q is the electron charge. The gate capacitance C tot in an FET is the total capacitance of C q and C ox connected in series, where C q is the quantum capacitance of the    12 As a result, the DOS is high. As shown in Fig. 1 (a), the carrier statistics stays effectively nondegenerate at room temperature over a very wide range of density of interest (10 11~1 0 13 cm -2 ), with the Fermi level hardly entering the bands. As expected, at elevated temperatures the semiconductor turns intrinsic because of interband thermal excitation of carriers. The intrinsic carrier density ( n i ) in 2D crystal semiconductors is given by where E 0 = E g 2 , E g is the band gap energy. Since in most 2D semiconductors, E 0 ≫ k B T , 12 ) . The intrinsic sheet carrier density is low even at room temperature because of the large bandgap, for example, n i ~ 1.1×10 -2 cm -2 for SL MoS 2 as compared to ~10 11 cm -2 for zero-gap graphene. 8 The carrier density in a semiconductor cannot be lower than at that temperature; this is also the reason for the high achievable on-off ratios in TMD FETs compared to 2D graphene.
The effect of the gate voltage in a FET is to tune the carrier density, and consequently, the Fermi level in FET channels. A positive gate voltage applied to an intrinsic 2D crystal single layer channel populates the CB with electrons, and the Fermi level is driven from the midgap towards the CB edge. The local channel electrostatic potential V ch , which is tuned by the gate bias, determines the electron density in the 2D crystal layer: n i Writing the total charge density in a 2D semiconductor single layer Q = q p − n ( ) as a function of V ch , and using the definition of quantum capacitance C q = − ∂Q ∂V ch , one obtains for 2D level is deep inside the CB or VB, When qV ch > E 0 , and the quantum capacitance C q saturates and approaches the degenerate limit: C q → C dq = q 2 g 2 D . As indicated by the dielectric cases in Fig. 1 (b), for most of the nondegenerate region, C q is much lower than C ox . For very thin dielectrics, for example: 3 nm HfO 2 , even the degenerate limit C dq is comparable with C ox .
Thus the quantum capacitance can significantly influence the field effect. Device models should include C q in order to properly capture the device behavior, especially in the subthreshold region and for devices with high-κ or thin dielectrics.
When the quantum capacitance is taken into consideration, a part of the gate voltage is dropped in the channel to populate it with an electron (hole) density n ch ( p ch ), as shown in the equivalent circuit in the inset of Fig. 2 (a). For FETs with intrinsic 2D semiconductor channels, under positive gate bias, the relationship between V gs and n ch is where V ch and V ox denote the voltage drops in the channel and the dielectric layer respectively, only be solved numerically. The resulting n ch in an intrinsic SL MoS 2 channel as a function of V gs from Eq. (5) is shown in Fig. 2 (a) as black lines for 3 nm and 300 nm SiO 2 gate oxide.
Electron densities calculated with Eq. (1) are also shown in Fig. 2 (a) as reference with blue lines. The shaded areas and the arrows indicate the error between n ox and n ch . It is obvious that the carrier density can be strongly overestimated by using the commonly used expression Eq. (1) for n ox . The large deviation proves that neglecting the quantum capacitance will lead to significant errors in the extraction of the carrier density. where C q ≪ C ox , most of the gate voltage drops in the channel, that is V gs ≈ V ch . In this case, the electron density in the channel n low reduces to as shown by the green line in Fig. 2 (a). n low arises solely due to the channel material itself, thus is independent of the gate oxide. At high gate voltages when the FET is 'strongly on', C q reaches C dq , the channel electron density n high is approximately as shown by the red lines in Fig. 2 (a). V cr is the critical gate voltage that differentiates the situations described by Eq. (6) and (7), which corresponds to the gate voltage when C q = C ox , When V gs < V cr , n ch is determined by Eq. (6); when V gs > V cr , n ch is determined by Eq. (7). The critical carrier density n cr corresponding to V cr is For SL MoS 2 FETs with 300 nm SiO 2 gate oxide, V cr~ 0.698 V and n cr~1 .86×10 9 cm -2 ; for 3 nm SiO 2 , V cr~ 0.818 V and n cr~1 .87×10 11 cm -2 . It is worth noting that Eqs.  6) and (7) should be replaced by Now we discuss the validity of using Eq. (1) to estimate the carrier density in the 2D crystal FET channel. Because Eq. (1) is valid only when V ox ≈ V gs , we show the proportions of V ch and V ox in V gs as a function of n ch obtained from Eq. (5) for SL MoS 2 FETs with 3 nm and 300 nm SiO 2 dielectric layers in Fig. 2 (b). As can be observed, for FET with 300 nm SiO 2 dielectric layer, n ch ranging from 10 11~1 0 13 cm -2 can easily be overestimated by Eq. (1) because is significantly smaller than V gs . For the very thin 3 nm SiO 2 gate oxide, n ch can be strongly overestimated over the whole carrier density range of interest: 10 11~1 0 13 cm -2 , as also shown in Fig. 2 (b). For thin gate barriers, a significant amount of voltage is dropped in the semiconductor channel because of the carrier statistics, and its neglect can cause large errors.
With the correct carrier statistics, we now re-examine the methods employed to extract other important parameters from the device characteristics, for example, the carrier mobility. A

V ox
commonly used method to estimate the carrier mobility in the channel is the field-effect mobility µ FE , given by: 9,13-17 where is the electronic conductivity in the channel, I d is the drain current, V ds is the drain voltage, and L and W are the length and width of the channel respectively. Eq. (10) is widely used in device analysis of Si-based MOSFETs and III-V semiconductor-based FETs. However its validity in TMD devices must be re-examined. Equation (10) is derived from the fundamental drift current equation of an FET in the linear regime at small drain voltages: where v d and µ d are the carrier drift velocity and drift mobility in the channel respectively. To obtain Eq. (10) from Eq. (11), the first assumption is that the carrier density in the channel can be calculated using Eq. (1). For on-state device operation where V gs ≫ V th , Eq. (7) captures the carrier statistics and quantum capacitance more accurately. The term V cr or V th can be eliminated by taking the derivative of I d vs. V gs . Eq. (10) can be recast as which amounts to replacing C ox → C ox C dq C ox + C dq , which is not a fundamental new result in itself, but we emphasize that not doing so can cause significant errors. However, another implicit but more important assumption in Eqs. (10) and (12), which is barely discussed, is that the carrier mobility µ d in the channel does not change when gate bias is varying. The derivative in Eqs. (10) and (12) can lead to significant errors when µ d is V gs dependent, as we now discuss. into consideration. Details of the calculation can be found in Ref. [3]. As can be seen from Fig.   3 (a), at all three temperatures, µ d first increases with n ch and then tends to saturate at high density. At high temperature, a higher carrier density is required to fully screen Coulombic scattering potentials. For example, µ d starts to saturate at ~ 3×10 13 cm -2 at 300 K, but at ~4×10 11 cm -2 for very low temperature 4 K. Combining the results of Fig. 3 (a) and Eq. (5), one can obtain the electron mobility as a function of V gs , as shown in Fig. 3 (b). An ionized impurity density N d of 4×10 12 cm -2 is assumed to be located in the channel, which leads to a negative shift of the threshold voltage of ~ 55 V from the intrinsic case based on the following At 4 K, the mobility starts to saturate at ΔV gs (= V gs − V th )~ 10 V, while mobilities at 77 K and 300 K keep increasing even when ΔV gs is well over 100 V. Note that the drift mobility µ d discussed here differs from the Hall mobility µ H by a Hall factor, which is induced by the magnetic field in the Hall-effect measurement.
The Hall factor is often assumed to be unity, however careful consideration of the Hall factor with relevant scattering mechanisms at different temperatures needs further detailed study. 18 Baugher et al. 19 have compared µ FE and µ H and found that µ FE can differ significantly from µ H . They attributed the lower µ H to the possible screening of charged impurity scattering at higher densities, which is consistent with our results in Fig. 3. In the following, we quantitatively explain the discrepancy between the conventional method of extracting the fieldeffect mobility µ FE and the 'true' drift mobility µ d in the channel by combining a theoretical transport calculation with density-dependent mobility, and with the correct electrostatics of the  can be observed, with constant mobility, the on-state current appears to fit well for high V gs ~ 20 -40 V. However, significant quantitative and more importantly, qualitative discrepancies are observed at low V gs . On the contrary, if we fit the current at low V gs , we would see large errors at high V gs . Thus we remodeled the devices characteristics by taking both the carrier statistics, and the V gs -dependence of the electron mobility into account. This calculation is shown as red lines in Fig. 4 (a) and (b). The impurity density is used as the fitting parameter, with value of ~ 4×10 12 cm -2 . The excellent fit of the V gs -dependent µ d model to the experimental data over several orders of magnitude change in current indicates that if we use Eq. (10) or even Eq. (12) to extract the field-effect mobility from the FET transfer characteristics, we will be in significant error. Both the quantum capacitance and the density-dependent mobility must be included for proper extraction.  sub-threshold region and the on-state region that described by Eq. (6) and Eq. (7) respectively.
For current structure, V th is ~ -55 V. To further prove the validity of the method of extracting V th , we find that when V gs = V th , E f is located ~0.66 eV above the midgap, as shown in Fig. 4 (c). This is also the Fermi level when C q ≈ C ox , as can be observed in Fig. 1 (b). Once the threshold voltage is extracted, one can now estimate the carrier drift mobility in the channel at room temperature with combining the empirical expression proposed in Ref. [3] and Eq. (7) for n ch ≤ 10 13 cm -2 : where To further show the discrepancy between the field-effect mobility and the drift mobility in the device channel, we calculate the transfer characteristics of a SL MoS 2 FET as a function of temperature, using the same parameters as used in Fig. 4. The example transfer curves at temperatures 4 K, 100 K, 200 K and 300 K are shown in Fig. 5 (a). Because µ FE is usually extracted from the measured transfer characteristics in the region that appears to be linear, 15 for example, for V gs ~ 20 -40 V in Fig. 4 (b), here we take the carrier mobility at V gs~ 20 V as a case study. The carrier density at V gs~ 20 V is n ch~ 5.4×10 12 cm -2 . The field-effect mobilities calculated using Eq. (10) are shown by the red line in Fig. 5 (b). Because of the derivative term in Eq. (10), µ FE is proportional to the slope of the tangent to the I d -V gs curve, as indicated by the red lines in Fig. 5 (a). The black curve in Fig. 5 (b) shows µ d calculated using our transport model. As we can see from Fig. 5 (b), µ FE is higher than over the entire temperature range.
Moreover, the error Δµ ( = µ FE − µ d ) is not constant as the temperature varies. The value of Δµ depends on the dependence of µ d on V gs , as was shown in Fig. 3 (b). The faster µ d increases with V gs , the higher is the discrepancy Δµ . µ FE calculated by Eq. (10) shows a much higher value of ~ 104 cm 2 /Vs at 300 K while µ d is ~ 50 cm 2 /Vs. Conversely at 4 K, since µ d starts to saturate at very low ΔV gs , µ FE (~ 190 cm 2 /Vs) is only slightly higher than µ d (~ 175 cm 2 /Vs). At temperature lower than 20 K, one can approximate µ FE ≈ µ d with error less than µ d 10%. Over 20 K, Δµ first increases and then decreases with increasing temperature, leading to an apparent increase of µ FE at temperatures ranging from ~30 K to ~80 K. This observation can partially explain the experimentally obtained decrease of the field-effect mobility as the temperature is lowered. 9 Thus we conclude that µ FE extracted from the device transfer characteristics by Eq. (10) not only overestimates the electron mobility, but can also show a false temperature dependence. The red line in Fig. 5 (b) shows an anomalous increase of mobility with temperature for 30 K < T < 80 K. This is not related to any real scattering mechanism, but rather has roots in using incorrect carrier statistics.
To accurately extract the carrier transport properties from the device measurements, the fieldeffect mobility may be obtained by: µ FE _ acc extracted from the calculated transfer curves in Fig. 5 (a) using Eq. (14) are shown as open triangle symbols in Fig. 5 (b) with V th taken as -55 V. We can see a very good agreement between µ FE _ acc and µ d . Now µ FE _ acc is proportional to the slope of the straight line joining remarkable low contact resistances have been achieved. [29][30][31] In conclusion, we have investigated the importance of the carrier statistics and quantum capacitance in understanding the characteristics of 2D crystal semiconductor electronic devices.
The commonly used expressions for extracting the carrier density and field-effect mobility from the transfer characteristics of 2D semiconductor FET are demonstrated to be only valid for very limiting conditions, and prone to severe errors. By combining the correct carrier statistics, quantum capacitance, and density-dependent mobitlities, we prescribe a new method to extract the correct mobilities from the FET measurements. The results presented here are expected to be useful to place our understanding of the fundamental properties of 2D crystal semiconductors on a more firm foundation.