An extensive electrostatic analysis of dual material gate all around tunnel FET (DMGAA-TFET)

In the proposed work an analytical model of a p-channel dual material gate all around tunnel FET (DMGAA-TFET) is presented and its performance is compared with the conventional GAA-TFET. The electrostatic potential profile of the model is obtained using 2-D Laplace’s solution in the cylindrical coordinate system. A quantitative study of the drain current has been carried out using electric field in the z-axis and tunneling path. However the potential and current analysis is prolonged to different combinations of gate length in the DMGAA-TFET model. The results show an improvement in drain current and subthreshold swing as compared to GAA-TFET, which makes this model a potential replacement for low power application. Also the effect of scaling of the gate oxide thickness and cylindrical pillar diameter on the surface potential, initial tunneling point and tunneling current are analyzed.


Introduction
As the conventional metal-oxide-semiconductor field effect transistor (MOSFETs) scaled beyond its physical limit, it suffers from high subthreshold swing (SS), high leakage current (I OFF ) and other short channel effects (SCEs) like threshold voltage roll-off and drain induced barrier lowering (DIBL) [1][2][3][4]. Many researchers employed a number of multigate silicon on insulator metal-oxide-semiconductor (MOS) technology to improve the device performance by enhancing the gate control over channel from various sides [5][6][7][8]. However gate all around (GAA) MOS provides highest degree of control over channel and lowest characteristics length with the reduction of various SCEs compared to omega/pi-gate, tri-gate, double-gate and single-gate structures [9][10][11]. That also demonstrates the maximum scaling capability and strong electric field confinement of the structure. But the key concern of GAA-MOS device is that it offers high subthreshold swing and leakage current in the subthreshold region which makes the device incompatible for low power and steeper switching applications [12,13].
GAA tunnel FET (TFET) is the likely alternative for MOS technology which has the capability to reduce SS limit and improve the device scaling performance. Also it reduces different SCEs because of gated p-i-n structure. The movement of charge carriers in TFET is due to the non-local bandto-band tunnelling (BTBT) process and is independent of temperature variation [14][15][16][17][18]. It also offers better electrostatic control over the channel due to cylindrical gate confinement [9]. A number of analytical models have been proposed to compute the potential and drain current of multigate TFET by using Kane's model [19][20][21][22]. However GAA-TFET provides low on-state drain current and high off-state leakage current compared to bulk technology due to tunnelling process [23]. The improvement of on-current in TFET can be achieved by optimizing the band-gap energy of semiconductors [24]. The gate engineering can be employed to enhance the tunnel current and to optimize the device parameters as proposed by Saurabh et al [25,26].
In this paper a dual material gate all around TFET (DMGAA-TFET) analytical model is developed which has two regions with different work functions cascaded to each other. The region-1 is having higher work function as compared to region-2. The change in surface potential due to work function difference results in improvement of gate control over tunneling process and thus drain current increases compared to single material. The model provides high tunneling current with reduced DIBL and better scaling of oxide thickness and cylindrical pillar diameter. In this work the entire channel length is considered as 30 nm. The behavior of electrostatic potential and drain current for different combinations of gate length such as L 1 = 10 nm and L 2 = 20 nm, L 1 = 15 nm and L 2 = 15 nm, L 1 = 20 nm and L 2 = 10 nm are observed. The combination L 1 = 20 nm and L 2 = 10 nm shows better performance compared to other combinations. The effect of scaling of t ox and t si on electrical parameters is also studied.

Analytical model of DMGAA-TFET
The cross-sectional view of a p-channel dual material GAA-TFET structure is shown in figure 1. The source and drain regions are heavily doped with pentavalent and trivalent impurity of concentration 10 20 cm −3 respectively. The channel region is un-doped and made up of intrinsic material with negligible trivalent concentration of 10 15 cm −3 . For the given model two different metals having worked function AE = 4.9 eV M1 and AE = 4.7 eV M2 are considered as the gate metal contacts. The entire channel is divided into two regions (region-1 and region-2) as depicted in figure 1. The effective length of these non-overlapping channel regions are L 1 and L 2 respectively. However the low-k dielectric SiO 2 is used as the gate oxide layer having thickness (t ox ) 2 nm. The diameter of silicon cylindrical pillar (t si ) is taken as 10 nm. Here the length of both metallic regions is varied keeping the work function and total channel length constant.
The effect of doping concentration of channel on analysis of electrical parameters is neglected as the channel is considered as intrinsic and is lightly doped with a concentration of 10 15 approximately. The electrostatic potential of both the channel regions have been obtained by solving the 2-D Laplace's equation which is obtained by neglecting the electron space charge.
Here j r z , 1 ( ) and j r z , 2 ( ) denote the electrostatic potentials in the channel region-1 and region-2 respectively. The above equation can be used to compute the surface potential at the gate-channel interface and center potential at the center of cylindrical pillar for both channel regions The solution of above Laplace's equation in both regions has been resolved using 2nd order polynomial approximation [13] The boundary conditions are required to predict the zdependent coefficients a , Here  si is the dielectric permittivity of silicon, C ox is the oxide capacitance,  ox is the permittivity of oxide layer and V GS is gate-to-source bias. However V FBj denotes the flat-band voltage of both the regions, which is independent of gate length and can be calculated through the work function of materials where AE Mj and AE si represents the work function of gate material for j th region and silicon work function respectively. The essential boundary conditions at the interface of both the channel regions are required to solve equation (1). The potential profile and lateral electric field for both the regions are same at the interface Using the above boundary conditions at the center of the cylindrical pillar, channel-SiO 2 interface and dual region interface, the potential profile at the center is found to be j j where λ is known as the natural length of cylindrical structure and is expressed as The surface potential of the cylindrical structure j z s ( ) is related to the center potential j z c ( ) as [25] The surface potential for both the channel regions are obtained by solving equation (16).
Similarly the surface potential for region-2, For the above expressions the coefficients C 1 , C 2 , D 1 and D 2 can be calculated using the potential boundary conditions at the source and drain end [27] Here V bi is the built-in-potential, V DS is the voltage applied at the drain terminal and = + L L L 1 2 is the maximum channel length of the device. Equating equations (17) and (18) using the boundary conditions at source-channel and drain-channel interface, we found However the center potentials of both the channel regions can be obtained using equation (13). The center potentials of region-1 and region-2 are expressed as In conventional TFET the tunneling of charge carriers is primarily based on is non-local BTBT mechanism [28][29][30].
For GAA-TFET the tunneling process is dominant in the lateral direction of cylindrical body. So it is desired to find the lateral field in both the channel regions which helps us to calculate the tunneling current. However the lateral electric fields in both the regions are obtained by differentiating the potential profile in the range of   z L 0

Drain current analysis
In non-local BTBT the tunneling of charge carriers starts only when the conduction band of source gets in-line with the valence band of channel region [31]. At zero gate bias a small amount of band bending arises at the source-channel interface, because of the presence of built-in-potential. This condition is known as OFF-state condition of the device as depicted in figure 2(a). In this state the current in the channel is insignificant due to the absence of band-to-band tunneling. Further increase of gate bias results significant amount of band bending. When the applied gate potential attains a critical value (V th ), the conduction band of source and valence band of channel gets aligned to each other. For V GS > V th , the drain current increases exponentially due to the improvement in tunneling volume as depicted by the area under the solid lines in figure 2 In the ON-state the tunneling path is the lateral distance between the two tunneling points z 1 and z 2 . The initial tunneling point is the value of z for which the surface potential changes by an amount of unit band gap energy per elementary charge / E q . g ( ) However this point plays a decisive role in the extraction of drain current. In this model z 1 is assumed to lie in the region-1   z L 0 , 1 1 ( ) because the region-1 is surrounded by the metal with higher work function. So the tunneling distance z 1 can be obtained by using the surface potential profile at the interface and at the critical threshold where E g is the band-gap energy of silicon at equilibrium. z 1 can be further reduced by optimizing band-gap energy of semiconductor and increasing the gate potential (V GS ). Low z 1 increases the tunneling path along the channel and hence the drain current is improved. In this model the tunneling volume is not affected by the drain voltage for constant V GS . This is because the effect of electron charge injected into the channel from the drain end has been neglected in equation (1). The drain current can be calculated by integrating BTBT generation rate over the entire tunneling volume in both the radial and lateral directions. However, for the present model the current is obtained in the lateral direction of channel from z 1 to z 2 using Kane's direct tunneling phenomena [32]. Here z 1 lies in the region-1 due to sharp reduction of the surface potential and z 2 lies in the region-2 due to charge accumulation at drain end as shown in figure 2(b). So the drain current is expressed as  Here both the channel regions involve tunneling process as  z L 1 1 and > z L . 2 1 Hence the tunneling volume is calculated by integrating the generation rate over both regions and is expressed as   because of higher work function and larger gate length of the region-1. The sharp reduction of potential is responsible for increase of the BTBT tunneling volume and drain current. So for this model, current analysis has been done with gate length L 1 = 20 nm, L 2 = 10 nm and results are compared with different combinations of dual gate lengths.

Results and discussion
The center potential at r = 0 and surface potential at r = t si /2 of the DMGAA-TFET are compared for different gate voltages in figure 4. For a constant gate voltage the center potential lies above the surface potential. This is due to higher influence of gate bias at the channel interface. In the present analysis surface potential based approach is followed for the calculation of tunneling current.
The surface potential profile for the proposed model with different gate voltages at a constant drain voltage are illustrated in the figure 5(a). The potential is stuck to built-inpotential (V bi ) at the source interface and V DS at drain interface as per the boundary condition. The surface potential in both the channel regions reduces with increase in gate voltage at V DS = −0.1 V. Therefore the slope of the surface potential is getting sharper and the minimum potential is achieved early. The sharp slope of the potential for higher gate voltage indicates the larger tunneling volume. However the potential of entire channel of GAA-TFET varies linearly. This is due to the impact of drain bias over both the channel regions. Figure 5(b) shows the surface potential of the proposed device for various drain voltages. It is observed that the slope of the reduced potential profile is not affected by the increment of the drain voltage as the effect of electron space charge has been ignored in equation (1). Hence there will be no significant drain induced barrier lowering (DIBL) effect in the model, so the tunneling current is not affected by drain bias. Figure 6 demonstrates the effect of reducing gate oxide thickness and pillar diameter on the surface potential and the results are compared to the conventional GAA-TFET. Unlike the orthodox model, the potential of DMGAA-TFET decreases as we go on reducing t ox and t si . The potential is minimized further due to the influence of gate bias on channel at low oxide thickness and pillar diameter. Dual material GAA-TFET shows reduced and sharp slope potential profile as compared to single material gate. Figure 7 shows the behavior of lateral electric field of the model and that has been compared with the different combinations of gate length. It is clearly seen that the electric field varies non-linearly for the entire channel for a constant gate and drain bias and the field exists for both the channel regions. However the lateral field plays a vital role in the calculation of tunneling volume over the entire channel.
The initial tunneling points for different values of gate length as a function of gate voltage are shown in figure 8. The results are compared to the conventional GAA-TFET. As the gate voltage increases beyond threshold, the charge carriers tunnel from source to channel which results z . 1 Lower the z , 1 better the tunneling volume. Inclusion of dual material gate results in low z , 1 hence improves the device performance. For the proposed model the combination of the gate lengths L 1 = 20 nm and L 2 = 10 nm yields best result because of sharp slope of surface potential. The sharp reduction of surface potential reduces threshold voltage, hence achieves tunneling earlier.
For a constant gate oxide thickness and cylindrical pillar diameter, z 1 reduces with increase in gate voltage beyond threshold. As the gate oxide thickness (t ox ) is scaled from 3 to 1 nm for radii of 5 nm, more tunneling volume is achieved because of the reduction of z 1 as depicted in figure 9(a). This is due to the impact of gate bias on channel with low oxide thickness. Reduction in z 1 enables the flow of charge carriers for small value of V GS . Similarly figure 9(b) displays the variation of z 1 versus V GS for different Si pillar diameter for the dual material model. When the diameter of cylindrical pillar reduces, the gate control on the channel is dominant and thereby reduces z 1 marginally. Therefore the scaling of t ox and t si improves the drain current performance of DMGAA-TFET. Figure 10 shows I D -V GS characteristics for GAA-TFET in linear and logarithmic scale. The drain current analysis is done for different combinations of gate length as a function of gate voltage. As the gate bias increases beyond threshold, the tunneling current flows from source to drain end along the lateral direction. However the on current performance of dual material gate is better as compared to single material, because of sharp potential reduction and minimum threshold achievement. Here also the gate length combination L 1 = 20 nm and L 2 = 10 nm yields better performance in comparison with other lengths as the BTBT current primarily influenced by the sharp potential profile near the sourcechannel interface. The drain current improves exponentially for V GS > V th due to dominant tunneling process in both channel regions. Figure 10(b) displays the logarithmic drain current versus V GS . The model produces drain current in the range of 10 −5 A compared to single gate model (10 −6 A) depicted in figure 10(b). High I ON and low I OFF can be achieved because of large L 1 and small L 2 , respectively. So the gate length combination L 1 = 20 nm and L 2 = 10 nm provides maximum I ON to I OFF ratio.        The I D -V DS characteristics for different gate length combinations are shown in figure 11(a) at constant gate bias. In the ON state the drain current is independent of drain voltage, because of the dominancy of gate bias. The independent nature of drain current versus V DS is due to the fact that the electron space charge has been neglected in the electrostatic potential analysis. At V GS = −1 V, the conventional GAA-TFET produces current of order 10 −10 A. This negligible amount of current resulted, because at V GS = −1 V the device operates at cut-off. Whereas with the same gate voltage DMGAA-TFET yields higher drain current of order 10 −8 A with low threshold. However the device with higher region-1 dimension gives better on current performance at constant gate voltage. Figure 11(b) shows the I D -V DS characteristics of DMGAA-TFET for different gate voltages. It is clearly observed that increase in gate voltage beyond threshold results increment in drain current. Figures 12(a) and (b) display the effect of t ox and t si variation on drain current. Figure 12(a) shows significant increment of drain current with reduction in oxide thickness for the model, because of the small value of initial tunneling point. This leads to larger tunneling volume in non-local direct tunneling process and hence results large tunnel current. Similarly the effect of scaling of t si on drain current for different combinations of gate length is depicted in figure 12(b). It is clearly observed that high drain current is obtained at lower thickness of the cylinder due to higher influence of gate on channel. The BTBT tunneling takes place faster for small diameter and conversely improves the tunneling current. Comparing the results for different combinations of gate length, L 1 = 20 nm and L 2 = 10 nm gives better performance. Figures 13(a) and (b) show the effect t si and t ox scaling on I D versus V GS characteristics of DMGAA-TFET and concluded that higher drain current is achieved at low t ox and low t si due to gate-dominant tunneling process. As we scaled down the t si from 10 to 6 nm, the tunneling current improves by a factor of 10 as given in figure 13(a). However in the subthreshold region (V GS < V th ), the effect of the variation of t si is insignificant on drain current due to the absence of tunneling of carriers.
Subthreshold swing (SS) can also be calculated for different gate voltages in the subthreshold region and compared  to single-material GAA-TFET as shown in table 1. DMGAA-TFET produces low SS for V GS < V th .
Therefore this model can be a potential candidate for ultra-low power CMOS applications in the near future due to vast improvement of drain current at low subthreshold swing.

Conclusion
In this paper a 2-D analytical model for p-channel DMGAA-TFET is developed. The work proposes the potential profile of two channel regions for different gate length ratios. This results improved drain current compared to conventional GAA-TFET. The impact of work function, gate length, gate oxide thickness and cylindrical body diameter on the drain current and initial tunneling point are discussed. The drain current is improved approximately by a factor 10 for DMGAA-TFET compared to conventional GAA-TFET. Also the improved SS resulted for the present model (30 ∼ 40 mV/ decade) allows the device to be a promising candidate for low power and high speed application.