Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime

In this work the sensitivity of process parameters like channel length (L), channel thickness (tSi), and gate work function (φM) on various performance metrics of an undoped cylindrical gate all around (GAA) metal-oxide-semiconductor field effect transistor (MOSFET) are systematically analyzed. Undoped GAA MOSFET is a radical invention as it introduces a new direction for transistor scaling. In conventional MOSFET, generally the channel doping concentration is very high to provide high on-state current, but in contrary it causes random dopant fluctuation and threshold voltage variation. So, the undoped nature of GAA MOSFET solves the above complications. Hence, we have analyzed the electrical characteristics as well as the analog/RF performances of undoped GAA MOSFET through Sentaurus device simulator.


Introduction
To achieve low cost, high operational speed and better performance, the dimensions of conventional transistors need to be downscaled to the sub-nanometer region. The reduction of metal-oxide-semiconductor field effect transistor (MOSFET) dimensions will degrade the gate control over the channel due to close proximity between source and drain. This leads to increase various short channel effects (SCEs) such as hot carrier effect, threshold voltage roll-off, and substrate bias effect [1,2]. Many new devices have been introduced beyond Moore's era [3][4][5] to suppress the SCEs and enable further scaling down of the device. Similarly, a number of multi-gate silicon on insulator (SOI) technologies have also been proposed to replace the conventional MOSFET [6,7]. However, the cylindrical gate all around (GAA) MOSFET is one of the novel devices which further enables scaling without hindering the device performance. Because of the low characteristic length and higher drive current, GAA MOSFETs can achieve higher packing density as compared to double gate (DG) MOSFETs [8][9][10]. Also GAA MOSFET has excellent electrostatic control of the channel, robustness against SCEs, better scaling options, no floating body effect, larger equivalent number of gates, and ideal subthreshold swing as compared to other multiple gate MOSFETs. Hence, the GAA MOSFET is a promising solution for nanoscale technology complementary metal-oxide-semiconductor (CMOS) devices [11][12][13][14][15]. Recently, MOS devices with sub-50 nm channel length demonstrate more than 100 GHz of cut-off frequency [16][17][18]. Important device parameters such as threshold voltage (V th ), on-off ratio (I on /I off ), and cut-off frequency (f T ) are very much sensitive to the device geometry such as channel length (L), channel thickness (t Si ), and gate work function (φ M ). In this work an attempt was taken to present a detailed analysis of the performance dependency of GAA MOSFET on device geometry variation.
In this paper, different performance metrics like drain current (I D ), transconductance (g m ), total gate capacitance (C gg ) and cut-off frequency (f T ) are systematically presented with the variation of L g , φ M , and t Si . Along with the introduction, section 2 describes the device structure description that includes all the dimensions, materials and doping concentrations of GAA MOSFET. This section also analyses the physics of the device using device numerical simulations and models activated for simulation. Section 3 comprises all results and discussion. Finally, the concluding remarks are presented in section 4.

Device structure and simulation setup
The schematic diagram of the fully depleted cylindrical GAA MOSFET structure used for modeling and simulation is shown in figure 1. The radial and lateral directions of the channel are assumed to be along the radius and the z-axis of the cylinder as shown in figure 1. The source and drain of the device are uniformly doped with doping concentration of N D = 1 × 10 20 cm −3 . The channel is kept undoped. The gate oxide thickness is t ox = 1.1 nm.
The simulation is carried out by the device simulator Sentaurus, a 3D numerical simulator from Synopsis Inc. [19]. To obtain accurate results for MOSFET simulation we need to account for the mobility degradation that occurs inside inversion layers. The drift-diffusion model is the default carrier transport model in Sentaurus device is activated. For the drift-diffusion model, the current densities for electrons and holes are given by where J n and J p are electron and hole current density, μ n and μ p represent electron and hole mobility, n and p describe electron and hole density, γ n and γ p are Fermi statistics constants, and m n and m p present spatial effective masses of electron and hole, respectively. T and k describe temperature and Boltzmann constant. E C and E V are conduction and valance energy bands. D n and D p represent the diffusion constants for electron and holes respectively.
The first term takes into account the contribution due to the spatial variations of the electrostatic potential, the electron affinity, and the band gap [20,21]. The remaining terms take into account the contribution due to the gradient of concentration, and the spatial variation of the effective masses m n and m p . All other terms used have their commonplace meanings. In the simulation, basic mobility model is used that takes into account the effect of doping dependence, high-field saturation (velocity saturation), and transverse field dependence. The silicon band gap narrowing model that determines the intrinsic carrier concentration is activated.

Results and discussion
In order to analyse the impact of channel length (L g ), and channel thickness (t Si ), and gate work function (φ M ) on the device performance, the simulation is carried out by varying the above parameters.  figure 2(a), L g varies from 28 to 70 nm and we can observe from the figure that a decrease in L g results a shift in the characteristics. The off-state current (I off ) increases dramatically as L g decreases to below 30 nm with comparison to others. In the short channel device the I off increases due to random motion of charge carriers. As channel length decreases, it gives rise to high drain current because of the relation I D ∝ 1/L. However, from the log scale, the leakage current is also prominent for lower channel lengths. Figure 2(b) reveals the I D dependency on silicon body thickness of the GAA MOSFET. The characteristic of I off is also influenced by t Si , which is cleared from figure 2(b). As the silicon film gets thinner, there is a significant improvement in leakage current because no further leakage path is available far from the gate. Figure 3(a) represents the I D -V GS characteristic for different values of metal gate work function (φ M ). The work function is varied from 4.6 eV to 5.1 eV for V DS = 50 mV (sub-threshold region of operation). The results illustrate that the off-state leakage current (subthreshold performance) of the device improves for higher values of metal gate work function. This is because the higher φ M consequently depicts higher threshold voltage, which further reduces the off-state leakage current and improves the subthreshold behavior of the device. Figure 3(b) shows the intrinsic capacitances (gate to gate capacitance C gg ) as a function of I D for subthreshold or weak inversion with variation in channel length. As shown in figure, the intrinsic capacitance increases with increase in I D . This is because of the increase in the fringing field lines emanating from the gate edges. The device with L g = 28 nm shows low value for C gg and as L g increases the C gg also starts increasing and obtains its maximum at L g = 70 nm. Hence, in the case of L g = 28 nm, the intrinsic capacitance value is smallest, which in turn leads to high cutoff frequency.
Transconductance (g m ) and cut off frequency (f T ) as a function of I D are presented in figures 4(a) and (b), respectively. From the figure, it is clear that as the channel length decreases the g m value is increasing because of high drain current. The high g m will further enhance the transconductance generation factor (TGF = g m /I D ) which is the requirement for realization of circuits operating at low supply voltage. From figure 4(b), the variations of cut off frequency (f T = g m /2πC gg ) can be observed with respect to V GS for different values of channel lengths. Here, the value of f T obtained for the device having low channel length is higher, and gradually decreases as the channel length increases. f T is inversely proportional to the intrinsic capacitance (C gg ). So, the f T value is low due to high capacitance values for higher channel length devices, as discussed in figure 3(b).
All the extracted and calculated values of dc as well as analog/RF performances are tabulated in tables 1-3 with the variation of silicon body thickness (t Si ), gate work function (φ M ), and channel length (L g ) of the GAA MOSFET respectively. Table 1 compares and analyses the sensitivity of   t Si on various important parameters such as I on , I off , and V th . We can effectively control the V th and SCEs such as off-state leakage current by reducing t Si with a little compromise in onstate current. Hence, people always prefer ultra-thin body (UTB) fully depleted (FD) SOI MOSFET as the body is completely controlled by the gate and there is no leakage path far from the gate. The percentage of improvement in I off is 82.53% and 91.33%, while t Si varies from 15 nm to 10 nm and 10 nm to 5 nm, respectively. Table 2 reports the similar parameters (as in table 1) but with variation in gate work function (φ M ) for gate length L g = 28 nm. The φ M is one of the main controlling parameters threshold voltage. As we can measure from the table, V th is increasing with increase in φ M , which further controls the subthreshold leakage current. While φ M changes from 4.6 eV to 4.9 eV, a significant improvement in I off consequently in SCEs can be observed. Table 3 summarizes the analog/RF figures of merit (FOMs) for different values of channel lengths. It is clear from the table that, while the gate length is reduced, the RF FOM f T is increased because of high drain current which results in higher g m values for shorter gate length devices.

Conclusion
A cylindrical gate all around (GAA) MOSFET is explored and the performance evaluation is carried out with extensive device simulation by Sentaurus simulator. The sensitivity of device parameters like t Si , φ M , and L g on various dc and analog/RF FOMs are systematically presented. From our results, by considering an ultra-thin body (UTB) and little higher gate work function can enhance the device performance with well suppressed SCEs. The subthreshold leakage current can be significantly improved for lower t Si and higher φ M values. Similarly, continuous miniaturization of L g is required for obtaining high I on , g m , and f T . Hence, an appropriate selection of the silicon thickness, and metal gate work function give rise to an optimum threshold voltage at a given channel length and drain bias.