Bit error rate evaluation in high speed communication channels

This work offers calculate technique probability errors in transmitter – receiver path during the design phase with apply theory of probability elements, which is based on results of transient process modeling. As estimation, designed method was verified by comparison his results with computer experiment results. Implementation and using variants of represented algorithm are offered.


Introduction
Serial transceivers are essential part of transfer data electronic systems. They provide stability and fast information exchange between devices by external communication lines.
Actual transceivers with data rate 1 Gbps and more should provide number of errors less 10^-12. With current data rates (1,25/2,5/3,125 Gbps and more) impact of phase distortion increases on transmitted data integrity.
Bit Error rate (BER) is important and obvious criterion of transceiver path work and is defined as number of errors divided by total number transmitted bits. Currently measuring devices manufacturers offer technique of measurement BER for a couple transmitter -receiver, but actual problem is estimation BER during the design phase.
Eye diagram is image of superposition all bit periods of measured signal. Estimation of correctly data transmit is provided by apply mask to eye diagram. Intersection of mask with eye diagram means error. But this method provides only rough estimate.
There are algorithms estimation BER which is based on some basic principles. Comparison of main methods is represented in Table 1. Methods, which is based on results SPICE modeling, require long time modeling. Example, confirmation of BER level less 10^-12 require modeling transmit more 10^12 bit. Statistical methods provide high precision of estimation and high calculate speed. Algorithm types is possible, which can have universality with modeling different transmitter -receiver path types.

The task of receiving data
The task of any transceiver is to trusty exchange information between two paired devices. It is necessary to control all critical nodes that are subject to changing conditions of the circuit operation and the influence of jitter. One of the main elements of the receiver, requiring attention, is the first trigger of the shift register in the receiver, which latches the input data stream and converts it into an internal data signal Q_CORE ( Figure. 1). Figure. 1. The first trigger of the shift register of the digital part of the receiver. The Stream and CLK signals are a data signal and a clock signal, respectively. The phase of the CLK signal is restored from the Stream signal using the Clock and Data Recovery (CDR) block. The Stream data signal is received from the interface part of the receiver, the CLK reference signal is produced by a phase and frequency adjustment unit called the CDR. To successfully pass the data signal with the subsequent deserialization of the stream, in general, it is necessary to observe the required phase and amplitude relations between these signals.
From the central limit theorem of probability theory it is known that the sum of a sufficiently large number of weakly dependent on each other random variables having the same scope, subject to the normal distribution. Based on this situation it is assumed that the noise, which is the source of bit errors has a normal distribution in amplitude. Therefore, for the treatment of the consequences of his influence can be to use the tools of probability theory.
The parasitic elements of the topology and the housing deteriorate the parameters of the transmitted signal [4]. Therefore, when the worst bit sequences are transmitted, for example "0101" or "1110", the signal amplitude is distorted and the deterministic jitter increases [5].
Two types of causes of bit errors can be identified. First, at low values of the signal-to-noise ratio, the transmitted signal can cross the receiver switching level (Figure 2), and, consequently, the probability of an error in receiving increases.
Secondly, the necessary condition for obtaining correct data receiver is that the permitted switching timing between the data signal DATA and the clock signal CLK input to flip-flop in the digital portion of the receiver ( Figure. 3).  The data must arrive at the input no later than the minimum setup time ( _ ) to the clock edge. Also, the data must remain at the input after the clock signal drops no less than the minimum hold time

Description of the BER analysis method
During transmission, a bit error can occur regardless of two reasons: amplitude or phase distortion of the input signals. In this case, the error probabilities of these two species will be different. The total BER will be equal to the algebraic sum of the probabilities of bit errors in amplitude and phase as two independent events. The proposed algorithm for estimating BER is a separate analysis of the magnitude of the probability of errors due to phase and amplitude distortions. The analysis of the bit stream of data is carried out in regions A and B, respectively ( Figure. 4). On the basis of the obtained values, separately for the zero level and the unit level, the RMS deviation of the random variable A (RMS) is calculated from the signal amplitude: The mathematical expectation A is known: this is either the logical unit level or the logical zero level. The random variable i is the instantaneous amplitude of the signal, n is the number of instantaneous amplitude measurements. The number of samples is predetermined. Thus, the probability density function is determined for each of two cases: where A is the instantaneous amplitude of the signal.
Next, the probability density is integrated over the range corresponding to the case of error generation at the intersection of the receiver response level for each case: (2a) for the "one" level and (2b) for the "zero" level. The probabilities obtained are multiplied by the number of bits in the pattern and added (3).
Where A 0the probability of an error in the transfer of zero bit, A 1the probability of an error in the transmission of a one bit, Athe total error probability, the threshold level of the receiver trigger switching.
BER analysis by phase. In Figure. 5 illustrates the distribution of data phases P_DATA and phases of the clock signal P_CLK at the input of the receiver. In this case it is necessary to satisfy the condition under which the data and clock edges are arranged relative to one another no closer than s_min -minimum setup time of the data signal. Analysis the relative position of the fronts of these signals to meet the minimum hold time h_min is similar.  Figure 5. Probability distribution of the phases of the data signal and the clock signal. The probability distribution of signal fronts is described by means of a normal distribution. The occurrence of an error can be considered as the simultaneous occurrence of two random events, for which the condition of time relations between the arrival of the clock signal and the data signal is not satisfied.
The RMS signals DATA and CLK, respectively, have the form: где mathematical expectation, the moment of arrival of the signal front corresponding to an ideal grid of clock signals.
The distribution of the probability density of the arrival times of the DATA and CLK signal fronts, respectively, is: where t is the arrival time of the signal front.
RMS deviation of the phase of the data signal and the clock signal are reduced to the total RMS by the formula: It is assumed that the phase of the data is unchanged, and the total RMS has a phase of the clock signal. In this case, BER is the probability of the edge crossing of the CLK signal of the minimum thresholds of the setup and hold times _ and ℎ_ . The resulting BER can be calculated from the formula: where T is the duration of one bit of data.
In integrated circuits, bitstream transmission produces deterministic jitter, partly due to intersymbol interference. In this case there is the background of the length of several bits results in a variation of the duration of a single bit interval ( Figure. 6).  Figure 6. Distribution of the probabilities of the phases of the data signal and the clock signal taking into account the deterministic jitter. As can be seen in the figure, the distribution has two maxima, which should be taken into account during the analysis. This distribution depends on the pattern of the transmitted bit code.
In this case, the sophisticated model takes into account the difference in the lengths of bit intervals, depending on the sequence of transmitted data. The algorithm analyzes the transmitted code, making bit patterns that take into account the history of several data bits. For example, if the length of the pattern is 5, the total number of templates will be 32. In this case, the length of the last bit depends on the sequence of the preceding four bits. Taking the data stream as infinite, the algorithm calculates the probability of the appearance of one or another template, giving them a weighting factor j : where D is the length of the pattern in bits, N is the total number of transmitted bits, j -The number of repeats of the jth template in the sending of the transmitted bits.
In this case, the probability density function for each of the cases will have the form: where tjthe mathematical expectation for each of the distribution variants.
Also, as it was described earlier, the RMS phases of the data signal and the clock signal are reduced to the total RMS according to the formula (8).
The presence of two or more distribution peaks since the arrival of data bits means that in the formula (4) will be used to its limits of integration according to each of the data signal distribution maxima. In this case, the RMS for each of the distributions is assumed to be the same. Then integration is performed according to the formula (11) for each of the patterns: where s_minj и h_minjminimum setup and hold times corrected according to the offset of the data signal distribution center for each of the cases.
Thus, the BER in the signal phase will be the algebraic sum of the BERs for each of the patterns, taking into account their weighting factors: where nthe number of distribution maxima.
The resulting path BER is a BER amount, calculated by the signal amplitude and phase of the signal: 4. Check and use of the methodology.
The technique was tested on the basis of SPICE modeling of the path connecting the transmitter and the receiver operating on the SpaceWire interface at bit frequencies up to 3.125 Gbit / s.