Effects of substrate heating and post-deposition annealing on characteristics of thin MOCVD HfO2 films

It is well known that Hf-based dielectrics have replaced the traditional SiO2 and SiON as gate dielectric materials for conventional CMOS devices. By using thicker high-k materials such as HfO2 rather than ultra-thin SiO2, we can bring down leakage current densities in MOS devices to acceptable levels. HfO2 is also one of the potential candidates as a blocking dielectric for Flash memory applications for the same reason. In this study, effects of substrate heating and oxygen flow rate while depositing HfO2 thin films using CVD and effects of post deposition annealing on the physical and electrical characteristics of HfO2 thin films are presented. It was observed that substrate heating during deposition helps improve the density and electrical characteristics of the films. At higher substrate temperature, Vfb moved closer to zero and also resulted in significant reduction in hysteresis. Higher O2 flow rates may improve capacitance, but also results in slightly higher leakage. The effect of PDA depended on film thickness and O2 PDA improved characteristics only for thick films. For thinner films forming gas anneal resulted in better electrical characteristics.


Impact on scaling on MOS gate stack
Over the last decade, MOS gate stack combination has undergone several changes. Conventional CMOS structure includes Polysilicon gate electrode, SiO 2 gate oxide and Silicon substrate. For the 45nm node and below, this combination had to be changed due to several factors. SiO 2 thickness has been scaled down in accordance with Moore's law ever since miniaturization started over half a century ago in order to ensure sufficient gate capacitance which affects the performance of the device. When the silicon dioxide thickness is reduced to less than 5nm, direct tunnelling occurs through the oxide leading to higher leakage currents. For the 45nm node and below, the SiO 2 thickness required had become less than 1nm, causing the leakage to become unacceptable [1]. While there are circuit techniques to overcome this leakage [2], these can only be temporary solutions. Using a thicker film with a higher dielectric constant is the most practical and long-term solution. SiON gate dielectrics [3], having k value between 4 and 7 were used till the 65nm node. Among the other high-k dielectrics a To whom any correspondence should be addressed.  [4,5], ZrO 2 [6,7], and Hafnium silicate [8,9] are the most promising ones based on their physical and electrical properties. It is known that since the 45nm node, Hf-based dielectrics such as HfO 2 have been implemented in the gate stack along with metal gate electrodes [10]. Polysilicon had to be replaced with metal gate electrodes due to several issues such as thermal stability in contact with high-k, and poly depletion effect which degrades the gate oxide capacitance [11]. Hence the dual-poly approach had to be replaced with dual-metal gate approach since different work-functions are required for NMOS and PMOS devices. One serious issue with high-k dielectrics has been the low carrier mobilities observed in high-k dielectric based MOSFETs, especially in the high-field regions. This has been addressed by using 'strained-Si' in the channel as in the 45nm node [10] which results in improved mobilities, and perhaps by using Germanium in the channel region in future [12]. Figure 1 shows the modifications in gate stack in traditional CMOS over the last decade.

Dielectrics for flash memory applications
While HfO 2 has been implemented in CMOS, there has been another area where it has been widely considered for. Charge-trapping flash memories such as NOR and NAND flash memories, consist of an inter-poly dielectric layer (also called blocking dielectric), a charge -trapping layer, and a tunnel dielectric layer ( fig. 2). For this, HfO 2 is believed to be a potential candidate for all the three layers. These devices require high-k materials for improved capacitance leading to better memory retention while maintaining low leakage densities [13,14]. In addition, this also enables the device to withstand higher operating voltages, thereby enhancing the programming and erasing speeds of the flash memory (Kim and Lee 2005). In the 2015 edition of International Technology Roadmap of Semiconductors (ITRS 2015), high-k materials are included as part of requirements for Flash Memory Technology, to be used as an blocking dielectric, in the next few years. Among the various potential candidates for Non-volatile memory, HfO 2 is considered as one of the most suitable candidates.
In spite of the fact that HfO 2 has been studied extensively in the past, there is not much study in the 9-25nm thickness regime -especially certain aspects such as effects of substrate heating, post deposition anneals, and effects of constant voltage stress on electrical characteristics. As this thickness is also suitable for flash memory applications, it becomes important to understand the behaviour of HfO 2 in this thickness regime. In this work, HfO 2 films were deposited by MOCVD on Silicon substrates. The effects of substrate heating and O2 flow rate while depositing HfO 2 on the electrical and physical characteristics of HfO 2 films are presented. In addition, effects of post deposition annealing ambient on electrical properties are also presented.

Experimental Details
Metal -Oxide -Semiconductor capacitors (N-MOSCAPs) were fabricated using p-type Si (100) substrates with a resistivity of 1 -10 cm. The wafers were cleaned using standard RCA cleaning followed by a dilute HF-dip. HfO2 was deposited by MOCVD using Applied Materials' Centura. The precursor flow rate is 20mgm, while the oxygen flow rate was varied between 200 -500sccm. The substrate temperature was varied between 400ºC and 700ºC, while the pressure was kept at 6 Torr. After film deposition, selected samples were annealed in O 2 or Forming gas ambient or both. After PDA, Aluminium metallization was done using shadow mask.
The material characterization was performed by determining the refractive-index and thickness using an Ellipsometer (SE800). The electrical measurements were carried out using the Semiconductor Parameter Analyzer (Agilent 4155C), LCR meter (Agilent 4284), and the Semiconductor Characterization System (Keithley 4200). The Capacitance-Voltage characteristics were determined at 10 kHz -1MHz, with the applied AC voltage peak-to-peak signal level of 50 mV. Equivalent oxide thickness (EOT), Interface state density (Dit), and flatband voltage (Vfb) were obtained using CVC Hauser program.

Effect of substrate temperature on thickness and film quality
One of the key variables in an MOCVD process is the substrate temperature. Figure 3 shows the physical thickness and refractive index under varied substrate temperature. It was observed that the film thickness decreased with increasing substrate temperature indicating that the films deposited at higher temperatures have more density. The films were subsequently annealed in O 2 ambient at 500°C for 15 seconds. Refractive index obtained in as-deposited films were observed to be very close to reported values of 1.9 -2.0 [15] indicating good quality HfO 2 films. It can be observed that annealing reduces physical thickness in all cases probably due to further densification of deposited film [16]. This results in improved film quality after PDA. Films deposited at higher substrate temperatures also showed much higher dielectric constant and significantly lower EOT (Table 1). This is understandable because at lower substrate temperatures, the organic precursors of Hafnium leave behind small amounts carbon contamination in the films [17] which reduces overall k-value of HfO 2 . At higher temperatures these contaminants are removed [17] by the formation of CO 2 . The lowering of the kvalue for the 700°C sample is most likely due to formation of a thin interfacial layer (probably HfSiOx) between HfO 2 and Si substrate [18]. For the sample deposited at 400°C the carbon impurity is removed upon subsequent O 2 anneal. This is corroborated by the improvement in refractive index after O 2 anneal for this sample. For the samples deposited at 600°C and 700°C, the slight reduction in refractive index after O 2 annealing is attributed to the formation of the above mentioned interfacial layer. The observed improvement in overall dielectric constant of these samples is attributed to higher density HfO2 films free from carbon contamination.

Effect of substrate temperature on C-V characteristics
The C-V characteristic of the films deposited at different temperature has been shown in Figure 4a. The sample deposited at 500C was found to be defective. The maximum capacitance value has increased with increasing temperature due to densification at higher temperatures. But the important pattern to be noted here is the shift in the flatband voltage towards zero with increasing temperature (fig. 4b). This reflects removal of carbon impurities from film and the resultant reduction in fixed charges in the film at higher substrate temperatures. The reduction in hysteresis at higher temperatures also indicates reduction in fixed charges in film ( fig. 4b) [5,8,17].

Effect of post deposition annealing on C-V characteristics
The effect of annealing was found to be dependent on film thickness. For thicker films, sufficient PDA is required to fully oxidise the film and capacitance improves with annealing as a result ( fig. 5a). It can be seen in the figure that the shape of CV for the 35nm film in accumulation improves upon annealing, but is still not matching with the simulated CV indicating that the film is still not yet fully oxidized. But on the other hand, for thinner films, O 2 PDA results in lowering of capacitance owing to the formation of a SiO 2 -like interface ( fig. 5b) [18]. The shape of the CV even without O 2 anneal is also quite typical suggesting a fully oxidized film even before PDA.  Now since O 2 anneal cannot be used for thinner films, Forming gas anneal was tried (400°C, 20mins) as a PDA for the 12nm film. The results obtained can be seen in Figure 6 which shows a comparison of CV of the un-annealed film with the ones annealed in O 2 and Forming gas. As seen previously, the O 2 anneal resulted in a thick interface formation and subsequent reduction in capacitance. On the other hand, with forming gas anneal, it was observed that the accumulation capacitance reduces slightly perhaps due to the reducing environment of forming gas. But more importantly, forming gas anneal considerably improves the slope of the CV curve as seen from the inset in the figure. Forming gas is known to cause hydrogen passivation of oxide-silicon interface thereby reducing the dangling bonds [19] which leads to reduction in the interface state density

Effect of O 2 flow rate (during HfO 2 deposition) on film properties
The effect of O 2 flow rate during CVD on the film characteristics was studied. Fig 7a shows the effect of O 2 flow rate on film thickness and refractive index of HfO 2 films. As the O 2 flow rate is varied from 100sccm to 500sccm (while keeping other parameters constant), the HfO 2 thickness varies very slightly from 19nm to 20.6nm, which is attributed to higher reaction rate in presence of more oxygen. Meanwhile, the refractive index is more or less unaffected (variation between 2.05 and 2.01 is within measurement error). The important thing is to see if there is any variation in electrical characteristics.  Figure 8(a) shows the hysteresis of the hafnium oxide films under different O 2 flow rates. It can be seen that while higher O 2 flow rates can marginally lower the hysteresis values, the samples without PDA have significantly larger hysteresis values than the samples with PDA. PDA helps remove the ionized charges in the film which are present close to bottom interface. PDA also helps remove carbon contamination. Higher O 2 flow rates lead to slightly higher leakage which arises probably as a result of higher capacitance (fig. 8b).

Summary and Conclusion
HfO 2 films were deposited on Silicon substrates using MOCVD. The effects of substrate heating on the electrical and material characteristics of HfO 2 were studied. It was observed that higher substrate temperatures resulted in thinner films with higher density. However, the 700ºC deposition also resulted in formation of thick interfacial layer causing deterioration of overall dielectric constant. The highest k value obtained was around 22 at 600ºC substrate temperature. Higher deposition temperatures also resulted in shifts in V fb closer to zero and significant reduction in hysteresis indicating that fixed charges and carbon contamination can be minimized by going to higher substrate temperatures. The effect of PDA on the device characteristics was studied and it was found that it depended on the thickness of the HfO 2 film. For example, for a 35nm HfO 2 film, O 2 annealing results in fully oxidizing the film and thereby improves capacitance and V fb . But for a 12nm HfO 2 , O 2 annealing results in decrease in overall capacitance due to interfacial layer formation. For the HfO 2 films thinner than 12nm, annealing in forming gas helps reduce interface states by H-passivation and results in better CV characteristics. The effect of O 2 flow rate on film characteristics was studied. It was observed that having a higher flow rate improves the capacitance and V fb values. At higher flow rates, the film is fully oxidized and the carbon contamination and fixed charges are reduced leading to improved capacitance. However, at higher flow rates, the films were found to be slightly leakier. In conclusion, it was observed that process parameters have significant impact on electrical characteristics of MOCVD HfO 2 . For ideal MOS capacitor characteristics, using a substrate temperature of 600ºC along with O 2 flow rate of 500sccm gives the best film in terms of k-value for the thickness range studied. Further annealing in O2 ambient is recommended for thick films, while doing PDA in an inert ambient such as N2 is recommended for thinner films. Performing a forming gas anneal before or after the gate electrode deposition is critical for improving the interface quality without sacrificing the capacitance much.

Acknowledgement
Part of the work presented here was carried out at the Center of Excellence in Nanoelectronics, Indian Institute of Technology, Bombay as part of the Indian Nanoelectronics Users' Program (INUP) which is sponsored by the Department of Information Technology, Ministry of Communications and Information Technology (Government of India). We would like to sincerely thank Professor Anil Kottantharayil and Professor Juzer Vasi of IIT Bombay along with their graduate students for their help and support without which this work would not have been possible.