Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.


Introduction
There does not seem to be any fundamental physical limitation that would prevent Moore's Law from characterizing the trends of integrated circuits. However, sustaining this rate of progress is not a straightforward achievement [1][2][3][4]. Figure 1 shows that the trend of power supply voltage, threshold voltage, and gate oxide thickness versus channel length for high performance CMOS logic technologies [5]. Sub-threshold non-scaling and standby power limitations bound the threshold voltage to a minimum of 0.2V at the operating temperature. Thus, a significant reduction in performance gains is predicted below 1.5V due to the fact that the threshold voltage decreases more slowly than the historical trend, leading to more aggressive device designs at higher electric fields [6, 7]. As the channel length is reduced to increase both the operation speed and the number of components per chips the SCE will arise. The critical geometry parameters which determine device short-channel behaviours spatially Vth roll-off are gate length, fin thickness, fin height, Tox and channel doping [8]. The decrease of Vth with decrease in L is a well-known SCE. For shorter channel lengths, the value of Vth reduces. The effect of short channels becomes more pronounced as the channel length is reduced further. Short channel device has channel length which is comparable to depth of drain and source junctions and depletion width and causes threshold voltage and I/V curve variations [9,10].
Due to excellent control of the SCE, lower gate leakage current, higher on-current, and better subthreshold slope, symmetrical double-gate silicon (DG) MOSFETs with extremely short-channel length have the appropriate features to constitute the devices for nanoscale circuit design [11][12][13]. As for bulk MOS devices, the SCE threshold voltage is important for assessing device performance and gaining insights into device designs. Compared to single-gate devices, the Vth of the DG devices may be difficult to define due to the co-existence of the front and the back channels [14][15][16].
In general, the Vth of a MOSFET is independent on either L or gate width (W). However, when the L or W is reduced to dimensions that are comparable to the edge-affected region, then the Vth experiences dependence on the L or W. The equation of Vth is given as in (1), assumes that bulk depletion charge is only due to the electric field created by the Vg, while the depletion charge near n+ source and drain region is actually induced by PN junction band bending.
Therefore, the amount of bulk charge the Vg support is overestimated, leading to a larger Vth than the actual value [15]. When L becomes smaller, the Vth begins to decrease due to the two-dimensional field effect of the drain junction. Vth changes due to the reduction of charges in the depletion layer for reduction of L. For shorter L, the value of Vth reduces. The conventional process such as ion implantation cannot be used to control Vth of a vertical MOS transistor [17,18].
The gate-oxide capacitance per unit area is defined as where ox  , is the permittivity of oxide and Tox is the oxide thickness. As the Tox is decreased, less Vg is required for strong inversion. The oxide capacitance increases with the decrease in Tox and the oxide capacitance is directly proportional to the Vth. The parameters of Vth increase with reducing the L or increasing the channel thickness [8]. In short-channel devices, the centre of the channel has higher electrostatic potential than anywhere because of the influence of the source/drain potential and the weak gate control below threshold, becoming the leakiest path. The short-channel devices that for appropriate device structure parameters and bias conditions, a normally-off device may also be turned normally-on if the L is made shorter than the previous one [14].
The probability of electron occupancy of an allowable state is based on the doping level in semiconductor. As the substrate doping increases, the initial threshold voltage increases and the short channel threshold shift also becomes larger. Vth roll-off also depends on Na. As the thickness of oxide is decreased, less Vg is required for strong inversion [19]. Based on the carrier concentration at the minimum channel potential located at a depth x of the channel, an analytical expression of the subthreshold slope has been derived in terms of the natural L [20,21].
In this paper, the relationship between parameters that affect the threshold voltage is being investigated. These changing trend of threshold voltage will be visualised to see whether the targeted parameters are improving or withholding the device performance.

Modelling of SCE
Main focus of this study is to model the phenomena of SCE in 60nm NMOS transistor and its relationship with the affected parameters in device performance. The values of Tox, Na and L were varied to study the effect of these parameters on the short channel Vth. The Cox, potential, xdT width and Vth are calculated using formula that models the SCE phenomenon. The changing trend of Vth with respect to independent parameters are then visualised using Sentaurus TCAD. The phenomena were specified to the Vth of SCE and study the effect of parameters in the Vth equation as shown in (2).
The Cox and xdT can be determined using (3) and (4), respectively: Where = 0 , Vth is the threshold voltage, rj is the junction depth of drain and source, L is the length of gate, Cox is the oxide capacitance, is the dielectric constant of silicon dioxide (SiO2), 0 is the vacuum permittivity, Tox is oxide thickness, Na is the concentration of acceptor atoms and ni is the intrinsic carrier concentration.

Determination of Vth against Na for different L
The Vth is determined by varying the value of Na, and the other two variables Tox and rj are fixed for several values of gate length. In this case, both Tox and rj were set at 25nm, whereas L was varied from 10nm to 130nm.

Determination of Vth against Tox for different L
Next, the Vth is determined by varying the value of Tox, with both Na and rj were set at 1×10 16 cm -3 and 25nm, respectively. Similar in the case of sub section 2.1, L was varied between 10nm to 130nm.

Determination of Vth against L for different Na
Thirdly, the Vth is determined against various L while both Tox, and rj are fixed. Vth is calculated against L for Tox=25nm and rj=25nm, whereas Na was set in the range of 1.4×10 15 cm -3 and 1×10 17 cm -3 .

Determination of Vth against Tox for different L
Next, the Vth is determined against various Tox while both L and rj are fixed. In this case, L and rj were set at 60nm and 25nm, respectively. Na was set in the range of 1.4×10 15 cm -3 and 1×10 17 cm -3 .

Determination of Vth against Tox for different L
Fifthly, the Vth is determined by varying the value of L. Na and rj were set at 1×10 16 cm -3 and 25nm, respectively and Tox was in the range between 10nm and 65nm.

Determination of Vth against Tox for different L
Finally, the Vth is determined by varying the value of Na with both L and rj were set at 60nm and 25nm, respectively. The range Tox in this case was between 10nm and 65nm.
In each case, the simulation was carried out in Sentaurus TCAD starting from Sentaurus Workbench (SWB), which determining the changing parameters, up to the Inspect, a tool to visualise the electrical characteristic of the NMOS transistor. The whole process is depicted in Figure 2.

Results and discussion
In this section, the device performance will be presented in the presence of SCE according to six cases of study outlined in Section 2. There are five graphs presented to visualise the effect of these parameters over Vth. Those graphs were plotted based on numerical simulations carried out in the Sentaurus TCAD.

Vth against L with varying Na
The values of each parameter used for simulation were recorded in Table 1. Figure 3 shows the trend of Vth changes against L for various Na.   Figure 3, it is observed that the Vth in both graphs changes sharply when L is less than 60nm. Beyond this point, the fluctuation of the Vth is comparatively less. The Vth changes due to the reduction of charges in the depletion layer for reduction of L. It is also worth to note that as the Na increases the Vth decreases. In general, the Vth obtained is higher when Na = 1×10 16 cm -3 compared with Na = 2×10 16 cm -3 .

Vth against L with varying Tox
The values of each parameter that used for simulation were recorded in Table 2 and the associated graph is shown in Figure 4.   Referring to Figure 4, the trend of Vth is almost similar with the trend shown in Figure 3. In general, as L becomes smaller, the value of Vth reduces significantly. It is also observed that the Vth falls with the increasing of Tox. This observation suggests that as the Tox increases, the gate control over the channel diminishes leading to an increase of short channel effects towards the Vth.

Vth against L with varying Tox
The values of each parameter that used for simulation were recorded in Table 3 and the associated graph is shown in Figure 5.   Figure 5, it is observed that the Vth increases a bit before drops significantly as Na increases. For L = 45nm, the increment of Vth is notable when Na is between 10 15 and 10 16 before it decreases as Na increases to 10 17 . For L = 60nm, Vth is almost unchanged when Na is between 10 15 and 10 16 and starts to decrease as Na increases to 10 17 . The decrement of Vth is due to the higher number of free carriers as the number of dopant increases. These carriers are contributing to higher possibility of drive current to exist in the transistor channel.

Vth against L with varying Tox
The values of each parameter that used for simulation were recorded in Table 4 and the associated graph is shown in Figure 6.  Figure 6. Changing of Vth for different L and Tox Figure 6 illustrates the curve of Vth as the Tox changes from 25nm to 40nm. Observation in Figure 6 shows that as the Na increases, the Vth decreases for both cases of Tox values. In both cases of Tox, Vth is almost flat when Na is between 10 15 and 10 16 before it drops significantly as Na increases to 10 17 . This observation suggests that as Na increases, so too the number of free carriers in the channel. As free carriers flooding the channel, the potential barrier will lower and thus drive current will starts to flow in the channel.

Vth against Tox with Varying Na
The values of each parameter that used for simulation were recorded in Table 5 and the associated graph is shown in Figure 7.  This observation suggests that as the Tox is decreased, less gate voltage is required for strong inversion. Since Tox is inversely proportional to the Vth, therefore the oxide capacitance will increase as Tox decreases. It is also noted that the Vth drops more than double as Tox increases by 50nm. This shows strong effect of Tox over Vth in the presence of SCE in NMOS transistor.

Conclusion
In this work, modelling of SCE has been carried out and investigation of SCE over the transistor performance is presented. The transistor performance is benchmarked at Vth and simulated against three parameters; L, Na, and Tox. Observation on simulation results show that the Vth is directly proportional to L and inversely proportional to both Na and Tox. The presence of SCE in 60nm transistor shows the Vth is highly dependent on those three parameters; L, Na and Tox. Improvement in device performance, as suggested by the simulation results, can be achieved by increasing the channel length, and reducing both the Na and Tox beneath the gate terminal.