The NA62 liquid Krypton calorimeter's new readout system

The NA62 experiment [1] at CERN SPS (Super Proton Synchrotron) accelerator aims at studying Kaon decays with high precision. The high resolution Liquid Krypton (LKr) calorimeter, built for the NA48 [2] experiment, is a crucial part of the experiment photon-veto system; to cope with the new requirements, the back-end electronics of the LKr had to be completely renewed. Due to the huge number of the calorimeter readout channels ( ∼ 14 K) and the maintenance requirement over 10 years of the experiment lifetime, the decision to sub-contract the development and production to industry was taken in 2011. This paper presents the primary test results of the Calorimeter REAdout Module (CREAM) [3] prototype delivered by the manufacturer in March 2013. All essential features, analog performance, data processing and readout, are covered.


The NA62 experiment
The NA62 experiment at CERN will study several Kaon decays with unprecedented statistics. Its main goal is the measurement of the ultrarare K + → π + νν decay's branching ratio (BR), whose precise theoretical prediction within the Standard Model (SM) framework [4] has a sub-10% total error but can presently be compared with an experimental measurement based on seven candidate events [5] only. The collection of about 100 events with ∼ 10% background will allow to test the SM in a complementary way to LHC studies, and to probe the presence of new physics.
A view of the NA62 experiment is shown in figure 1. Kaons produced by the 400 GeV/c SPS protons inpinge on a Beryllium target; outgoing charged particles are selected in a 75 ± 1% GeV/c momentum band. Before the decay region, Kaons are identified by the Cedar, a Helium-filled Cherenkov detector, with 10 −3 inefficiency, and their momentum and direction measured with high precision by the Gigatracker, made of 3 silicon pixel stations. The CHANTI detector vetoes particles produced by inelastic scattering of beam particles in the last Gigatracker station.
The veto system aims at measuring particles from several Kaon decays (especially π 0 s, whose detection inefficiency must be be < 10 −8 ) that would otherwise be a BG for the K + → π + νν decay. It is made of 12 Large Angle Veto stations (LAVs) along the beamline, made of lead-glass crystals from the OPAL [6] calorimeter, the Liquid Krypton (LKr) calorimeter, described in detail in section 2 and the IRC and SAC, two Shashlik-based detectors used to increase the LKr calorimeter acceptance at low angles and to detect photons decaying along the beamline, respectively.
The Straw system, made of 4 chambers, measures momenta and directions of secondary charged particles with high precision. The RICH detector provides Pion identification at 5 · 10 −3 inefficiency, and the MUV system yields pion energy measurement (MUV1+2, iron/scintillator sandwich) and muon rejection (MUV3, scintillator tiles).
-1 - BG rejection of the K + → π + νν decay is obtained by selecting two regions of the M 2 miss = (P K − P π ) 2 variable distribution, whose computation requires the measurement of the incoming Kaon and Pion four-momentum by the Gigatracker and by the Straw system, respectively.
Three trigger levels will be implemented to reduce the 10 MHz Kaon decays in the fiducial region down to the 10 KHz events written on disk, each level reducing the data load by about one order of magnitude. The first trigger level (L0T) is FPGA-based and will use the TEL62 board [7], developed by the NA62 collaboration and based on the TELL1 board [8] used in the LHCb experiment. The latency of the L0T decision will be fixed and equal to about 1 ms.
The other two trigger levels will be performed by a PC farm and their latency is not fixed. The second level trigger (L1T) algorithm will take a L1T decision using data collected at L0 in ∼ 1 s and distribute the L1T signals to the detectors that didn't send their data to the PC farm before. After this data is collected, the third trigger level algorithm (L2T) is applied, its latency being as long as the SPS cycle. Events accepted by the L2T are written on disk.
2 The NA62 liquid Krypton calorimeter NA62 will reuse the quasi-homogeneous LKr calorimeter built for the NA48 experiment (figure 2). Its goal is to veto particles from BG decays, as part of the NA62 veto system, and to measure electromagnetic energy deposits with high precision. The calorimeter is made of ∼ 10 m 3 liquid Krypton at 120 K, housed inside a cryostat. The LKr volume is divided into 13248 2 × 2 cm 2 cells by Cu-Be electrodes, which have a pointing geometry and a zig-zag shape to minimise response inhomogeneities when the particle shower is too close to the anode (figure 3).
The signal produced by a particle crossing the LKr is collected by preamplifiers mounted inside the cryostat, directly attached to the calorimeter strips, and is then sent out using 50 Ω coaxial cables and feedthroughs on the top of the cryostat. The signals are then sent to the transceiver boards, plugged directly on the feedthroughs and sharing the Faraday cage made by the cryostat. The board performs a pole-zero compensation, recreating the ∼ 20 ns rise time and ∼ 2.7 µs total length triangular signal shape given by the calorimeter cell, previously shaped by the τ = 150 ns decay constant of the preamplifier. The output signal is sent to the readout system through cables housing 16 twisted pairs each.
-2 -  To control the response uniformity and stability of the whole calorimeter, a calibration system based on about 2000 pulse generators has been implemented. Each generator produces an exponentially decaying signal that serves 8 channels; its pulse height is set by a 15 bits DAC.

The CREAM module
The CREAM, shown in figure 4, is a 6U VME 64 board developed by CAEN, under specifications provided by the NA62 and the PH-ESE CERN groups. It consists of a daughterboard, where the analog input signals are shaped and digitised, and a motherboard, where the data is processed and eventually sent out if the required trigger conditions are met. The CREAM will replace the old calorimeter's readout system [9], unable to cope with the demanding NA62 requests in terms of rate sustainability and trigger logic.
Each CREAM board reads 32 LKr channels (2 cables) plugged on the front panel. A total of 448 CREAMs are needed to read all LKr cells, requiring 28 VME crates (up to 16 CREAMs/crate are needed, depending on the LKr geometry. A crate can host up to 19 CREAMs) housed in 8 racks located above the LKr cryostat. A fully equipped crate is shown in figure 5.

I/O signals and data
The CREAM receives the optical TTC signal through the TTC-LKr board [11], developed by the CERN PH-ESE group and placed in the 11th slot of each VME crate. The TTC [10] is a unidirectional optical fiber based transmission system where two channels, A and B, are multiplexed and encoded using the LHC 40.08 MHz clock (40 MHz hereafter) and transmitted at 160 MHz rate. One channel is used to carry the L0T signal only, while the other carries the information concerning resets, trigger type, calibration and monitoring. The TTC-LKr board turns the TTC information into M-LVDS signals and distributes them to all CREAMs using a custom P0 backplane, which is also used by each of the 16 CREAMs to signal the presence of a CHOKE or ERROR condition, as described in section 3.3.
Output data are delivered through two RJ45 connectors on the front panel. The first (the data link, DL) features a 1 Gbit/s Ethernet I/O link, while the second (the trigger sum link, TSL) is used -3 -  to deliver the LKr information to the LKr L0 processor. A switch collects data from the DL of all CREAMs in one crate and sends it to the NA62 PC farm through a 10 Gbit/s optical link. The type of data sent through these two links are described in section 3.3.

Configuration
The CREAM configuration interface is provided via the VME bus. A PC equipped with a 4 optical link PCIe card can control up to 8 daisy-chained VME bridges per link, thus handling the configuration of all CREAMs. A set of configuration libraries developed by CAEN is available; the board firmware can be updated through the VME backplane or through JTAG.

Firmware properties
A schematic view of the CREAM block diagram is shown in figure 6. After being shaped from triangular into pseudo-gaussian, 70 ns wide, by a shaper, the input signals are sampled using the 40 MHz clock by four 14-bit, 2 V pp range, 8-channel serial output ADCs [12], placed on the daughterboard. The baseline of each channel can be set by a 16 bit DAC to fully exploit the available dynamic range. The digitised samples are then sent to an Altera Stratix IV FPGA mounted on the motherboard; here data is continuosly copied on a circular 256 Mbit buffer (corresponding to 12.5 ms of acquisition time, whereas the latency required by the experiment will be of about 1 ms) implemented in a 8 GB storage capacity DDR3 SODIMM module. The CREAM data flow is shown in figure 7. When the CREAM receives a L0T signal, a configurable number of samples (up to 256) is extracted from the circular buffer at fixed, but configurable, latency and copied into the L0 buffer, also implemented in the DDR3. An ID number and a timestamp (in 25 ns units), that uniquely indentify the event, are associated with each trigger. The L0 buffer can contain up to 16 seconds data-taking (> SPS spill duration) at the nominal L0T 1 MHz rate and for 8 samples/channel per trigger for all channels.
A L1T decision is notified to the CREAM through a UDP packet sent to the DL; CREAM data corresponding to the requested event number, formatted as UDP packets, is sent to the PC farm through the same link. A zero-suppression mode, triggered by a flag in the L1 request packet, has -4 -  been implemented: in this mode the CREAMs will send out only data of those channels having at least one sample above a configurable threshold value.
The information from CREAMs cannot be fully exploited to take a L0T decision, because the bandwidth required to move the corresponding data to the L0T processor would be too large. For this reason the sums of the digitised signals from 4 × 4 cells are serialized by the CREAM every 25 ns and sent out through the TSL. The serialised data is collected by a TEL62 board via the TELDES daughterboard [13], currently under development. The LKr L0 processor implemented in these FPGAs will look for maxima in energy deposits in space and time and compute the total energy in the calorimeter or in parts of it (e.g. quadrants or stripes). This information will then be used for the final L0T decision.
In addition to the lines used to deliver the TTC information to the CREAMs, the P0 backplane also hosts 20 CHOKE and 20 ERROR single ended CMOS lines, one for each CREAM slot. A CHOKE line is driven high to indicate that the module memory is overloaded with data and approaching a situation in which triggers cannot be served without losing data. The assertion of a CHOKE signal is notified by the LKr-TTC to the L0T central processor, that stops the L0T dispatching. When the overloading problem is solved, the CHOKE signal is driven low and the L0T dispatching can restart. In a similar way, if, in spite of the choke signal, L0Ts cannot be served, or if a generic error occurred, an ERROR signal is raised.

Analog signal tests at CERN
Four CREAM modules were delivered at CERN in March 2013 with a preliminary version of the firmware. A full characterization of the module was carried out at CERN in order to test the performances of the analog system processing. Along with the triggered data selection mode, a continuous sampling mode, required to perform the tests, was implemented.
-5 -  Tested parameters include: • Effective number of bits (ENOB): in order to compute the ENOB of each channel the following procedure was adopted: a 5 MHz differential sine wave was generated using a Tektronix AFG 3252 dual channel generator; spurious frequencies were eliminated using narrow-band 5 MHz pass filters; the sine wave was fed into the CREAM's channels, and the digitised data collected on PC; the FFT of the digitised sine wave was computed (figure 8), and hence its SINAD and ENOB; the measured ENOB mean value, as shown in figure 9, is within the specifications (ENOB < 10 LSB); • Cross-talk: the same experimental setup used for the ENOB measurement was used to study the cross-talk induced on neighbouring channels. One of the 32 channels of a CREAM was fed with a 5 MHz sine wave and the ratio of the FFT 5 MHz component of the pulsed channel's and the neighbouring channels' signal was computed.
Only the two closest channels to the pulsed one show a pick-up slightly above specifications, amounting to −67/ − 68 dB whereas < −70 dB was required; • Non-linearities: in order to evaluate the differential (DNL) and integral (INL) non-linearities, the statistical metod described in [14] was used. A sine wave of period slightly differing from 5 MHz (not multiple of the clock frequency) and of amplitude slightly higher than the dynamic range allows to populate all ADC values, and, given the number of events, the theoretical distribution in case of perfect linearity can be computed. Differential and integral -6 -  non-linearities (figure 10) are then computed as follows: Where i runs over all 2 14 possible ADC values and H exp (i) and H theo (i) are the entries of the i-th bin acquired and according to theory, respectively.
The measured non-linearities, as shown in figure 11, are well within specifications (|DNL| < 2 LSB, |INL| < 5 LSB); • Signal width and uniformity: the shaped signal was required to have a 40 ns rise time, and its FWHM to be 70 ns ± 10% wide, with ±1% uniformity. In order to test these parameters, a calorimeter-like differential signal was reproduced using a function generator and its output was fed into the CREAM channels. By synchronizing the input signal and the L0 trigger sent to the CREAM, the 8 samples corresponding to the shaped pseudo-gaussian signal were selected. The signal was then fitted with a gaussian, and the sigma of the distribution obtained by accumulating several such events was computed (figure 12); • Non-coherent and coherent noise: in order to estimate the coherent noise, the pedestal value of each channel is measured; in the following the pedestal mean value is removed from the measurement. Two groups of 16 channels, even and odd ones respectively, are formed. The distribution of the sums of the two groups yields the total noise σ SUM ( figure 13, left), while the distribution of the difference between the two groups yields the total non-coherent noise σ DIFF (figure 13, right), to be divided by √ 32 in order to have the non-coherent noise/channel:  The coherent noise/channel can then be obtained by quadratically subtracting the two above quantities, and dividing by 32: Non-coherent and coherent noise are both within the specifications (σ NCOH < 2 LSB, σ COH < 10% · σ NCOH ).

Test runs at CERN, project status and future plans
Several tests were performed over the last months or are scheduled in order to test the CREAMs in data-taking conditions: • in November 2012 signals from 8 LKr calorimeter cells were digitised by a CREAM daughterboard and collected through a custom readout system, the motherboard not being available at the time. The signal produced by real particles was thus investigated, this being the only occasion before the the start of the NA62 data-taking period due to the SPS long shutdown until October 2014; • in July 2013 two CREAMs were succesfully tested within the final experimental framework.
In particular, CREAMs were tested as part of the NA62 data network, as L1T request packets were issued by the PC farm and reached the CREAMs on a different network segment, and data produced by the CREAMs were correctly sent to the requesting PC and written on disk; • in October 2013 1 the CREAM preproduction batch was delivered at CERN. These boards will allow to instrument a whole crate during the NA62 test run scheduled in November 2013.
Several functionalities of the firmware will be tested, among which the zero-suppression mechanism, the trigger sum links and the delivery of special triggers. The CREAM will also be tested at rates close to the nominal ones.
The delivery of the full CREAM production is foreseen in two batches of 220 boards each, expected to be at CERN by the first months of 2014. The whole LKr readout will be installed and commissioned in spring/summer 2014, while the NA62 data-taking phase is scheduled to start in October 2014.