The upgrade of the CMS electromagnetic calorimeter for HL-LHC

The High Luminosity upgrade of the Large Hadron Collider (HL-LHC) at CERN aims to achieve unprecedented levels of instantaneous and integrated luminosities, approximately 5 × 1034 cm-2 s-1 and 3000 fb-1, respectively. It is anticipated that each bunch-crossing will result in an average of 140 to 200 collisions (pileup). The lead tungstate crystals and avalanche photodiodes (APDs) in the barrel region of the electromagnetic calorimeter (ECAL) of the Compact Muon Solenoid (CMS) will remain effective. However the readout and trigger electronics will undergo complete replacement to keep the current level of performance. A dual gain trans-impedance amplifier and an application-specific integrated circuit will be installed, providing two 160 MS/s analog-to-digital converter channels, gain selection, and data compression. The increase in noise within the APDs, due to radiation-induced dark current, will be alleviated by reducing the operating temperature of the ECAL. Additionally, the trigger primitive formation will be shifted away from the detector and handled by powerful and flexible field-programmable gate array processors housed on the back-end electronics cards. In this document, the complete ECAL barrel readout chain design and the current state of research and development for each individual component regarding the upgrade will be described. The outcomes of recent test beam campaigns conducted at the CERN SPS, exploiting electron beams with energies of up to 250 GeV, will also be summarized. Notably, measurements pertaining to the energy resolution performance of the latest prototypes of HL-LHC ECAL readout electronics will be presented.


HL-LHC and the ECAL upgrade
To achieve the goals of High Luminosity upgrade of the Large Hadron Collider (HL-LHC), CMS needs to increase the Level 1 (L1) trigger rate from 100 kHz to 750 kHz.In order to include more advanced trigger algorithms and handle an increase in the data granularity of the upgraded CMS detector, L1 triggers latency will be extended from 4 µs to 12 µs.The legacy electronics system (used in Run 1, 2 and 3 [1] of Phase I) will not be able to sustain these new conditions and it has to be replaced.Another reason for the electromagnetic calorimeter (ECAL) upgrade comes from the avalanche photodiodes (APDs) which ECAL has adopted as crystal readouts in the barrel.When hadrons hit an APD two negative effects are possible: direct ionization in the active material with the generation of a false physics signal (also called spike) or bulk damage with consequent increase of dark current (and so of the signal noise) enhanced by the higher luminosity of LHC.For instance, the expected trigger rate induced by such anomalous signals above 20 GeV is about 1 MHz, which, if not suppressed, would badly saturate the ECAL trigger bandwidth.For these reasons countermeasures have to be taken in the ECAL Phase 2 upgrade [2].The ECAL Very Front End (VFE) electronics will use a faster signal shaping and a sampling finer than in Phase I which will allow an improvement in the spikes recognition and rejection.Furthermore, in order to maintain the APD dark current increase under control, the ECAL barrel will be kept at a temperature of 9 • C (instead of the present 18 • C), thus mitigating negative effects on time and energy resolution.As a consequence of these upgrades, ECAL will also be able to provide excellent time resolution (up to 30 ps for energy higher than 50 GeV).Preshower and the Endcaps sections will be completely replaced by a silicon based High Granularity Calorimeter (HGCAL, which will not be discussed in this document) since they would not sustain the HL-LHC radiation levels.

On-detector electronics
In the legacy system, a matrix of 5×5 crystals forms a readout channel (or tower).Electric signals from the APDs of a row of 5 crystals are read by a VFE board and digitized.The 25 lines from 5 VFEs are collected by a Front End card (FE) which, by means of simple algorithms, extracts the energy -1 -and generates a trigger primitive (TP) for the Level-1 trigger.Data, triggers and commands follow three different paths and are connected to dedicated off-detector electronics boards.For mechanical constraints, the system will use the same schema (5 VFEs connected to a FE) and card sizes during Phase 2, but the electronics mounted on them has been completely re-designed.

VFE electronics
In the new VFE (figure 1) each of the 5 signal lines passes through two custom application-specific integrated circuits ASICs called CATIA (CAlo-TIA) and Lite-DTU (Lisbon-Torino ECAL Data Transmission Unit [3]).The CATIA chip is equipped with two amplification lines (×1-10) which cover the dynamic range 50 MeV to 2 TeV.It also provides a signal shaping faster than legacy electronics.The Lite-DTU chip is equipped with a 12 bits 160 MS/s analog-to-digital converter (ADC) which provides four times the 40 MS/s sampling frequency used in the legacy system.Each gain line is sent to the Data Compression Unit which takes the highest not saturated gain sample and it transmits it, by a 1.28 Gb/s serializer, to the higher step of the DAQ chain.

FE electronics
Differently from the legacy system, the new FE board (figure 2) is not in charge of creating TPs or applying spikes suppression, tasks that will be moved to the off-detector electronics.The card collects data from 5 VFE cards using 4 Low Power Gigabit Transceivers (LpGBT) equipped with e-links at 1.28 Gb/s.At the same time it is able to communicate and configure VFE devices via I2C bus and distribute clock signals via electrical links.The FE card has a GBT-SCA chip [4] for collecting hardware temperatures and APDs dark currents values.Communication with the off-detector card is provided by a VTRx [5] chip with four uplink 10.24 Gb/s fibers and one downlink 2.56 Gb/s fiber.The average data compression applied by the VFE cards maintains the data rate low enough so that a single VTRx is enough.GBT-SCA, LpGBT and VTRx chips have been developed at CERN and have been tested to be radiation resistant for the HL-LHC levels [6,7].

Off-detector electronics
Unlike in the legacy system, all data and control processing is moved off-detector on the Barrel Calorimeter Processor Card (BCP), which will be equipped with a powerful field-programmable gate array (FPGA) processor.It is in charge of controlling the on-detector electronics, distributing the clock and fast signals, decompressing digitized data, buffering data until the Level 1 trigger accept, transmitting packages to the DAQ system, generating and transmitting trigger primitives to the Level 1 trigger system.Trigger primitives will be generated per each channel increasing the trigger granularity.The more recent ATCA standard is used in place of the VME of the legacy system.A mezzanine for the power control and card monitoring (Intelligent Platform Management Controller, IPMC) is installed on the card aside an Embedded Linux Mezzanine (ELM) that works as a service environment and allows fast access to the FPGA registers.A single BCP will be able to read up to 600 crystals, therefore 108 cards are required to cover the entire ECAL Barrel.The BCP will support shared links among neighbour cards in order to run algorithms requiring multiple crystal signals like more advanced spike rejection mechanisms or cluster TPs generation.Three main algorithms will be applied to the data extracted: • Linearization, where digitized samples are subtracted by the baseline pedestals and multiplied by their gain.
• Amplitude and Timing reconstruction, where predetermined crystal pulse shapes are applied to the data collected in order to extract the real amplitude and the arrival time and correct for possible signal pile up from adjacent bunch crossings (see figure 3 left).
• Spike rejection, where thanks to a faster sampling rate (160 MHz), shorter pulse shapes and single crystal information, spikes can be distinguished with a discriminant built from the ratios of three consecutive linearized samples (figure 3 right).

Test beam data taking
During the last years, several campaigns have been performed to test the new electronics prototypes with particle beams.Pure electrons beams with energy in the range 20-200 GeV have been used at the CERN H4 beamline facility.The upgraded on and off-detector electronics (figure 4) have been tested and energy scans on crystals have been performed to measure energy and time resolution.Hodoscopes were placed on the beam line to provide the beam position, and microchannel plate detectors (MCP) were used for time reference (the latter read by 5 GS/s CAEN V1742 digitizers).
Finally the readout of the electronics was triggered by plastic scintillators (figure 5).The test beam carried out in 2021 showed that the target time resolution of 30 ps can be achieved, and even improved, on a single crystal for energies above 50 GeV (figure 6).Test beams were carried out also in 2022 and 2023: however the full analysis of the data taken is still to be completed.In July 2023, a full ECAL readout tower was irradiated with a dose that is intended to simulate the future CMS conditions.It has been performed at the CERN Mixed-Field Irradiation Facility (CHARM), and 67.7 Gy/day of accumulated dose have been achieved with a mixture of 41.3% neutrons, 19.5% protons and 35.6% pions.The total accumulated dose at the end of the test was 1.4 kGy which corresponds to 24% of the HL-LHC life time.A future irradiation campaign at the Paul Scherrer Institut will achieve a total accumulated dose corresponding to more than twice of HL-LHC life time.In order to monitor the radiation hardness of the DAQ system during the irradiation, data are collected via BCP card, and periodic reconfigurations of the electronics are performed.The APD dark current and number of SEUs in the chips are recorded, and they will be studied to create correction strategies.

Conclusions
The Barrel of the CMS Electromagnetic Calorimeter will undergo a major upgrade of both on-and off-detector electronics to be ready for the start of the HL-LHC operation.The conditions foreseen at the HL-LHC include the increase of the Level 1 trigger rate (750 kHz), Level 1 trigger latency -4 -  -5 -

Figure 1 .
Figure 1.Picture of VFE card v3.2 showing a pair of CATIA and Lite-DTU chips for each acquisition channel.

Figure 2 .
Figure 2. FE card v3.3.The 4 LpGBTs, the GBT-SCA chip and the VTRx with the fiber direct to the off-detector electronics are visible in the picture.

Figure 3 .
Figure 3. Left: effect of the pile up in the evaluation of the time of arrival and amplitude of a pulse shape.Right: difference between pulse shapes belonging to an APD spike and scintillation signal.

Figure 4 .
Figure 4. BCP card V1 with the ELM (top-right) covered by a metal plate, the FPGA (a Xilinx Kintex UltraScale XCKU115) hidden below the fan and the IPMC mezzanine in the bottom left part.Both ELM and IPMC use a ZYNQ7000 ARM/FPGA hybrid.

Figure 5 .
Figure 5. Schema of the DAQ system used in the 2023 test beam campaign.

Figure 6 .
Figure 6.Time resolution obtained aligning all the maxima of the signals collected from a crystal and fitting them with a pulse shapes over-sampled in the frequency domain.