Testing and characterisation of the prototype readout chip for the High-Luminosity LHC upgrade of the CMS Inner Tracker

: This contribution describes the characterisation and validation campaign of the prototype of the CMS Readout Chip (CROC), a 65 nm CMOS pixel readout ASIC for the CMS Inner Tracker upgrade for High Luminosity LHC. This validation campaign includes tests with single-chip and multi-chip modules, irradiation campaigns, test beams and wafer-level tests. The main results obtained in the testing of the CROC prototype will be outlined. Key improvements and fixes that have been implemented in the final version of the chip before the October 2023 submission will be described.


The CMS Readout Chip for High-Luminosity LHC
The High-Luminosity LHC environment will pose unprecedented challenges for the pixel readout electronics of the CMS experiment [1][2][3].In order to mitigate the increase in pileup (up to an average of 200 concurrent interactions at each bunch crossing), the pixel size will be decreased by a factor of 6 (25 µm × 100 µm) with respect to the current Inner Tracker [4].The increase in instantaneous luminosity will also cause unprecedented hit rates, up to 3.5 GHz cm −2 in the innermost tracking layer.The readout ASIC is also required to be extremely resistant to radiation, with a total ionising dose (TID) requirement of 1 Grad and single-event upset (SEU) rates that can reach the level of 0.1 kHz.Operation at low detection thresholds, as low as 1 k, will be necessary in order to cope with the reduced charge collection in the highly irradiated sensors, with fluences exceeding 2 × 10 16 n eq /cm 2 in the innermost layer.
The CMS Readout Chip (CROC) [5] is a pixel readout ASIC developed by the RD53 Collaboration [6] for the High-Luminosity LHC upgrade of the Inner Tracker of the CMS experiment [7].RD53 is a joint ATLAS-CMS collaboration that produced a first demonstrator chip (RD53A) in 2017 and prototype chips in 2020 for ATLAS (ITkPixV1) and 2021 for CMS (CROCv1).The ASIC has been developed using the 65 nm process in order to meet the granularity, hit rate, and radiation hardness requirements for HL-LHC operation of the pixel detector.
The CROC features approximately 1.4 × 10 5 readout channels with 50 µm × 50 µm pitch over a surface of about 4 cm 2 .The pixel front-end includes a charge-sensing amplifier with Krummenacher feedback in the analogue front-end, 4 bit charge information with a 40 MHz time-over-threshold (ToT) measurement in the digital front-end, and 5 bit of in-pixel configuration for threshold equalisation.Data is sent out of the chip with up to four high speed serial links (1.28 Gb s −1 ).The feature of merging data from multiple chips into one (data merging) has also been introduced in order to reduce the number of needed output links per detector module.
Both the chip periphery and the pixel matrix are protected against SEUs by means of triple-modular redundancy (TMR).In the periphery, a TMR scheme with auto-correction and clock triplication -1 -has been introduced, whereas in the pixel matrix there is no auto-correction capability.The usage of minimum-size transistors has been avoided for the digital domain in order to improve resistance to TID effects.
The ASIC contains shunt-LDO regulators in order to allow the powering of detector modules through a serial powering scheme to reduce the material budget from power cables [8].

Testing and characterisation of the CMS Readout Chip prototype
The prototype of the CMS Readout Chip has been subjected to an extensive testing and characterisation campaign from 2021 to 2023.The CROCv1 has been studied with single-chip boards and on prototype detector modules.Several irradiation campaigns have been performed, both with bare chips and with bump-bonded sensors.Moreover, the performance of the chip has been studied at test beams using both planar and 3D sensor technologies.Finally, the majority of the available CROCv1 wafers has been tested at wafer level, obtaining important characterisation data for approximately 1.9 × 10 3 chips.
In the following sections, selected results from the testing campaign are reported.

Front-end performance
The linear front-end, as already demonstrated by the experience with RD53A chips [9], meets the CMS requirements for what concerns low threshold operation (1 k) and low noise occupancy [10,11].
During wafer-level testing of the ASICs (see section 2.5), threshold scans are performed for the whole matrix, before and after equalisation to approximately 3 k.The threshold dispersion for a bare chip has been found to be of the order of 40  after equalisation, with an equivalent noise charge (ENC) of about 80 .The threshold dispersion and the ENC do not increase significantly when an equalisation to a threshold of 1 k is performed.These results also match observations from diced chips.
The efficiency of the analogue and digital front-ends has been measured at hit rates compatible with the ones expected at HL-LHC by means of a high intensity X ray beam at INFN Torino.A CROCv1 ASIC with planar sensor was tuned to a threshold of 1.5 k and configured in such a way to obtain an average time-over-threshold count of 2 (fast discharge mode).
The results of the test can be found in figure 1 for both front-ends.Whilst the analogue front-end is still more than 99 % efficient at 3.5 GHz cm −2 , the efficiency of the digital front-end is slightly above 95 % at the same hit rate and for the nominal 12.5 µs trigger latency due to the fact that the buffering architecture has not been optimised for single pixel hits from photons.The digital front-end efficiency has been found to meet the requirements in simulations using charged particles.These results match previous measurements with RD53A chips [12].

Radiation hardness
The RD53B chips, and the CROCv1 in particular, have been subjected to multiple irradiation campaigns in order to verify the 1 Grad TID requirement [11,13,14].The chip has been irradiated both with and without bump-bonded sensors and also with different dose gradients.In all cases, the ASIC has been found to meet the requirements for operation at High-Luminosity LHC.
For the analogue front-end, an increase to 100  in the threshold dispersion after equalisation at 1 k has been observed.In case of bump-bonded sensors, instead, the ENC reached approximately -2 -  the 150  level.An example of threshold distribution for a CROCv1 with 3D sensor irradiated to circa 1 Grad is reported in figure 2.
The radiation hardness of the chip periphery has been verified also with the aid of several monitoring features of the ASIC.For example, the gate delay degradation in the digital logic can be monitored with the use of in-chip banks of ring oscillators using different standard cells and drive strengths.In general, the reduction in ring oscillator frequency has been found to be at most of the order of 40 % for the minimum-size transistors at 1 Grad.For the analogue circuitry, instead, relevant signals have been measured whilst increasing the TID and small to moderate increases have been obtained (reported in figure 3), not problematic for chip operation.

SEE resistance
Several single-event effects (SEE) testing campaigns have been performed with RD53B chips [15,16].In general, it has been observed that in no case the ASIC ends up in a state which is unresponsive to input commands.Moreover, it has been found that, in case of SEUs, recovery is always possible without performing hard resets or power cycles of the ASIC, which is particularly important for a serially-powered system.The SEU-protection schemes used in the pixel matrix and in the chip periphery have been found to provide, respectively, a 100-fold and a 400-fold decrease in SEU cross sections (reported in figure 3).
A single-event transient sensitivity has been discovered in the bandgap reference circuit of RD53B ASICs, both by two-photon absorption tests and with SEE simulations.This sensitivity, causing output link dropouts during SEE tests, has been fixed with the introduction of a filtering capacitor in the bandgap circuit of the final versions of the chips.
It has also been found that SEUs in the pixel matrix can cause the readout to get in a stuck state.Functionality can then be recovered by clearing the data path using a dedicated chip command.The final version of the chip has been designed to be more resistant to this effect by increasing the skew of the triplicated clocks in the periphery.

Serial powering tests
Given the importance of the serial powering scheme in the future detector, several studies have been carried out with CROCv1 chips in different conditions, both by using single-chip boards and with prototype detector modules [17,18].Important data have also been obtained from wafer tests.
In general, no significant problems have been found with the serial powering scheme.For example, it has been verified that the inclusion of a chip in a serial powering chain does not negatively affect its performance [17].Moreover, the functioning of an important safety feature of the ASIC, which prevents harmful overvoltages above 2 V in case of malfunctioning readout ASICs in a detector module, has been verified both with diced chips and at wafer level.Data from waferprobing also show that process variations in key parameters of the voltage regulator are well below the 1 % level (as can be seen in the second distribution in figure 2).

Wafer-level testing
Twenty wafers of the prototype readout ASIC have been produced in 2021.Of these, fourteen have been tested at wafer level at INFN Torino [19,20] in order to produce testing boards and prototype detector modules [17,18].The number of tested ASICs amounts to 1932.
Most of the functionalities of the CROC are verified already at wafer level.For example, a threshold equalisation to approximately 3 k is performed during waferprobing and threshold scans are taken before and after this procedure.In addition,  curves up to 4 times the nominal chip current (4 × 2 A) are measured in order to test the worst possible powering condition.
The chip yields obtained on some of the last tested wafers are reported in figure 4. The average yield for a CROCv1 wafer is approximately 70 %, which is considered acceptable if the large area of the ASIC (about 4 cm 2 ) is considered.In the same figure, a breakdown of the causes for chip rejection is reported.A significant contribution, for example, is obtained from non-functioning bits in the pixel configuration registers, which amount to approximately 1.16 Mb per chip.In general, none of the rejection causes can be attributed to design weaknesses but rather to process variations and to the manufacturing process in general.

Future developments
The final version of the pixel readout ASIC, called CROCv2, has recently been submitted on 10 October 2023.It will be the second RD53C chip to be produced after the submission of the ITkPixV2 in March 2023.The CROCv2 design features several improvements over the prototype chip, such as increased SEE resistance and improved monitoring.Moreover, most of the weaknesses that have been identified in the testing campaign have been addressed, such as an inefficiency in the data merging circuit for some phase delays between the primary chip and the secondary ones [14].
-5 -Preliminary test results from the final readout chip of the ATLAS experiment are promising.Quick feedback from the testing of the first wafers has been obtained by both the ATLAS and CMS waferprobing centres and several of the improvements that are in common between the ITkPixV2 and the CROCv2 have been verified, both at wafer level and with diced chips.

Conclusions
The CMS Readout Chip, developed by the RD53 Collaboration for the High-Luminosity LHC upgrade of the CMS Inner Tracker, has been produced in a prototype version in 2021.The testing and characterisation campaign that has been performed in 2021-2023 confirmed that the prototype ASIC fulfils the design requirements for operation at HL-LHC, such as radiation hardness, SEE resistance, hit rate capability, and more.The information obtained during the testing campaign has been used to improve the design of the final version of the ASIC that has been submitted recently.

Figure 1 .
Figure 1.Results of the high rate X-ray tests performed at INFN Torino.Analogue (left) and digital (right) front-end efficiencies as a function of hit rate.For the digital efficiency, different values of trigger latency have been investigated, up to the nominal one for HL-LHC (12.5 µs).

Figure 2 .
Figure 2. Left: threshold distribution after irradiation to approximately 1 Grad on a CROCv1 ASIC with a bump-bonded 3D sensor.The threshold has been tuned to circa 1.1 k with a resulting dispersion of 0.1 k.One ΔVCAL unit corresponds to approximately 5 .Right: distribution of the  factor on a CROCv1 wafer, a crucial parameter of the on-chip regulator with a nominal value of 1000 that sets the slope of the linear  characteristic of the shunt-LDO regulator.

Figure 3 .
Figure 3. Left: variations in ASIC voltages as a function of TID.Reproduced with permission from [14].Right: SEU cross sections for the different TMR schemes employed in the chip [15].

Figure 4 .
Figure 4. Chip yields (top) and causes of chip rejection (bottom) for some of the last tested CROCv1 wafers at INFN Torino.