A prototype Radiation Energy Measuring Integrated Circuit with an asynchronous current-pulse reset block providing analog-to-digital conversion in 28 nm CMOS

In this paper we introduce a prototype Radiation Energy Measuring Integrated Circuit (REMIC) fabricated in a 28 nm CMOS process. The chip operates in a single-photon counting (SPC) mode and contains 100 pixels with a size of 50 μm × 50 μm. It is designed for precise energy measurements using asynchronous analogue-to-digital conversion. The proposed architecture allows both fast signal processing and precise energy measurement of incoming photons to be performed independently in each pixel, occupying a small pixel area. The integrated circuit (IC) has dimensions of 1.1 mm × 1.1 mm and is currently undergoing preliminary measurements. The paper focuses on the methodology used to mitigate process variations in each of the recording channels.


Introduction
One of the most widely used imaging techniques in crystallography, medical diagnostics, and industry [1][2][3] is x-ray based imaging, which is becoming increasingly popular due to massive progress in the development of both ionizing detectors and integrated electronics.The combination of a multichannel detector and multichannel integrated electronics enables the construction of an imaging system with geometric resolution determined by the active area of a single detector channel.These types of systems allow not only to detect ionizing radiation, but also to collect information about its intensity or energy.As more advanced integrated processes are offered, better spatial resolution can be achieved or more functionality can be provided on the same area, opening up new detection possibilities.Single-photon counting imaging is a popular technique due to its high dynamic range (determined by the counter depth), noiseless imaging, and the ability to count photons only within a given energy window (in systems with two or more discriminators).However, its main drawback is that its energy measurement levels are limited to only a few due to area and power constraints.Importantly, the required biomedical imaging system should be able to simultaneously record both the intensity and energy of incoming photons, thus enabling so-called color imaging.As a result, ongoing global efforts [4][5][6][7][8] are focused on the development of such imaging systems.
In this paper, we present the results of our work, which is aimed at the development of a recording channel that is capable of rapidly processing incoming signals and performing a precise energy-to-digital conversion.This technique has potential applications in biomedical imaging.Our proposed solution combines the feedback of the front-end amplifier with an energy-to-digital converter, thus minimizing not only the power and area of these blocks, but also the conversion time.The presented approach has been implemented in a 28 nm CMOS process and is based on asynchronous digital logic without the need for fast, power and area consuming clock distribution.
The paper is organized as follows.Section 2 provides the chip description and explanation of the working idea.It also discusses a proposed strategy to improve the uniformity of the chip's main parameters.Section 3 presents details of the performed measurements, while section 4 summarizes the paper.
-1 - The digital part includes a 12-bit digital counter (CTR) used in the SPC mode as well as in the energy-to-digital conversion mode, a control register (CREG) used to control both the pixel functionality and its main parameters, a control logic (CTRL) responsible for the generation of signals required for the energy-to-digital conversion and the SPC mode, and a digitally controlled delay line (DCDL) responsible for the generation of clock signals required by the dynamic discriminator (DISCR D ).
The analog part is equipped with a cascoded-inverter-based charge sensitive amplifier (CSA) [9], responsible for processing signals generated either by the incoming photons or by the current source I DIS used in the energy-to-digital conversion mode.However, since the current version of the IC is a prototype without the possibility of connecting a pixel sensor, the incoming photons can be mimicked thanks to the calibration voltage V CAL , which via the calibration capacitor C CAL generates a charge of C CAL ×V CAL at the CSA input.The recording channel also contains a replica amplifier (CSA R ) whose aim is to provide a reference voltage V R used in the energy-to-digital mode, and two discriminators: a continuous discriminator (DISCR C ) used in the SPC mode and to trigger the voltage-to-digital conversion of the CSA output, and a dynamic discriminator (DISCR D ) used in the energy-to-digital mode.To ensure that no incoming events are missed, the CSA output must be continuously monitored.Therefore, the first discriminator should be of the continuous type.Conversely, since energy-to-digital conversion is a multi-step process supervised by the CTRL, the second discriminator can be dynamic, resulting in better power performance.Each of the pixels is also equipped with digital-to-analog converters (DACs) responsible for mitigating the effects of process variations as well as for pixel operation control.These are a 5-bit DAC I used for setting the I DIS current, a 3-bit DAC R for controlling -2 -the Krummenacher-based feedback resistor R F of the front-end amplifier [10], and a 4-bit DAC T for controlling the mutual timing relation of the CLK 1 and CLK 2 signals of the DCDL block.

Operation idea of the recording channel
The recording channel can be set to SPC mode, in which only the DISCR C is used to generate pulses (for the CTR), only for those CSA output signals that exceed the threshold set by the V TH voltage.Whenever the CSA output pulse crosses V TH , a positive rising edge is generated, incrementing the number stored in the CTR.In this way, information about the incoming photon intensity can be recorded.Threshold scans can be obtained using the DISCR C , the V TH threshold, and the CSA input charge (mimicked by C CAL and user-provided V CAL ).From the threshold scans, the voltage offset V BASE , the pulse amplitude and the noise of the analog part can be extracted (see figure 2).The recording channel can also be configured in energy-to-digital conversion mode, where both discriminators cooperate with the control block CTRL and the dynamically triggered current source I DIS .The energy-to-digital conversion is initiated by the DISCR C , which notifies the CTRL block about the CSA activity.As a result, the CTRL starts the conversion procedure with a time delay that is required for the CSA output pulse to reach its peak value V OUT,Peak .The energy conversion is based on short current pulses I DIS injected at the CSA input to compensate the charge stored at the feedback capacitance C F (for further details see [11]).The whole conversion process is terminated when the CSA output voltage reaches the reference voltage level V R generated by the replica amplifier CSA R .Every single current pulse of time width t DIS and amplitude I DIS results in the CSA output voltage drop given by the following relation.
The main advantage of the proposed approach is its asynchronous operation, which does not require an external clock.This feature may be particularly attractive in systems composed of thousands of pixels, where clock distribution poses both area and power consumption related problems.Moreover, thanks to the modern 28 nm CMOS process and the asynchronous operation of the digital circuitry, the energy conversion is fast and limited only by the delays of the logic gates of the DISCR D and CTRL -postlayout simulations showed that two consecutive I DIS triggers are separated in time by only about 250 ps.Finally, the proposed conversion approach, based on the current source connected -3 -to the input of the amplifier being the virtual ground, prevents changes in the operating conditions of the current source, resulting in high linearity of the energy-to-digital conversion.Considering the parameters of the I DIS current pulses, the peak value of the CSA output pulse V OUT,Peak , and the reference voltage V R level, the conversion result can be given as:

Correction of the main parameters of the recording channel
Considering the given energy-to-digital conversion process and its adaptation in the integrated multichannel recording system, it is necessary to take into account possible variations of the main parameters of both the recording channel and the proposed converter, which may degrade the final performance of the energy measurement.Looking at the exemplary conversion process shown in figure 3(a), it can be seen that the pixel-to-pixel spread of the recording channel gain and baseline levels (both V R and V BASE ), as well as the speed of the capacitor C F discharging process (which is directly I DIS current dependent), can significantly affect the conversion result N CTR and thus degrade the conversion transfer function (see figure 3(b)).Therefore, in the presented chip, we provide a methodology that allows to minimize the potential non-uniformity of the energy measurement of the incoming photons.The proposed correction is based on three consecutive steps starting with the adjustment of the CSA output pulse amplitude.Here, we use a methodology adapted in [12], which allows the fine-tuning of the pulse amplitude by controlling the feedback resistance R F .This is because the maximum value of the CSA output pulse is related not only to the input charge Q IN and the feedback capacitance C F , but also to the mutual ratio  of the time parameters of the CSA output signals by: where  =   /  , and   =     is related to the falling edge of the CSA output pulse, while   is related to the rising edge.It can be seen that the R F control can be used to influence V OUT,Peak , and here this is realized by the 3-bit DAC R , i.e. the DAC R is controlled individually in each pixel to equalize the pulse amplitudes gathered via threshold scans.
-4 -Next, the C F discharge speed is equalized by providing two different V CAL values and counting the N CTR difference.In that way, applying (2.2), the recording channel offset can be canceled as shown below.
DIS ×  DIS (2.4)In this procedure, I DIS can be tuned to equalize the C F discharge phase using the 5-bit DAC I .
Finally, the voltage offsets of the recording channels are minimized using the methodology presented in [13].This is achieved by separating the dynamic discriminator DISCR D trigger signals CLK (see figure 1(b)) and controlling their mutual time difference relation.In contrast to [13], here we propose to use the DCDL instead of the voltage-controlled delay line (VCDL).Thus, the time delay of the DCDL signals is controlled by the DAC T which changes the load capacitors of the particular buffers (the DAC T is a 4-bit bank of MOS-based capacitors connected to the outputs of the DCDL buffers).

Measurement results
The measurement setup consists of a test printed circuit board (PCB), a controller, and a remote PC.The test PCB, shown in figure 4, is comprised of two modules: the daughter board, which includes the wire-bonded chip and decoupling capacitors, and the motherboard, which is equipped with the logic translators and optional test points.This approach enables more efficient testing, as any issues with the chip or a particular PCB failure only require the exchange of one module.The controller is based on a system-on-chip (SoC).Its FPGA component facilitates communication with the chip, while the CPU component executes Python-based tests and enables remote PC communication.The performed transfer characteristics of the energy-to-digital conversion performed in terms of DAC I , DAC R , and DAC T control allowed to minimize the spread of the energy conversion, as shown in figure 6.The standard deviation of the conversion gain was reduced from 0.022 count/e − to 0.001 count/e − .

Summary
The design description of the pixel blocks of the REMIC and its preliminary measurement results were presented.A new approach to energy-to-digital conversion, based on asynchronously generated short current pulses for incoming charge compensation, was described.The possible sources of energy measurement nonuniformity and the methodology to mitigate them were discussed as well as the nonuniformity minimization algorithm was proposed and followed by measurements proving its efficiency.The linear operation can be achieved approximately from 10 ke − to 25 ke − , promoting REMIC to medical imaging or synchrotron experiment applications.The chip is currently undergoing testing, and its full functionality verification is expected soon.

Figure 1 .
Figure 1.(a) Photo of the chip, (b) simplified schematic idea of the single recording channel.

Figure 2 .
Figure 2. Example of threshold scans with description of the recording channel's main parameters.

Figure 3 .
Figure 3. (a) Conceptual sketch of the potential mismatches anticipated in the energy measurement process and (b) its possible influence on the transfer characteristic of the conversion.

Figure 5
Figure 5 shows the measured transfer characteristics of an exemplary chip pixel for different DAC I and DAC T settings.Figure 5(a) illustrates the influence of the current I DIS (in its whole tuning range), responsible for discharging the feedback capacitance C F , while figure 5(b) shows how the DCDL line affects the energy-to-digital conversion by modifying the clock signals CLK that trigger the DISCR D operation.

Figure 5 (Figure 5 .
Figure 5 shows the measured transfer characteristics of an exemplary chip pixel for different DAC I and DAC T settings.Figure 5(a) illustrates the influence of the current I DIS (in its whole tuning range), responsible for discharging the feedback capacitance C F , while figure 5(b) shows how the DCDL line affects the energy-to-digital conversion by modifying the clock signals CLK that trigger the DISCR D operation.

Figure 6 .
Figure 6.Possible conversion gain values of REMIC recording channels.The most uniform configuration is highlighted in green.