Overview of the production and qualification tests of the lpGBT

The Low-Power Gigabit Transceiver (lpGBT) is a radiation-tolerant ASIC used in high-energy physics experiments for multipurpose high-speed bidirectional serial links. Around 200,000 chips have been tested with a production test system capable of exercising the majority of the ASIC functionality to ensure its correct operation. Furthermore, specific individual qualification tests were carried out beyond the production tester limits, including radiation, multi-drop bus topology, inter-chip communication through different types of electrical links and characterization of jitter and stability of the recovered clocks. In this article, an overview of the production and qualification tests is given together with their results demonstrating the robustness and flexibility of the lpGBT.


Overview
The Low Power GigaBit Transceiver (lpGBT) [1] is a radiation-tolerant ASIC that was designed at CERN and that will be integrated in the Front-End electronics of most of the High-Lumi Large Hadron Collider (HL-LHC) experiments.It supports a high-speed bidirectional serial link between Front-End (on-detector electronics, exposed to radiation) and Back-End (off-detector electronics, far from radiation) and provides Timing and Trigger Control (TTC), Data Acquisition (DAQ) and Slow Control data (SC) in a single link.In figure 1 a scheme showing the location of the lpGBT in the link between Front-End and Back-End is shown.
To cover the needs of the HL-LHC experiments, around 200,000 lpGBTs were manufactured.To ensure the proper operation of these chips, two testing stages were carried out: qualification and production.
Qualification tests were performed to demonstrate advanced functionalities not planned to be tested during production due to the system limitations.They were carried out on a small sample set (dozens of chips).Qualification provided information about the design and the behavior of the chip under specific environment conditions.In section 2 the most important qualification tests that were made are described and a summary of the obtained results is shown.For each of them, a link to an exhaustive report is provided.
During production, all manufactured lpGBTs, which were previously packaged in a ball-grid-array package, were tested and verified.In order to test such a large amount of chips, a production tester system was made.In section 3 the operation of this system is described and a summary of the obtained results is shown.

Qualification tests 2.1 Radiation tests
The lpGBT went through several radiations campaigns: X-ray, heavy-ions and neutrons.These were done to validate the chip against total ionizing dose (TID) and Single Event Effects (SEE).[3].The X-ray tests showed that the lpGBT is robust against TID for the digital features at 1.08 V (up to 200 Mrad), 1.2 V (up to 300 Mrad) and 1.32 V (up to 600 Mrad).For the analog features, voltage drifts proportional to TID at all operating temperatures were observed between 0 and 300 Mrad affecting the analog calibration but not the functionality of the chip.In addition, the chip anneals properly at low temperatures (-25 • C) but shows data errors during annealing when biased at room temperature.[4].The lpGBT has also been extensively tested with heavy ions by using ion Linear Energy Transfer (LET) between 9.9 (Ar) and 62 (Xe) MeV cm 2 mg -1 and an ion flux of 15 × 10 3 s -1 cm -2 .The results showed that the lpGBT high-speed interface is very robust against high energy deposits with no errors after a total of 4 × 10 14 bits transferred at 1.28 Gbps for the downlink data (32 bits of payload per frame) and no errors after a total of 1 × 10 14 bits transferred at 8.96 Gbps for the uplink data (224 bits of payload per frame).However, for the lpGBT output clocks in transmitter mode, clock phase jumps of around 30 ps can occur due to SEE sensitivity of the lpGBT LC tank oscillator inductor for clock generation [5].This would only be critical for timing detectors, for which the configuration of the lpGBT in transceiver mode is recommended for reference clocks delivery (synchronous with the LHC bunch clock).In this mode, a clock phase stability of less than 5 ps is achieved as explained in section 2.4.

Heavy-ions
Neutrons [6].The last irradiation campaign performed with the lpGBT was with 23 MeV neutrons up to a fluence of 2.5 × 10 14 n cm -2 .In this case, the lpGBT together with the VTRx+, bPOL12V [7] -2 -and bPOL2V5 [8], housed in the VLDB+ (Versatile Link + Demo Board) [9], were irradiated.During the 35 hours of irradiation and during the annealing, the lpGBT could operate without problems together with the VTRx+ and bPOL DC/DC converters.

The EC-channel tests
The external control channel (EC-channel) is a special electrical port of the lpGBT -electrical link between on detector electronics and lpGBT -that can send and receive data at 80 Mbps when used in transceiver mode of operation.It can be used to control other devices.The EC-channel can be used in two different bus topologies: point-to-point connection and multi-drop bus.
The point-to-point connection implies that the lpGBT communicates with a single device at the end of the EC link.This device can be another lpGBT or a custom front-end ASIC such as the GBT-SCA [10].The multi-drop bus topology implies that more than a single device is connected to the EC bus.Since the VTRx+ can transmit data from up to four different lpGBTs, typical multi-drop bus topologies use four lpGBTs in the same bus: one in transceiver mode (master) and the others in transmitter modes (slaves).Other schemes having six different lpGBTs or more are also possible.
During the production testing of the lpGBT, only the EC-channel point-to-point connection could be tested by communicating with the FPGA at the other end of the bus.With this test it could be ensured that the EC driver and pins were functional, which was enough from a production test perspective.In order to validate the second bus topology -multi-drop -, specific setups made of up to six VLDB+ (each one housing one lpGBT) were made [11].With such a setup, the EC-channel multi-drop bus topology design could be validated.

Phase-noise tests
The lpGBT, being part of the timing distribution chain, has to guarantee a short-term phase variation tolerance of the order of a few picoseconds.The phase stability was part of the intended functionality of the lpGBT and can be verified by means of different tools which are shown below.
The phase-noise of the clocks delivered by different lpGBT samples was characterised by looking at one of its output clocks while being on a state where, depending of the mode of operation (lockmode), its internal Phase-Locked Loop (PLL) or Clock and Data Recovery (CDR) are locked.For this purpose, a special VLDB+ housing a test socket was used to be able to analyse different chips with different test conditions (output clock, frequency, registers configuration, lockmode, irradiation level and operating temperature) by using the same board.
In figure 2 one of the results from the phase-noise tests is shown.The plot on the left side shows a typical comparison between CDR and PLL modes.It can be seen that the integrated RMS jitter is higher in PLL mode than in CDR.This also happens for any combination of settings due to the overshoot response always present at 10 kHz in PLL mode.In a different measurement, the chips that were previously irradiated reaching a TID above 400 Mrad were having very similar phase-noise results as the ones that were not irradiated: this can be seen in the plot on the right-hand side of figure 2 where the integrated RMS jitter differences are less than 1 ps (100 Hz to 100 MHz).Such a span was also obtained when comparing chips from different production lots, which makes the irradiation impact in phase-noise very low.The rest of the results showed that independently of the test condition, the integrated RMS jitter is always below 5 ps (100 Hz to 100 MHz), well within the detectors specifications such as CMS [12].

Phase stability tests
Phase stability tests were also carried out by using the Characterization Board [13] housing one soldered lpGBT.In this case three output clock signals could be analysed (ECLK0, ECLK1 and PSCLK1) and their phase difference with respect to the reference clock could be compared.The reference clock was coming from a HPTC [14] which is a reference for both CDR (320 MHz used as a Reference Clock by the transceiver of the back-end FPGA) and PLL (40 MHz directly used by the lpGBT) modes.
For some of the test conditions mentioned in section 2.3 -output clock, frequency, configuration and lockmode -various actions were applied to trigger a loss of lock of the lpGBT (data/clock interruption by fiber/external clock disconnections, and chip resets).
The results in figure 3 show that the phase of the three output clocks analysed vary the same way with differences of less than 0.1 ps at a stable temperature (the temperature variation was also monitored and was less than 1.5 • C).It can be seen in the corresponding histogram a normal distribution with a peak to peak phase variation of less than 5 ps.The other set of results show that independently of the test conditions and cycle interruption type the phase variation is always below 5 ps peak to peak [15].In the image it can be seen that the test socket is still having the adjustable lid on it which is used to manually squeeze the chip against the contacts.During production testing, this lid is removed to allow a robot arm to insert and hold each chip in the socket with the required pressure.
The FPGA evaluation kit emulates both the Front-End and Back-End counterparts of the lpGBT under test.It also exchanges data with the PC through an ethernet cable and via the IPBus [16] control system in order to execute the necessary commands sent by the Tester Software to control and test each lpGBT [17].Thirty seconds are needed to fully test a good chip.It is shorter for a faulty lpGBT as the procedure is interrupted as soon as a failure is detected; the chip is then rejected.

Results
During the production testing, a total amount of 200,917 chips were tested.Out of them, 14,531 chips did not pass the tests initially, leading to a first yield of around 92.8 %.A small percentage of test failures were found to be caused by tester instabilities (communication errors, measurement errors or dust on the socket pins) and a second small production testing was carried out for the chips that were initially rejected.After testing the 14,531 chips a second time, 10,797 chips passed and a final yield of 98.14 % was obtained, having the I2C communication with the chip as the main reason of failure.

Figure 1 .
Figure 1.Typical HL-LHC Link Architecture.To receive downlink data (data going into the lpGBT), a PhotoDiode (PD) and a TransImpedance Amplifier (TIA) are used.To transmit uplink data (data going out of the lpGBT), a Driver (DRV) and a Laser Diode (LD) are used.A typical optocomponent used with the lpGBT is the VTRx+ [2].

Figure 2 .
Figure 2. Typical result obtained from the phase noise tests.Comparison between CDR and PLL modes for a given chip at a given set of configurations (left) and comparison between irradiated and non-irradiated chips for another set of configurations (right).

Figure 3 .
Figure 3.One of the results obtained from the phase stability tests with a reset applied between each measurement point.Phase variations of the three output clocks together with the temperature variation for each cycle (left) and the corresponding histogram of the ECLK0 (right) are shown.