Abstract
This paper presents the design and test results of a 13 Gbps 1:16 deserializer ASIC fabricated in a 55 nm CMOS technology for Nuclotron-based Ion Collider fAcility (NICA) Multi Purpose Detector (MPD) project. The deserializer would be used in the downlink data transmission of MPD readout system to recover the serial data from the back-end to the parallel data for the front-end. The ASIC adopts a tree-type structure, consisting of a high-speed data receiver (RXDATA), a high-speed clock receiver (RXCLK), four levels of demultiplexer (DEMUX) modules, clock dividers and 16 Low-Voltage Differential Signaling (LVDS) drivers. The demultiplexer modules are composed of different numbers of high-speed DEMUX unit and low-speed DEMUX unit. The high-speed DEMUX unit and the high-frequency clock divider adopt an optimized compressed current mode logic (CML) differential structure to ensure the bandwidth with limited voltage headroom. The low-speed DEMUX unit and the low-frequency clock divider use CMOS latch to save power consumption. The duty cycle correction (DCC) circuit and the clock aligner are employed in the clock paths to ensure the correct duty cycle and aligned clock edges. In the chip test, the ASIC receives 13 Gbps serial data and outputs 16 channels of 812.5 Mbps data correctly with wide-open eye diagram. The tested power consumption is 203 mA with 1.2 V power supply including the RXDATA, the RXCLK and the 16 channels of LVDS drivers, and the core power consumption is 122.7 mA.