Interstrip Capacitances of the Readout Board used in Large Triple-GEM Detectors for the CMS Muon Upgrade

We present analytical calculations, Finite Element Analysis modeling, and physical measurements of the interstrip capacitances for different potential strip geometries and dimensions of the readout boards for the GE2/1 triple-Gas Electron Multiplier detector in the CMS muon system upgrade. The main goal of the study is to find configurations that minimize the interstrip capacitances and consequently maximize the signal-to-noise ratio for the detector. We find agreement at the 1.5--4.8% level between the two methods of calculations and on the average at the 17% level between calculations and measurements. A configuration with halved strip lengths and doubled strip widths results in a measured 27--29% reduction over the original configuration while leaving the total number of strips unchanged. We have now adopted this design modification for all eight module types of the GE2/1 detector and will produce the final detector with this new strip design.


Introduction
The Large Hadron Collider (LHC) was built to shed light on several fundamental questions in particle physics. The Compact Muon Solenoid (CMS) experiment [1] is one of the LHC's two general purpose experiments designed and built to detect and reconstruct particles produced in proton-proton (pp) and heavy ion (proton-ion and ion-ion) collisions. With the discovery of the Higgs boson [2,3], the CMS Collaboration has established a rigorous research program involving precise measurements of Higgs boson properties and searches for new physics. This requires a large increase in the LHC luminosity, which puts stringent requirements on the detectors. In order to maintain its excellent performance, the CMS experiment is currently undergoing a series of upgrades of its components, including its muon system [4,5]. The upgrade of the muon system is a critical component of CMS due to the strong role of exploring new physics with muons in the final state.
The CMS muon system is composed of three detector technologies: Resistive Plate Chambers (RPC), Drift Tubes (DT) and Cathode Strip Chambers (CSC), all of which are being upgraded [5]. To ensure continued function of the muon trigger at acceptably low Level-1 trigger rates and to increase redundancy and acceptance of the muon system, a new muon subdetector based on Gas Electron Multipliers (GEMs) [6] is being added in the forward region of the CMS detector (see figure 1) [5,7]. For this upgrade, triple-GEM detectors, i.e. micro-pattern gas detectors with three GEM foils, are being used. Figure 2 shows a schematic cross section of the geometrical configuration of drift anode, foils, and readout board for all CMS triple-GEM detectors.   Figure 1. An R-z cross section of a quadrant of the upgraded CMS detector high-lighting the locations of the new GE1/1, GE2/1, and ME0 stations with GEM technology in the CMS muon endcap region. The previously existing muon stations, i.e. drift tubes (MB), cathode strip chambers (ME), and resistive plate chambers (RB, RE), and the flux-return steel yoke (dark areas) are also shown. One of the challenges with any detector system is improving the signal-to-noise ratio (S/N). One variable that influences the noise in the detector is the capacitance between readout strips on the readout board (ROB), that we refer to as the "interstrip capacitance". As the S/N is influenced by the geometrical configuration and the dimensions of the readout strips, i.e. the length and width of the strips, as well as their spacing, the interstrip capacitance is crucial for detector operation and performance. The purpose of this study is to optimize the final readout strip geometry of the GEM detectors in the GE2/1 station (see figure 1) to maximize the S/N. Specifically, we are addressing the concern that the strips are quite long in the original design of the largest GE2/1 modules. This leads to significant capacitances presented to the inputs of the front-end electronics and a danger of unacceptable noise levels. We consider modifying the original design [5] by cutting the strips in half and doubling their widths while keeping the gap between strips the same. This obviously preserves the area of each strip and consequently the total number of strips per module. The key question then is by how much exactly this changes the interstrip capacitance. This motivates the studies presented here.
We discuss results from three methods used to determine the interstrip capacitance: analytical calculation, two-and three-dimensional (2D and 3D, respectively) simulations using Finite Element Analysis (FEA), and experimental measurements on a custom ROB with different strip geometries.
This paper is organized as follows: In section 2, we briefly describe the overall geometry of the GE2/1 chambers and of the readout strips on the readout boards. Section 3 provides information on the calculation and modeling of the interstrip capacitance of the GE2/1 strips. In section 4, we describe the setup used for experimental measurements of the interstrip capacitances. Results are presented and discussed in section 5.

Geometry of CMS GE2/1 GEM detectors
The GE2/1 muon station will cover the pseudo-rapidity region 1.6 < |η| < 2.4. This station consists of large trapezoidal chambers as shown in figure 3. A GE2/1 chamber comprises four separate modules and covers an area of 1.45 m 2 . Chambers are installed in pairs on the muon station to provide two positional measurements per muon track. The GE2/1 station will comprise 72 chambers, each covering 20.3 • in the azimuthal direction, with 36 chambers per muon endcap. The back chamber contains four modules labeled M1 (smallest) to M4 (largest), and the front chamber comprises corresponding modules M5 (smallest) to M8 (largest). In total, 864 large GEM foils are needed for this system. In this study, the smallest and largest modules of a GE2/1 chamber, i.e. the M1 and M4 modules, are considered; their original strip specifications are summarized in table 1 [5].      Figure 5 displays a cross section of a subsection of the GE2/1 ROB used for the analytical calculations. Here, "Strip" refers to the readout strips on the ROB and "Trace" refers to the signal lines on the other side of the ROB which are connected to the readout strips through a via, which is an electrically conductive channel that runs through the PCB. These signal traces terminate in the readout connectors, where the front-end electronics are plugged in so that a signal can be read out. Figure 5. The readout strip and trace geometry, where w is the strip width, 2g is the gap width of the strips, w t is the trace width, 2g t is the gap width of the traces, and h is the thickness of the substrate with dielectric constant . Note that strips and traces are connected by vias (not shown), which are conductive connections that run between the layers of the PCB.

Analytical calculation
The capacitance between coplanar metal strips on a dielectric surface has been widely investigated and used in particular in the fields of telecommunication and microwave applications [8,9]. In this work, the interstrip capacitance per centimeter of strip length is calculated using a modified version of the expression developed in [8]. This equation is modified to account for readout strips on the front of the board and for the traces on the back side of the ROB. Using the dimensions displayed in figure 5, we obtain the following equations, which are a linear sum of the strip and trace capacitances: where: Here, C a is the capacitance between two readout strips of length l s with air above and below, C sa is the capacitance between the readout strips due to the presence of the PCB substrate below, C t is the interstrip capacitance between two traces of length l t with air above and below, and C st is the capacitance between the traces due to the presence of the substrate. Equations 3.2-3.9 are the moduli of K(k), which is the complete elliptic integral of the first kind, where w is the strip width, w t is the trace width, 2g is the gap between the readout strips, 2g t is the gap between the traces, h is the thickness of the FR4 (flame retardant glass-reinforced epoxy laminate) substrate with dielectric constant = 4.7, and 0 is the vacuum permittivity. The average trace lengths, trace widths, and gap widths used for this calculation are measured experimentally as explained in section 4. The calculations are performed using MATLAB [10], and the built-in MATLAB function ellipke() is used for the complete elliptic integral of the first kind.

Finite Element Analysis model
A model of the GEM readout board based on the FEA is created using COMSOL, a Multiphysics simulation software [11]. The initial model uses simply two strips with the strip width and the width of the gap between the two strips as parameters. This results in a basic 2D model, as shown in figure 6 (left). To find the interstrip capacitance, a potential difference of 1 V is applied between the two strips and then the COMSOL software calculates the charges q using Gauss's Law and the capacitance C = q V . Specifically, the FEA model always considers one strip at 1 V and the other one at 0 V. The model utilizes the Electrostatic Physics module and extra fine meshing is done for all the components as shown in figure 6 (right).
The analytical method is limited to two strips and 2D calculations. In order to get more detailed insight into the interstrip capacitance, we also perform 3D modeling using the COMSOL software, i.e. including the finite length of the readout strips and the 3D geometry. Figure 7 shows 3D models for three strips and for 128 strips. The latter can be utilized to calculate the interstrip capacitance between any strips, i.e. not limited to only adjacent strips. The 3D model with two strips can also be  The models for the M1 and M4 modules of the GE2/1 chamber are also built using the COMSOL software. Since these are multi-strip models, it is not feasible to manually create the whole model. Instead, the COMSOL software is interfaced with MATLAB programming code to generate a model with the full complement of 384 strips. In this model, we also accommodate the gas volume in addition to the copper strips and the FR4 substrate. This model can also accommodate a copper sheet 1 mm above the ROB to simulate the presence of the GEM3 foil above the ROB (see figure 2), consistent with the hardware configuration (see figure 11). Using this software, we can designate the strips between which we wish to calculate the interstrip capacitance. This allows us to obtain the electric potential across the entire module and to calculate the interstrip capacitance between various combinations of the strips. For example, figure 9 shows the electric potential across the M1 module with the value of the interstrip capacitance between first and 384 th strip determined to be 0.00838 pF/cm (left) and 0.0154 pF/cm between the first and the 192 nd strip (right).

Experimental measurements
In order to conduct a comprehensive analysis of the problem, a custom ROB is fabricated that allows direct physical capacitance measurement. It has the overall shape of a GE1/1 ROB with twelve different strip configurations proposed for the M1 and M4 GE2/1 modules. These configuration explore different options for strip and trace lengths, as well as for strip and gap widths. To determine the geometry of the traces on the other side of the board, their length, width, and gap width are measured twelve times at each end of the traces. Because the gap width between the traces is not constant along their lengths, the average between the smallest and largest gap widths is used in the calculation. Table 2 lists the specific configurations of the readout strips and the measured signal trace dimensions in each of the 12 sectors of the custom-built ROB, including the parameters from the designs in the original Technical Design Report (TDR) [5]. The interstrip capacitance is measured in each readout sector with a commercial Excelvan M6013 capacitance meter. For each pair of strips, four measurements are made. To obtain an accurate measurement, the probes of the capacitance meter are placed at opposite ends of adjacent strip pairs, and held about a centimeter above the strips by one person while the meter is zeroed by another person. After zeroing, the probes are immediately placed on the strip and a reading is taken. A weighted mean over all strips in each sector is calculated from the average of all trials for each individual strip, and the standard deviation of the weighted mean is computed for all sectors. The measurements are repeated with a copper-covered PCB suspended 1 mm from the readout board in order to simulate the capacitance contribution of the bottom of the GEM3 foil above it (see figure 11). One-millimeter dielectric FR4 spacers are placed around the edge of the ROB to hold the copper-clad PCB 1 mm from the ROB. Extra spacers are also used in areas where there are no readout strips to ensure that the ROB remains planar. Because the readout strips are not directly accessible in this configuration, the probes of the capacitance meter are instead placed on the pins of the 128-channel Panasonic connector on the ROB. The same procedure of zeroing the meter and reading the measurements is followed as described above. The measurements are taken with the same statistics and in the same locations for both strips and traces (except for sector 1 where three additional measurements are taken).

Results and discussion
The calculated and measured interstrip capacitances for the readout board of GE2/1 detectors are presented for various configurations of strip dimensions. We wish to compare the results from the two calculation methods to each other and then the calculations to the measurements. For the latter, the trace dimensions in the analytical calculation and in the FEA modeling with 2 strips and 2 traces are varied to reproduce the different trace lengths on the physical ROB (see table 2).  Results from both methods agree quite well in all cases. As expected, interstrip capacitances increase when the strip width is doubled for both M1 and M4 modules. However, the increase is only on the order of 10-20%. Since interstrip capacitance is directly proportional to strip length, halving the strip length will decrease the capacitance by 50%. Consequently, halving the strip length while doubling the strip width does indeed lead to an overall reduction of the interstrip capacitance, which is now quantified to be 40-45%. This result confirms the original premise for this study quantitatively. A decrease on the order of 20% in the interstrip capacitance is seen in the calculations when the gap width between the strips is doubled.

Results from experimental measurements
For the experimental measurements of the interstrip capacitance, the values listed in table 3 are weighted means over all measured strip pairs in the sector, and the uncertainties are the standard deviations of the weighted means. The table also lists the ratios of the measured capacitances to the analytically calculated capacitances.
The configuration with the lowest measured interstrip capacitance (9.32 ± 0.05 pF) for the smaller M1 module is Sector 9 where the strip lengths are halved and the strip widths are unchanged,   Table 3 shows also that longer trace lengths increase the interstrip capacitance as one would expect. Comparing Sector 1 with Sector 4, i.e. the original configuration of the M4 module with the original configuration of the M4 module with long traces, we find that the interstrip capacitance is around 30% (∼ 6 pF) larger for the latter in both the experimental measurements and the calculations. The same effect is observed when comparing Sector 5 with Sector 10, i.e. the original configuration of the M1 module with the original configuration of the M1 module but with long traces; here the measured interstrip capacitance is around 23% (∼ 4 pF) larger for the latter. Similarly, comparing measurements in Sector 5 with Sector 11, i.e. the original configuration of the M1 module with the same geometrical configuration, but with minimal trace lengths, we find that the latter is around 14% (∼ 2 pF) smaller.
The measured capacitances are typically 20-40% higher than the analytically calculated values for all configurations. This is due to the simplicity of the model that is applied in the calculations where only the two strips and the FR4 substrate are present. By contrast, on the ROB the measured strip pair is surrounded by many other strips which leads to a modification of the electric potential in the space around the strip pair and an increased capacitance.
In summary, the measurements confirm the earlier conclusion from the calculations that the best strategy to minimize interstrip capacitance is to halve the strip lengths and double the strip widths if one wants to keep the number of strips constant. We also conclude that to reduce the interstrip capacitance and consequently the intrinsic noise from the ROB, the length of the traces should be minimized as much as possible in the GE2/1 and ME0 ROB designs. This is exemplified by the measurement result for Sector 12 that shows a 36% reduction in interstrip capacitance when both strategies are employed together.

Results for interstrip capacitance with and without a copper-covered PCB and 3D model
The motivation to perform additional measurements with the presence of a conductor plane comes from the discrepancy observed between the analytical calculations and the measurements shown in table 3. Clearly, nearby conductors modify the capacitance between adjacent strips. In a CMS GEM detector, the bottom of GEM3 represents a large additional electrode only 1 mm away from the strips. The average measured interstrip capacitances both with and without the presence of a copper-covered PCB to simulate the bottom of GEM3, and the ratio of the two, are presented for each sector of the ROB in table 4. With the PCB present, the measured capacitances change by -2% to +34% over the measurements without PCB with most sectors showing an increased capacitance with an average of +15%.
The basic conclusions from the previous section still hold in this more realistic configuration. The measured interstrip capacitances with halved strip lengths and doubled strip widths are reduced by 17% and 22% over the original TDR configurations for the M1 and M4 modules, respectively. Sector 12 shows a 46% reduction in interstrip capacitance over the original TDR configuration (Sector 5) when in addition the trace lengths are minimized in M1.
The interstrip capacitance between two adjacent strips obtained from the multi-strip FEA model both with and without the presence of a copper plate, and the ratio of the two are presented in table 5. Because the FEA model considers multiple strips, it is difficult to simulate in addition traces of varying lengths and widths. Consequently, in this model the traces are not considered, but the various strip and gap geometries are simulated, which results in simulations performed for eight of the twelve ROB sectors. The interstrip capacitances with and without a copper plate are almost the same in the simulation, as can be seen from the ratio between them. As in the experimental measurements, the lowest simulated interstrip capacitance for the M1 module is obtained by halving the strip length, and for the M4 module by doubling the strip width and halving the strip length.
Although the overall relative variations of the FEA results from sector to sector are in agreement with the variations in the experimental measurements, there exist differences in the absolute values. Comparing table 4 with table 5, we find that the values obtained from the FEA model are 22-40% lower than the experimentally measured values. This discrepancy is presumably due to the absence of the signal traces when simulating the readout board using the FEA model. This observed discrepancy prompts us to create a 3D FEA model to include the contribution of the traces. However, it is technically difficult to simulate the traces of the whole custom-built GE2/1 readout board (see figure 10), so a simple model with only two strips and two traces is considered to model the 12 sectors with their various strip and trace geometries (see figure 8). This model can also simulate the effect of the presence of copper at the bottom of the GEM3 foil. Table 6 shows the results of the interstrip capacitance obtained from this two-strips-and-two-traces 3D FEA model, both with and without the presence of a copper plate, and the ratio of the two. Including the traces in the model reduces the relative discrepancies with the experimental measurements significantly. Figure 13 shows a comparison of the results from this FEA model and experimental measurements, both without a copper plate (left) and with a copper plate (right). Results without copper plate typically agree better than results with copper plate.
The multi-strip FEA model allows us also to calculate an interstrip capacitance between strips that are not necessarily directly adjacent. For example, we calculate the capacitance between the first strip and each of the next 128 strips in the presence of all the other strips as shown in figure 7 (right). A fixed potential of 1 V is applied to the first strip and a fixed potential of 0 V is applied to the other strip of interest. The capacitance between those two strips is then calculated with the potential of all other strips varying accordingly. The result is shown in figure 14 for the first 128 Interstrip capacitance (pF) strips without a PCB present. Beyond that, the capacitance does not change very much anymore. As the distance between the strips is increased, the interstrip capacitance decreases similar to an inverse function.

Summary and conclusions
This paper presents and discusses analytical calculations and physical measurements of the interstrip capacitances for twelve different potential strip geometries and dimensions of the readout boards for the smallest (M1) and largest (M4) modules in the GE2/1 detector for the CMS muon upgrade. We  also present results from 2D and 3D Finite Element Analysis modeling of this system. The main goal of the study is to find configurations that minimize the interstrip capacitances and consequently maximize the signal-to-noise ratio for the detector. Specifically, we investigate if a configuration with doubled strip width and halved strip length, which leaves total channel number in the detector unchanged, can reduce interstrip capacitance compared with the original configuration. Overall, we find agreement at the 1.5-4.8% level between the two methods of calculations and on the average at the 17% level between calculations and measurements. For the M1 (M4) module, the configuration with halved strip lengths and doubled strip widths results in a measured 27 (29)% reduction over the original configuration. The corresponding calculations give reductions of 33 (32)%. Increasing the width of the 0.02 cm gaps between strips by 50-100% only produces a 8-16% reduction in interstrip capacitance. An important observation from the measurements of the interstrip capacitance is the effect the signal traces on the other side of the board have on the capacitance. With longer trace lengths, the interstrip capacitance increases by about 23 (30)% in the M1 (M4) module. We also find on average a 15% increase in the measured interstrip capacitance with the addition of a copper-covered PCB which is used to simulate the capacitance contribution from the bottom of the third GEM foil.
Finally, we briefly comment on the expected impact of the doubled strip width on detector performance. The main purpose of the GE2/1 detector is to help control the Level-1 muon trigger rates. In the original design [4,5], two strips are ganged together to form a trigger "pad". Consequently, we expect no impact on trigger performance at all if one double-width strip is used as one trigger "pad".
We conclude that the best strategy to minimize interstrip capacitance for the GE2/1 readout boards is indeed to halve the strip lengths and double the strip widths if one wants to keep the number of strips constant and to minimize the length of all signal traces on the board. We have now adopted this design modification for all eight module types of the GE2/1 detector and will produce the final detector with this new strip design (see figure 4).