Mini-MALTA: Radiation hard pixel designs for small-electrode monolithic CMOS sensors for the High Luminosity LHC

Depleted Monolithic Active Pixel Sensor (DMAPS) prototypes developed in the TowerJazz 180 nm CMOS imaging process have been designed in the context of the ATLAS upgrade Phase-II at the HL-LHC. The pixel sensors are characterized by a small collection electrode (3 $\mu$m) to minimize capacitance, a small pixel size ($36.4\times 36.4$ $\mu$m), and are produced on high resistivity epitaxial p-type silicon. The design targets a radiation hardness of $1\times10^{15}$ 1 MeV n$_{eq}$/cm$^{2}$, compatible with the outermost layer of the ATLAS ITK Pixel detector. This paper presents the results from characterization in particle beam tests of the Mini-MALTA prototype that implements a mask change or an additional implant to address the inefficiencies on the pixel edges. Results show full efficiency after a dose of $1\times10^{15}$ 1 MeV n$_{eq}$/cm$^{2}$.


Introduction
Depleted Monolithic Active Pixel Sensor (DMAPS) prototypes have been developed in the TowerJazz 180 nm CMOS imaging process with the aim to explore their viability for the Phase-II upgrade of ATLAS for the High Luminosity LHC [1], and for future HEP experiments [2][3] [4]. With previous developments focusing on low-radiation environments [5], special interest lies now on the radiation hardness of this technology up to 100 Mrad in Total Ionizing Dose (TID) and ≥ 1 × 10 15 1 MeV n eq /cm 2 in Non-Ionizing Energy Loss (NIEL) in order to be used in the harsh environment of these experiments. Monolithic CMOS sensors additionally allow to minimize scattering material for best tracking performance. The developments reported here investigate pixel sensors, dubbed MALTA sensor and Mini-MALTA sensor, with small electrodes (electrode diameter 3 µm at 36.4 µm pixel pitch).
The advantage of small collection electrodes lies in the resulting small capacitance, which in turn helps to minimize noise and achieve low power dissipation in the active area. However, detection efficiency after irradiation in sensors with small electrodes can be critically affected in the pixel corners [6] [7]. To improve this, we designed special p-type and n-type implant geometries [8]. These special implant geometries are implemented in sub-matrices of the Mini-MALTA sensor. The detection efficiency for different pixel designs before and after neutron irradiation are studied in beam tests to determine the optimal pixel design for radiation hard depleted monolithic CMOS sensors.

Sensors with small collection electrodes
The small collection electrode minimizes input capacitance to achieve a high Q/C ratio at the circuit input. In the case of a 25 µm thick sensitive layer we expect a most probable ionization charge of around 1500 e − . To calculate the expected ionisation charge for our sensor, we assume an ionisation charge of 63 electron-hole pairs per µm path length [9]. With a total electrode capacitance of 5 fF this results in a voltage step of around 50 mV. This offers the possibility of using an open-loop voltage amplifier as the first amplification stage, instead of the conventional charge-sensitive amplifier scheme with a feedback capacitor, to save space and simplify the circuit. The collection electrode input voltage is reset after a particle hit using a diode-circuit or a PMOS-transistor. The front-end (FE) amplifier output connects to a discriminator, which produces the digital signal for a hit pixel. The discriminator threshold is set globally for the full sensor. The analog FE circuit is shown in Figure 1.
Initial measurements of this circuit on the MALTA sensor revealed significant Random-Telegraph-Signal (RTS) noise preventing lower threshold settings. This was attributed to the "M3" transistor being much smaller than on previous circuits. To verify this assumption the Mini-MALTA sensor includes sectors with the same "M3" size as on MALTA and larger. Measurements on the Mini-MALTA sensor confirmed that the larger transistor sizes significantly decreased the RTS noise, both before and after irradiation. In addition, the larger NMOS size also yielded a significantly larger gain and lower charge threshold for the same settings. Further measurements confirmed the "M3" output conductance was higher than expected, which caused gain degradation for the FE. In addition it was found that for lower threshold settings, where the influence of this output conductance is larger, the spread on the gain and hence the threshold spread increased.

Charge collection implant structures in Mini-MALTA
Figure 2 (top) shows the cross-section of the TowerJazz process with a special low-dose n-type implant addition across the full pixel matrix [3]. This implant generates the junction to deplete the epitaxial silicon layer (25 µm thickness). This n − layer separates the deep p-well of the pixel circuit from the p-type substrate. The substrate is reverse biased (0 to −20 V) to fully deplete the epitaxial layer of the entire pixel. We refer to this implant configuration as "standard continuous n-layer". The deep p-well is biased in our measurements at −2 V. The n − layer is depleted from its junction to deep-p-well and p-type epitaxial layer. Depending on the choice of n − layer doping concentration the n − layer may not be fully depleted near the electrode at −2 V, which influences capacitance and gain. Changing the p-well voltage to −6 V in future prototypes is expected to improve charge collection and reduce capacitance.
The TowerJazz process can be further modified (as shown in Figure 2 bottom row) by adding a gap in the low dose n-layer through a mask change (lower right) or adding an additional production process compatible deep p-type implant (lower left). We refer to these configurations as "n − gap" and "extra deep p-well" configurations, respectively. The purpose of these modifications is to improve the charge collection at the pixel edges and corners through the creation of a stronger lateral field, which focuses the ionization charge towards the collection electrode. The design of these implant structures has been optimized in TCAD simulations [8], which indicate that these modifications significantly improve the charge collection at the pixel boundaries.

The Mini-MALTA sensor design
The Mini-MALTA chip matrix contains 16 × 64 square pixels with a pitch size of 36.4 µm. The full chip measures 1.7 × 5 mm 2 including periphery blocks for data handling, sensor configuration and biasing.
The Mini-MALTA sensor comprises eight different pixel flavours differing in analog FE design, reset mechanism and electrode/well geometries, as detailed in Table 1. They are implemented in the matrix as 8×16 pixel groups as illustrated in Figure 3.
Each pixel contains a charge collection electrode formed by an n-well of 3 micron diameter, contacted by an n+ region to the readout circuit. The n-well itself forms the contact to the lightly doped n-implant below. Reverse bias depletes the lightly doped n-region and also some part of the n-well. The undepleted remainder of the n-well then collects the signal charge.
The collection electrode is connected to the analog FE circuit, which is located in a separate deep p-well. The output of the analog circuit connects to the digital circuit, which buffers the discriminator output of the FE-circuit and transmits a digital signal to the end-of-column logic. The pixels are organized in groups of 2 × 8. Hits from pixels are sent to dedicated logic, common within the group, generating a reference pulse (1 bit) as well as a pixel address (16 bit where each bit corresponding to a particular pixel out of the 16 pixels in each group) and group address (5 bit) signal on the 22-bit wide double-column bus. Digital signals on this bus are 2ns wide and are transmitted asynchronously to the periphery [6]. No clock is distributed over the matrix to -3 -  minimize power consumption and avoid cross-talk between digital and analog circuit. The digital signal from the pixel is stored in the end-of-column logic memory: The data from the groups are stored asynchronously into 16 synchronization memories, which are then read out synchronously with the external 320 MHz clock using a priority encoder. Inside the synchronization memory, the precise time-of-arrival information is added by latching the value of a 4-bit counter running at 640 MHz. When reading out the hits, the priority encoder gives priority to leftmost pixel groups (see Figure 3 right) in case of simultaneous hits in multiple memories. In the end-of-column logic the 4-bit double-column address is added to the data words, along with 3 bit bunch-crossing counter information (BCID) which is generated in the synchronization memories by using the external 40 MHz clock. The data from the end-of-column logic is stored into a FIFO with a depth of 64 48-bit words. By default, the Mini-MALTA operates in 'fast' readout mode where the 48-bit 8b/10b encoded data is sent off from the chip at 1.2 Gbps. In this case a 600 MHz clock, which is generated from the external 40 MHz clock, is used to send the data at double data rate. The Mini-MALTA sensor also offers the possibility to output the data at 40 Mbps for setups where fast signal transmission is not necessary nor desirable. This mode was used for beam tests reported here. To mark the beginning and end of the sent 48-bit words, a dedicated 'acknowledge' output signal is used, which is active only during the 48 × 25 ns when the data is being transmitted.

Signal response using 55 Fe source
The response of the sensors is verified using photons from a 55 Fe source and dedicated "test-pixels" with analog readout. 55 Fe produces photons with two characteristic lines, K α and K β , having energies of 5.9 keV and 6.5 keV respectively. The K α peak is the dominant decay mode. The Mini-MALTA test-pixels allow to probe the analog signal before the discriminator ("OUT-A" in Figure 1) and at the collection electrode ("IN" in Figure 1). Figure 4 (left) shows the signal amplitude spectrum from the test pixels measured on "OUT-A" with enlarged NMOS transistors for unirradiated Mini-MALTA samples in comparison to preamplifiers with standard (minimal-size) transistors. As explained earlier, enlarging the NMOS transistor "M3" significantly improves gain and gain uniformity and also RTS noise and therefore allows operation at lower thresholds. Clear peaks from K α and K β lines of 55 Fe are visible for the unirradiated chip. Figure 4 (right) shows the signal amplitude spectrum from the test pixels measured on "OUT-A" with enlarged NMOS transistors for unirradiated and neutron irradiated sensors. The sensors received for 1 × 10 15 and 2×10 15 1 MeV n eq /cm 2 fluence an additional 1 Mrad and 2 Mrad of TID through the gamma background in the reactor. For the irradiated Mini-MALTA sensors, a clear increase in noise is observed, resulting in an increased width of both peaks. Moreover, there is a shift in the mean peak position visible after irradiation, which suggests that the irradiated Mini-MALTA sensors increase in gain by 20% when operated at the same preamplifier setting. For comparison the amplitude spectrum was also measured at the collection electrode, so at the input of the readout circuit ("IN"), for unirradiated and irradiated sensors, which also showed a 20% higher 55 Fe-signal for the irradiated sensors. Most likely it points to a change in sensor capacitance due to changes in effective doping concentration, rather than a gain change in the readout circuit.
The chip configurations used in Figure 4 (left) and in Figure 4 (right) were slightly different, resulting in some shift in mean peak position for unirradiated sensors and regions with enlarged NMOS transistors.

Threshold measurement and tuning
The threshold in the full pixel matrix is modified through dedicated on-chip 8-bit DACs which adjust the biasing of the pre-amplifier stage and in-pixel discriminator. The main threshold adjustment is carried out through the discriminator bias current ("IDB"), which is set globally for the full matrix. For the beam test measurements described in the following sections, the chips are tuned to different thresholds to test efficiency as function of applied threshold. The resulting threshold is measured for each pixel by injecting pulses with varying voltage amplitude on an in-pixel test capacitance (0.23 fF) at the input of each preamplifier. For each pixel, 200 injections per test pulse amplitude are performed, and the threshold point corresponding to 50% occupancy (50% probability of a pixel being fired) is determined by fitting a Gauss error function to the hit occupancy S-curve. The width parameter (to deduce the value of equivalent noise charge ENC) is also extracted from the fit. Figure 5 shows the measured threshold distributions for unirradiated and neutron irradiated Mini-MALTA samples, separately for sensor regions with standard (right plot) and enlarged transistors (left plot). Default chip tuning configuration is used for all sensors. The sensors were operated at −6 V substrate voltage in a climatic chamber set at −20 • C. The gaussian fits are performed to the threshold distributions for each chip. For regions with standard transistors the average threshold extracted from fit decreases from 570e − (unirradiated) to 360e − (1×10 15 1 MeV n eq /cm 2 ) and 290e − (2×10 15 1 MeV n eq /cm 2 ). As already mentioned most of this change is due to a change in the sensor capacitance rather than in the readout circuit. In all regions with enlarged transistors the average threshold values are systematically lower due to the higher gain of the FE circuit with enlarged transistors: 290e − (unirradiated), 220e − (1 × 10 15 1 MeV n eq /cm 2 ) and 160e − (2 × 10 15 1 MeV n eq /cm 2 ). The threshold dispersion extracted from the gaussian fit is larger for regions with standard transistors (around 50e − ) than for regions with enlarged transistors (20-30e − ).
The ENC distributions for unirradiated and irradiated Mini-MALTA sensors are shown in Figure 6. The most probable ENC value before irradiation is 11e − and increases to ≈20e − for chips after irradiation. Moreover, the ENC dispersion is lower in the regions with enlarged transistors (σ ENC ≈ 3e − ). The ENC distributions in -6 -    sectors with standard transistors (σ ENC ≈ 5e − ) show a significant tail of pixels with high noise. We attribute this to Random Telegraph Signal noise (RTS) due to the use of minimal-size transistors in parts of the analog circuit. The measurements on sectors with enlarged transistors show that increasing the size of these transistors significantly reduces RTS noise and ENC dispersion as illustrated in Figure 6 (left).

Noise occupancy
The noise level for each Mini-MALTA chip is characterized by measuring the number of noisy pixels as a function of charge threshold. The noisy pixels with relatively large noise rate (above 0.5 kHz) are masked and are not counted in the following. For each chip these masked pixels constitute less than 1% of the total number -7 -of pixels. Figure 7 presents the distribution of the number of noisy pixels as a function of charge threshold for various Mini-MALTA samples, separately for sensor regions with enlarged and standard transistors. Typically for unirradiated Mini-MALTA chips, no more than 1 or 2 noisy pixels are observed even at very low thresholds (≈100e − ). For the neutron-irradiated Mini-MALTA sensors, the number of noisy pixels is low at higher thresholds (less or equal one), and the number grows with decreasing the threshold. At lowest thresholds there are 3-5 noisy pixels (out of 384 measured pixels) for each region of the neutron-irradiated Mini-MALTA sensors.

Beam telescope arrangement
The data presented in this study were recorded at the ELSA test beam facility at the University of Bonn. The ELSA synchrotron circulates one electron bunch with a maximum energy of about 3.5 GeV. The test beam is generated via a twofold conversion and the detectors were probed with 2 GeV electrons.
The test beam setup is shown in Figure 8. The beam telescope based on six MALTA planes was used. Each MALTA sensor provides a fast trigger signal when there is a hit on the plane. Upon coincidence of 2 or 3 planes, a trigger signal initiates the readout of the entire system. The data acquisition is performed using a custom read-out system based on the Xilinx VC707 boards and fast software [10][11][12].

Track reconstruction and alignment
Tracks are selected by requiring a hit on the third plane of the telescope in front of the DUT (plane '2' from Figure 8), and hits in the first two planes after the DUT (plane 'REF' and plane '3' from Figure 8). Adjacent pixel hits are combined into clusters. The track reconstructed from these three telescope layers is extrapolated to the plane of the DUT, taking into account multiple scattering by using the General Broken Lines (GBL) formalism [13,14]. The track trajectory calculation uses the material description of the DUT and all telescope planes as well as the electron beam energy for multiple scattering estimation.
The alignment of telescope planes uses a two-step method. In the first step, a coarse alignment is performed, where the hits in X and Y of all neighboring telescope plane combinations are correlated and the resulting residual distributions are shifted with their means towards zero. The second step uses full telescope tracks and a χ 2 minimization method for fine alignment. This returns the alignment parameters and uncertainties for each of the telescope planes.
The residual distribution between the telescope track projection and the center of the nearest cluster, which is not used in the track reconstruction, has a width of ≈13.5 µm in both X and Y directions, as shown in Figure 9. The width of the residual distributions is dominated by the expected intrinsic DUT resolution of 10.5 µm.

Hit to track matching and efficiency calculation
The hit detection efficiency is defined as the fraction of clusters on the DUT matched to telescope tracks over the total number of tracks. Reconstructed tracks with χ 2 /do f < 10 are used in the efficiency calculation. A cluster in DUT is matched to a track if the distance between the position of a track interpolated to the plane of the DUT and the position of the center of the cluster is smaller than 100 µm.
The acceptance area of the DUT is folded into the efficiency calculation as follows: due to the finite track resolution of the beam telescope, all tracks with a hit prediction on a DUT edge pixel are removed from the analysis. An additional exclusion area of the size of two pixel rows is also applied between the neighboring DUT sensor sectors of different designs. Tracks with hit predictions on noisy pixels (radius of 36.4 µm around the noisy pixel center) are rejected from the efficiency analysis. Given the limited size of our sensor acceptance in each sector (14×6 pixel after removal of edge pixels) a single noisy pixel can influence the efficiency calculation. For sensor regions with enlarged transistors the average efficiency is 99.6±0.1% at a threshold of 200e − and does not depend on extra sensor modification. The small inefficiency is partly due to relatively tight cluster-totrack matching conditions which accounts for 0.2% efficiency loss, and partly due to small regional inefficiency at double-column boundaries (≈0.2% overall efficiency reduction) which is still under investigation.

Efficiency dependency on implant configuration and pre-amplifier gain
The 2D efficiency map for a 1 × 10 15 1 MeV n eq /cm 2 neutron irradiated Mini-MALTA sensor ("W2R1") is shown in Figure 10 (right).  After 1 × 10 15 1 MeV n eq /cm 2 neutron irradiation, the average efficiency significantly decreases for regions with standard transistors due to the lower gain (higher effective threshold) in these sectors: it reaches 78.8% in the region with no extra sensor modification, 87.0% with extra deep p-well and 86.5% with n − gap. While the modifications to the implant proof effective, the overall efficiency is still significantly affected by the high threshold. As expected, the inefficiency is mainly present in regions around the pixel edges and corners, as shown in Figure 11 where the in-pixel efficiency plots are shown. The 2×2 pixel plots overlap with the double column structure of the chip matrix. Along the pixel edge and in particular in the corners the charge is shared between two or more pixels. The resulting small per-pixel signals are suppressed by a high effective threshold leading to inefficiency. For regions with enlarged transistors the average efficiency is 91.9% in the region with no extra sensor modification, 97.9% with extra deep p-well and 97.6% with extra n − gap. It is therefore clear that the usage of enlarged transistors significantly increases efficiency for sensors after irradiation due to the higher gain, lower gain spread and reduced RTS noise. In the implant configuration with a continuous n − layer and no extra deep p-well (sector 0) the overall efficiency is still reduced in the corner. If the charge collection in the pixel corners is improved through either a gap in the n − layer or an extra deep p-well along the pixel borders (see Figure 2 bottom row), the sensor becomes nearly full efficient at 1 × 10 15 1 MeV n eq /cm 2 . Figure 10 also shows the number of noisy pixels through white bins in the different sectors, where the track prediction is rejected and no efficiency is calculated. We observe on the irradiated sensor ("W2R1") noisy pixels only in the area of standard FE. In the area with enlarged transistors, no noisy pixels are visible. This provides another indication that enlarging some crucial NMOS transistors helps to reduce RTS noise.
After 2 × 10 15 1 MeV n eq /cm 2 neutron irradiation, shown for sensor "W5R3" at different thresholds in Figure 12, we observe an efficiency reduction to ≈93% also in the sector with extra deep p-well and ≈92% in the sector with n − gap. All other sectors are affected by this efficiency reduction as well. The higher charge thresholds further degrade the efficiencies in the sectors with the lower gain pre-amplifier, especially after irradiation.

Efficiency dependence on substrate voltage
The efficiency is also studied as function of the substrate voltage. From TCAD simulations we expect best charge collection at a substrate voltage of around −10 V [8]. Higher substrate voltage leads to a strong vertical electric field but reduces the relative lateral field. The result of a higher substrate voltage is a much more vertical field that pushes charge generated near the pixel corners/edges into the low field region under the p-well at those locations. The charge takes time to escape from these regions and this decreases efficiency especially after irradiation as then charge is more easily captured by radiation induced traps.
In Figure 13 we show the results for neutron irradiated Mini-MALTA samples at 1×10 15 and 2×10 15 1 MeV n eq /cm 2 . For the chip irradiated at 1 × 10 15 1 MeV n eq /cm 2 the efficiency is relatively stable when changing the substrate voltage between −6 V and −10 V. In contrast, the chip irradiated at 2 × 10 15 1 MeV n eq /cm 2 has best efficiency around -10 V to -12 V. The efficiency decreases at higher (−6 V) and lower (−20 V) SUB voltages in most of the sectors which confirms the qualitative observations in TCAD simulations. Therefore, the non-irradiated and irradiated Mini-MALTA samples at 1 × 10 15 1 MeV n eq /cm 2 were operated at a substrate voltage of −6 V, whereas the samples irradiated at 2 × 10 15 1 MeV n eq /cm 2 had a substrate voltage of −10 V applied.

Efficiency for different threshold settings
The efficiency is significantly affected by the preamplifier design, and here in particular the size of the NMOS transistor "M3" influencing gain, gain uniformity and RTS noise, ultimately allowing lower threshold operation to achieve higher efficiency. Furthermore, the additional deep p-type implant or n − gap at the pixel edges -12 -     improves the charge collection and efficiency after irradiation. The efficiency as a function of threshold for 1 × 10 15 1 MeV n eq /cm 2 irradiated Mini-MALTA samples is shown in Figure 14. With lowering the threshold, the efficiency increases and can reach approximately 95% for continuous n − sectors with enlarged transistors and 98-99% for sectors with n − gap or extra deep p-well. The gain is due to better charge collection in the pixel corners caused by the modifications of implants on the pixel edge.
When using minimal size transistors we reach only 88-92% efficiency for n − gap or extra deep p-well pixel designs even at thresholds around 200 e − whereas the preamplifier design with enlarged transistors reaches 98%. This highlights the importance of transistor choice in our pre-amplifier circuit, most notably the "M3"transistor which needs to be chosen for lowest output conductance. The sector with continuous n − and standard transistor behaves worst, due to the inefficient charge collection in the pixel corners and high threshold.
Similar trends are visible for neutron irradiated Mini-MALTA samples at 2×10 15 1 MeV n eq /cm 2 ( Figure 15). In this case the best efficiency is obtained for modified regions with extra deep p-well and amounts up to 75% for regions with standard-size transistors and up to 94% for regions with enlarged transistors.
In these measurements we also observe that sensors with 25 µm epitaxial layer produce similar or sightly better efficiency than sensors produced on 30 µm epitaxial wafers at the same substrate voltage, despite the fact that we expect about 20% more ionization charge in the 30 µm epitaxial wafers. This effect may be due to the higher field in the thinner epitaxial layer. Additionally the choice of processing for the creation of the low-doped n − layer may contribute to the observed behaviour: For sensors produced on 25 µm epitaxial wafers we have chosen a slightly deeper n − implantation than in the 30 µm epitaxial wafers. A deeper n − layer moves the junction deeper in the high resistivity epitaxial layer which provides a better field configuration for charge collection in the pixel corners.

Conclusions
This paper presents measurement results on the Mini-MALTA Monolithic Active Pixel Sensor prototype developed in the TowerJazz 180nm CMOS imaging process. The prototype implements several improvements to address the inefficiencies and limitations of the previous prototypes. In particular charge collection is improved in the pixel corners by modifying implants along the pixel boundary (n − gap or extra deep p-well pixel designs), -15 -  and the charge sensitive FE is improved by increasing the size of an NMOS transistor yielding lower RTS noise, higher gain and lower threshold spread allowing operation at lower thresholds.
The measurement results demonstrate that with these improvements the sensors achieve a 98-99 % efficiency at a threshold of 100e − to 150e − after a dose of 1 × 10 15 1 MeV n eq /cm 2 . To achieve full efficiency at 2 × 10 15 1 MeV n eq /cm 2 the FE should be further improved to achieve thresholds below 100e − .