Simulations of CMOS pixel sensors with a small collection electrode, improved for a faster charge collection and increased radiation tolerance

CMOS pixel sensors with a small collection electrode combine the advantages of a small sensor capacitance with the advantages of a fully monolithic design. The small sensor capacitance results in a large ratio of signal-to-noise and a low analogue power consumption, while the monolithic design reduces the material budget, cost and production effort. However, the low electric field in the pixel corners of such sensors results in an increased charge collection time, that makes a fully efficient operation after irradiation and a timing resolution in the order of nanoseconds challenging for pixel sizes larger than approximately forty micrometers. This paper presents the development of concepts of CMOS sensors with a small collection electrode to overcome these limitations, using three-dimensional Technology Computer Aided Design simulations. The studied design uses a 0.18 micrometer process implemented on a high-resistivity epitaxial layer.


Introduction
Monolithic pixel-detector technologies lower the production effort and cost while reducing the material budget in tracking systems of detectors of high-energy physics experiments. Integrated CMOS pixel sensors with a small collection electrode offer a small sensor capacitance, a favourable signal-to-noise ratio and power consumption, and the potential for excellent spatial and timing resolution [1]. Such sensors have been developed and adopted for the ALICE ITS upgrade using a standard 0.18 µm CMOS imaging sensor process on a high resistivity epitaxial layer [2]. Modifying the process to achieve full lateral depletion in the sensor [3] improves the radiation tolerance, of importance for the ATLAS ITk High-Luminosity upgrade [4], as well as the timing resolution, relevant for the CLIC tracking system [5][6][7]. However, the electric field in the sensor reaches a minimum in the pixel corners resulting in a degraded timing resolution and efficiency loss after irradiation [8][9][10]. This is more pronounced for larger pixel sizes, and achieving full efficiency and a few ns timing resolution has been proven to be challenging for pixel sizes around 40 µm or larger. This paper presents a study of two improvements of the pixel design in this modified process, a mask change and an additional implant, to further reduce the charge collection time, and therefore improve radiation tolerance and timing resolution while maintaining the small collection electrode and its benefits. The two approaches have been studied using three-dimensional self-consistent transient Technology Computer Aided Design simulations (TCAD [11]) both for non-irradiated and irradiated sensors, and have been implemented in a prototype run for the ATLAS experiment [8,9].

Standard and modified process
A 0.18 µm CMOS imaging process with a small collection electrode has been studied (see Figure 1).

Standard process:
Modified process: Figure 1. Schematic cross section (not to scale) of the CMOS standard (left) and modified (right) process with a small collection electrode. The implants of the CMOS circuitry are not shown. The arrows for the modified process indicate the deep planar junction.
Full CMOS circuitry is placed inside p-wells and n-wells shielded by a deep p-well implant. All implants are placed on a high resistivity epitaxial layer that is grown on a low resistivity backside substrate to maximise the depleted region in the sensor. In this standard process (see left side of Figure 1), it is difficult to make the depletion layer extend from the junction around the small collection electrode laterally in the epitaxial layer between deep p-well and substrate, especially if the readout circuitry occupies a large fraction of the pixel area. With a deep low-dose n-type implant to create a planar junction under the existing implants (see right plot of Figure 1), full depletion of the epitaxial layer is much easier to achieve as the depletion starts at the junction and therefore extends over the full pixel area even with low reverse bias [3,12].
The concept of moving the junction from a small area around the collection electrode to a larger area deeper in the sensor has been pursued in developments to combine full depletion with a small collection electrode in monolithic sensors, both for bulk or epitaxial layer technologies [13,14], as well as for Silicon on Insulator (SOI) technologies [15].

Low electric field regions in the sensor
In the fully depleted sensitive layer of the modified process charge collection is governed by drift, and hence by the direction and magnitude of the electric field. However, as will be shown by the three-dimensional TCAD simulations, these sensors with a small collection electrode exhibit a very non-uniform electric field, dropping to zero at the pixel corners. If not mentioned otherwise, the simulations discussed in the following have been performed with a voltage of 0.8 V on the collection electrode and − 6 V on the p-wells and backside substrate. Cuts through the pixel centre of the simulated three-dimensional pixel cell are presented.
As shown in Figure 2 for a pixel size of 36.4 × 36.4 µm 2 , the lateral electric field is due to symmetry zero at the pixel corners and the electric field along the sensor depth reaches a zero value close to the depth of the deep planar junction, resulting in a zero overall electric field at the pixel corners, a constant electrostatic potential, indicated by a star symbol in the figure. As visualised by the black arrows, the direction of the electric field along the sensor depth results in a push of charge carriers created at various sensor depth at the pixel corner into this electric field minimum. For the propagation of the charge out of this minimum the lateral component of the electric field is crucial. As shown in Figure 3, the size of the lateral field around the electric field minimum depends strongly on the pixel size: The smaller the pixels, the larger the lateral electric field, that helps to push the charge carriers out of this minimum and towards the collection electrode. The importance of considering the direction of the electric field can be understood by inspecting different backside bias voltages for the modified process (see Figure 4). For lower backside voltages the electric field along the sensor depth is decreased. At the pixel corner, this results in a change of of the direction of the electric field towards the collection electrode and thus a shorter drift path. The electric field minimum results in a slower charge collection, creating a higher probability of charge trapping after irradiation. The resulting dependency of the efficiency after irradiation on the pixel size has been observed in test-beam measurements [8][9][10]16]. Moreover, results with different p-well layouts have shown a higher efficiency in pixel regions where the p-well layout leads to a higher lateral field [8,9].
Overall, the experimental results as well as the TCAD simulations indicate that increasing the lateral field is the key to increasing the charge collection to make CMOS sensors with a small collection electrode radiation hard and achieving precise timing resolution. While the pixel size is limited by the requirement to fit all needed circuitry, a change of the sensor concept is pursued in the following simulation studies to enhance the lateral field while only minimally changing the manufacturing process. Figure 5 shows two different approaches to increase the lateral electric field at the pixel borders: Creating a gap in the deep n-implant, requiring only a mask change, and introducing an additional p-type implant at the pixel border. Additional implants to accelerate the charge collection have also been pursued for image sensors for visible light detection [14] as well as for SOI sensors [15]. Both approaches proposed here introduce a junction along the sensor depth, significantly increasing the lateral electric field, but also shifting the minimum of the electric field deeper into the silicon compared to the original approach presented in the right side of Figure 1. As a result the electric field starts to bend towards the collection electrodes already deeper in the silicon, reducing the drift path and hence the charge collection time. This is shown in Figure 6 and Figure 7 for the gap in the deep n-implant and the additional p-type implant, respectively.

Lateral electric field:
Electric field along sensor depth: Electrostatic potential: Figure 6. Results of the electrostatic simulation for the concept with the gap in the deep n-implant with a pixel size of 36.4µm × 36.4µm. The black arrows mark the electric field stream lines, the star symbol indicates the electric field minimum and the white lines mark the edges of the depleted regions.

Lateral electric field:
Electric field along sensor depth: Electrostatic potential: Figure 7. Results of the electrostatic simulation for the concept with the additional p-implant with a pixel size of 36.4µm × 36.4µm. The black arrows mark the electric field stream lines, the star symbol indicates the electric field minimum and the white lines mark the edges of the depleted regions.
Cuts through the pixel centre of the simulated three dimensional pixel cell are presented for a simulation with 0.8 V collection electrode bias and − 6 V bias on p-wells and substrate with a pixel size of 36.4 µm × 36.4 µm.

Transient three-dimensional TCAD simulations
In the previous section the influence of the pixel size and two additional pixel modifications on the electric field was illustrated using electrostatic simulations. To compare the timing response for different cases, three-dimensional transient TCAD simulation results are presented for a Minimum Ionising Particle (MIP) traversing the pixel corner, the worst case in terms of charge collection time. Results are shown for both, non-irradiated sensors and for sensors irradiated with a fluence of 10 15 neq/cm 2 . To model the effect of radiation damage, defect levels have been introduced, as described in [17]. In the following the influence of the pixel modifications, of the pixel size, and of the sensor reverse backside bias are discussed. The voltage on the collection electrode and p-wells has been set to 0.8 V and − 6 V, respectively. If not mentioned otherwise, the voltage on the sensor backside has been set to − 6 V.

Pixel modifications
The current induced on a single pixel is presented versus time in Figure 8 for the different sensor concepts before (left) and after (right) irradiation. The charge collection time is reduced by a factor of at least two for the proposed concepts. The same general trends can be observed after irradiation. However, the overall pulse heights are significantly reduced, as explained by trapping and recombination of the charge carriers.
The differences in pulse height have been evaluated by integrating the current pulses and calculating the charge. Figure 9 shows the charge versus time before (left) and after (right) irradiation. Within 25 ns differences are already observable before irradiation: While the collected charge for the concepts with the additional p-implant and the gap in the deep n-implant saturates, it still increases at 25 ns for the modified process, indicating that not all charge is collected. This illustrates the need of a process modification for faster charge collection even without irradiation for applications with a short integration time. Both proposed pixel improvements increase the collected charge after irradiation by at least a factor of three.

Pixel size
Moving towards smaller feature sizes will allow smaller pixel sizes while maintaining functionality. Thus, to evaluate the future prospects of the proposed sensor design concepts, the modified process and the concept with the additional p-implant are compared for smaller pixel sizes after irradiation. Current pulses are presented for different pixel sizes in Figure 10, comparing the original modified process from the right side of Figure 1, with the concept with the additional p-implant in the right side of Figure 5. Even for small pixel sizes of 20 µm × 20 µm the additional p-type implant significantly accelerates the charge collection, resulting in sub-nanosecond peaking times. The charge versus integration time for different pixel sizes presented in Figure 11, shows that the charge lost after irradiation can be recovered by going to smaller pixel sizes as well as by the proposed sensor modifications.

Sensor reverse bias
The maximal reverse bias voltage applicable to the p-wells is limited by the CMOS circuitry to − 6 V [18]. The deep low-dose n-implant isolates the p-wells from the backside substrate and allows for a higher reverse bias on the backside. The two pixel improvements weaken this isolation, resulting in a high current flow between the p-wells and the backside substrate (punch-through). This is further investigated here by fixing the collection electrode and p-well bias to 0.8 and −6 V respectively, and sweeping the backside bias from 0 V to −20 V. For each step of the backside bias the current flow between the backside and the p-wells has been calculated, as presented in Figure 12. A high current flow is observable for backside voltages below the − 6 V applied to the p-wells, since the small depletion of the epitaxial layer does not sufficiently isolate the p-wells from the backside, resulting in punch through between the p-wells and the backside substrate. For backside voltages higher than the − 6 V applied to the p-wells, the modified process shows the expected isolation. For the additional p-implant and the gap in the deep n-implant this isolation is reduced to a smaller voltage range and minimal for the sensor concept with the gap in the deep n-implant, leading to punch-through at lower absolute bias voltages.
A simulation of a MIP traversing the pixel corners has been performed for the modified process applying higher backside voltages, to investigate the impact on the charge collection time. The current pulses after irradiation are presented in Figure 13.  In the pixel corners a slight improvement can be noted for a backside voltage of − 15 V. An even higher backside voltage of − 20 V reduces the pulse height and thus the amount of collected charge, as explained by the higher electric field along the sensor depth that results in a longer drift path, a slower charge collection and a higher recombination probability after irradiation (see Figure 4).

Summary
By combining the advantages of a small sensor capacitance and a fully monolithic technology, CMOS pixel sensors with a small collection electrode address the requirements of future experiments. A crucial parameter is the charge collection time: A faster charge collection results in a higher radiation tolerance simultaneously with a more precise time stamping capability, driving requirements for future experiments.
In this paper the electric field distribution in such sensors has been modelled with threedimensional TCAD simulations, showing an electric field minimum at the pixel corners. Two different concepts were presented to reduce this electric field minimum and speed up the charge collection. Three dimensional transient TCAD simulations have been used to benchmark the performance of the proposed concepts. At the pixel corners, a significant reduction of the charge collection time has been observed for the proposed concepts. The amount of collected charge after irradiation with a fluence of 10 15 neq/cm 2 has been increased by a factor of approximately three. Moreover, the proposed sensor concepts have been simulated for pixel sizes down to 20µm × 20µm, showing the dependency of the electric field minimum on the pixel size and the potential to reach sub-nanosecond timing precision.