Performances of typical high energy physics applications in flash-based field-programmable gate array under gamma irradiation

Recent field-programmable gate arrays (FPGAs) based on flash memories offer a high radiation tolerance. We discuss potential applications of the Microsemi IGLOO2 FPGAs in high energy experiments. We implement a 24 channel time-to-digital converter with a time binning of 0.78 ns and evaluate the performance. Differential and integral non-linearity is measured to be far below the time binning. The time resolution obtained is approximately 0.25 ns. The FPGA was exposed to gamma rays with a total ionizing dose of 300 Gy. The function of the configuration memory is monitored and the degradation of the performance on the ring oscillator and high-speed transceiver is measured. The errors during firmware download and verification of downloaded firmware have been observed at 110–120 Gy and 80–90 Gy, respectively. The functionality of the ring oscillator and high-speed transceiver remains up to about 200 Gy.

: Recent field-programmable gate arrays (FPGAs) based on flash memories offer a high radiation tolerance. We discuss potential applications of the Microsemi IGLOO2 FPGAs in high energy experiments. We implement a 24 channel time-to-digital converter with a time binning of 0.78 ns and evaluate the performance. Differential and integral non-linearity is measured to be far below the time binning. The time resolution obtained is approximately 0.25 ns. The FPGA was exposed to gamma rays with a total ionizing dose of 300 Gy. The function of the configuration memory is monitored and the degradation of the performance on the ring oscillator and high-speed transceiver is measured. The errors during firmware download and verification of downloaded firmware have been observed at 110-120 Gy and 80-90 Gy, respectively. The functionality of the ring oscillator and high-speed transceiver remains up to about 200 Gy.

K
: Front-end electronics for detector readout; Radiation damage to electronic components; Radiation-hard electronics

Introduction
Field-programmable gate arrays (FPGAs) are widely used in the experiments of high energy physics. FPGAs based on flash memories could have high radiation tolerance with respect to the FPGAs based on static random access memories. This extends the potential applications of the FPGAs. In this study, the flash-based IGLOO2 FPGA manufactured by Microsemi [1] is focused on. Examples of the experiments of high energy physics include the ATLAS experiment [2]. IGLOO2 FPGA has relatively high tolerance against single event effects [3]. Therefore we focused on total ionizing dose. The irradiation level at the monitored drift tube (MDT) chambers at the ATLAS detector is estimated to be 2-20 Gy in 10 years of LHC operation [4]. A 24 channel time-to-digital converter (TDC) with time binning of 0.78 ns, which has the same binning and number of channels as in the current MDT system, is implemented and tested. The radiation tolerance of the IGLOO2 FPGA against total irradiation dose is evaluated. The reprogramability of the configuration memory, the current-voltage characteristic of the ring oscillator, and the high speed transceiver under gamma ray irradiation up to 300 Gy are investigated. Figure 1 shows a schematic of the TDC, which has been developed with Xilinx Kintex-7 FPGA [5]. The internal clocks of 320 MHz and 160 MHz synchronized with a 40 MHz reference clock are -1 -generated with a phase-locked loop circuit provided in the FPGA. In this design, a multisampling scheme based on quad phase clocks with the frequency of 320 MHz is employed to achieve the time binning of 1/(320 MHz × 4) = 0.78 nsec. Time measurement is provided in a time window of 6.25 nsec and transfered with 160 MHz clock. The dynamic range of (1/160 MHz)×2 14 = 100 µsec is fulfilled by adding the information of 14 bit counter running with 160 MHz clock.

Schematic of the TDC
The performance of the time measurement could generally be affected by the variation of the delays between different signal paths in the core of the TDC. The locations of the D flip flops in the core of the TDC are placed near the input ports to minimize the difference between signal path lengths. The signal path difference obtained from a simulation corresponds approximately to 0.2 nsec.

JINST 12 C04002
the time difference between the two leading edges of the pulses is measured to be 30 psec. The data output from the TDC is read out with the UART protocol.

Performance evaluation
The differential nonlinearity (DNL) and the integral nonlinearity (INL) have been measured. The DNL is defined for each bin as where T BIN is the ideal time binning and T i is the time difference between the specific bins i and i + 1. For the measurement of DNL, the output from the core of the TDC is read out for the time difference of the leading edges between the signal clock and the reference clock. By scanning the time difference between signal and reference clocks, the width of a typical bin can be focused on.
The scan is performed with a step size of 25 psec. The result of the measurement of the DNL for channel 1 is shown in figure 3. The measured DNL is less than half of the unity. The nonlinearity is dominated by the length difference between signal paths in the FPGA. Similar results are obtained for all 24 channels. The INL is parameterized in this study by where T input is the time difference between the leading edges of input signal clocks and T measured is the mean of the time difference measured by the TDC. The result of the measurement of the INL for channel 1 is shown in figure 4. The measured INL is consistent with zero up to 100 µsec. Similar results are obtained for all 24 channels. The time resolution is evaluated by taking the data with various time difference between the leading edges of the input signal clocks. The standard deviation of the difference between the measured and input time difference is taken. The time difference is scanned from 200 ns to 100 µs.  Figure 6 shows a board developed for the irradiation tests of the IGLOO2 FPGA (M2GL010T-1FGG484). The board has SMA connenctors for high-speed transceiver (SERDES) and general purpose input and output ports. Gamma rays have been irradiated at the Cobalt-60 irradiation facility at Nagoya University. The irradiation rate is 0.1-1 Gy/min.

Test results for ring oscillator
The change in the current-voltage characteristic of metal-oxide-semiconductor field-effect transistor (MOSFET) due to the irradiation dose could affect the TDC performance. Since the oscillation of the ring oscillator is sensitive to the current-voltage characteristic of MOSFET [9], we have tested the ring oscillator. Other two boards have been irradiated with a step size of 10 Gy. The ring oscillator consists of 501 NAND gates, where the output of each NAND gate is connected to the two inputs of another NAND gate. The firmware utilizes 4% of the lookup tables as 501 NAND gates. The oscillation period and the power consumption have been measured. To evaluate the tolerance beyond the limit of firmware download, the firmware download is performed only at the beginning of the irradiation test. Figure 7

Test results for high speed transceiver
Other two boards have been irradiated with a step size of 100 Gy for the evaluation of the tolerance of SERDES. Pseudo-random data has been transmitted and looped back with the coaxial cable. Data transfer rates of 2 Gbps and 4 Gbps are tested. The bit error rate (BER) has been measured. This firmware utilizes 15% of lookup tables, 10% of D flip flops, 50% of clock resources, and 100% of SERDES blocks. The worst slack path timing is 1.7 ns. To evaluate the tolerance beyond the limit of the firmware download, the firmware download is performed only at the beginning of the irradiation test. Table 1 shows the measured BER for each irradiation level and data transfer rate. No data is sent or received after the irradiation of 200 Gy.

Recovery of the functions
In total eight boards are irradiated to an irradiation level of 92-300 Gy depending on the boards. After the irradiation, the four boards with the irradiation of 92-120 Gy had errors in PROGRAM, while the other boards with the irradiation of 160-300 Gy had errors in READ ID CODE. Two boards which have the errors in READ ID CODE were put in the thermostat chamber ESPEC SH-641 [10], and the temperature was kept to be 75 • C for the investigation of recovery, while heating is not considered for the actual application for MDT. Recovery has been observed for the two boards. Figure 8 summarizes the results of the function recovery. The function of PROGRAM are recovered in a few hours for the irradiation level of 100 Gy. The time needed for the recovery seems to correlate with the total irradiation level. The function of READ ID CODE and implemented firmware were recovered by annealing in the high-temperature environment of 75 • C. Implemented firmware, i.e. ring oscillator and SERDES, was also recovered at the same time of the recovery of the function of READ ID CODE.

Conclusion
In conclusion, we examine the performance of the flash-based Microsemi IGLOO2 FPGA. We implement a 24 channel time-to-digital converter with a time binning of 0.78 ns. The differential nonlinearity and integrated nonlinearity are measured to be small. The time resolution obtained is approximately 0.25 ns. The radiation tolerance against total ionizing dose is studied with the gamma ray irradiation of a few hundred Gy. Firmware download is observed to be impossible after irradiation of about 100 Gy. The downloaded NAND ring oscillator and SERDES seem to survive up to a higher irradiation level of 100-200 Gy. This study provides useful information on the use of IGLOO2 FPGA in high energy physics experiments.