First Implementation of a two-stage DC-DC conversion powering scheme for the CMS Phase-2 outer tracker

The ``2S'' silicon strip modules for the CMS Phase-2 tracker upgrade will require two operating voltages. These will be provided via a two-step DC-DC conversion powering scheme, in which one DC-DC converter delivers 2.5 V while the second DC-DC converter receives 2.5 V at its input and converts it to 1.2 V. The DC-DC converters will be mounted on a flex PCB, the service hybrid, together with an opto-electrical converter module (VTRx+) and a serializer (LP-GBT). The service hybrid will be mounted directly on the 2S module. A prototype service hybrid has been developed and its performance has been evaluated, including radiative and conductive noise emissions, and efficiency. In addition system tests with a prototype module have been performed. In this work the service hybrid will be described and the test results will be summarized.

: The "2S" silicon strip modules for the CMS Phase-2 tracker upgrade will require two operating voltages. These will be provided via a two-step DC-DC conversion powering scheme, in which one DC-DC converter delivers 2.5 V while the second DC-DC converter receives 2.5 V at its input and converts it to 1.2 V. The DC-DC converters will be mounted on a flex PCB, the service hybrid, together with an opto-electrical converter module (VTRx+) and a serializer (LP-GBT). The service hybrid will be mounted directly on the 2S module. A prototype service hybrid has been developed and its performance has been evaluated, including radiative and conductive noise emissions, and efficiency. In addition system tests with a prototype module have been performed. In this work the service hybrid will be described and the test results will be summarized.

K
: Particle tracking detectors (Solid-state detectors); Si microstrip and pad detectors; Voltage distributions 1Corresponding author.

The CMS Phase-2 tracker upgrade
The CMS experiment is one of the six experiments installed at the Large Hadron Collider (LHC), CERN. As of 2016, a data sample of in total about 75 fb −1 of integrated luminosity has been collected with the CMS detector [1]. The detector's performance is excellent, even at instantaneous luminosities exceeding the design value of 1 × 10 34 cm −2 s −1 . The accelerator will be upgraded during Long Shutdown 3 (2024Shutdown 3 ( -2026, to allow it to achieve instantaneous luminosities of 5 − 7.5 × 10 34 cm −2 s −1 , and the result of this upgrade is referred to as the High Luminosity LHC (HL-LHC). To cope with the harsher conditions in terms of radiation, particle rates and data volumes, the CMS detector will be substantially upgraded as well (CMS Phase-2 upgrade) [2]. In particular, the complete silicon tracking system will be replaced. The new device will feature improved radiation hardness, a reduction of the material budget and higher rate capability, and will be able to provide data to the first stage (Level 1) of the CMS trigger system.
The layout of the new tracker is shown in figure 1. The outer tracker consists of a cylindrical barrel with six module layers, accompanied by five disks per side in the forward direction. Only two module types will be used, where each module consists of two sensor layers (section 2). The PS modules consist of one strip sensor and one macro-pixel sensor (PS stands for "pixel-strip sensor"). The macro-pixels will have a pitch of 100 µm and a length of 1.4 mm, while the strips will have a 90 µm pitch and a length of 5 cm. A total of 5332 PS modules will be installed at radii below 60 cm. At larger radii, 2S modules with two identical strip sensors will be used, each with two rows of 5 cm long strips at a pitch of 90 µm (2S stands for "strip-strip sensor"). It is foreseen that 8224 2S modules will be installed.
-1 - Figure 1. Schematic view of the Phase-2 tracker layout. One quarter is shown in the r-z view, where z points along the beam direction and r represents the radial coordinate. The interaction point is located in the lower left corner. The pixel modules are shown in blue and yellow, the PS modules in dark blue, and the 2S modules in red.

The p T module concept and the 2S silicon strip modules
The CMS outer tracker modules follow a new concept, referred to as the p T module concept [2]. The goal is to provide tracking information at the bunch crossing frequency of 40 MHz to the Level 1 (L1) trigger. Due to bandwidth limitations this information has to be limited to tracks with a transverse momentum, p T , above a certain value (e.g. 2 GeV). The concept is illustrated in figure 2, left. Charged particle tracks are bent in the 3.8 T magnetic field of CMS, with the bending radius depending on p T . The hit patterns in the two closely spaced sensor layers are compared onmodule, in the readout chip, and two-hit tracklets (so-called stubs) compatible with a programmable threshold are sent to the L1 trigger. Tracks are formed from stubs at the back-end, and merged with calorimeter and muon information in the High Level Trigger (HLT). Upon reception of a L1 trigger signal, the full event information is read out.
The overall module concept is shared between 2S and PS modules. This work focuses on 2S modules, which will therefore be explained in more detail. A drawing of the 2S module is shown in figure 2, right. Each sensor has an area of about 10 cm × 10 cm and contains two rows of strips. The mid-planes of the sensors are separated by either 1.8 mm or 4.0 mm. The strips are wire-bonded to CMS Binary Chips (CBCs) [3], of which eight are located on each front-end (FE) hybrid [4]. Each CBC receives data from both the top and the bottom sensor. The data from the eight CBCs on one FE hybrid are re-formated and serialized by the Concentrator Integrated Circuit (CIC). The CIC forwards the data to the Low Power Gigabit Transceiver (LP-GBT) ASIC, which is a serializer and a distribution hub for trigger, clock, reset and I 2 C signals. Data communication with the back-end is performed using optical fibers. The Versatile Transceiver (VTRx+) module [5] houses the VCSEL array plus a laser driver ASIC, as well as the PIN diodes together with an amplifier ASIC. Both the LP-GBT and the VTRx+ projects are carried out by CERN, and the devices are still under development. The 2S service hybrid, explained in detail in the next section, is a flex hybrid arranged perpendicularly to the FE hybrids. It distributes the high and low voltages and houses the LP-GBT and the VTRx+ module.
-2 - The green track with high p T passes the requirement, while the red track does not due to its larger bending radius. Right: CAD-drawing of a 2S module, with sensors in yellow, front-end hybrids in orange, and CBC and CIC ASICs in red. On the service hybrid the shield of the power part is shown as red box, the input connector is shown in light blue, the left grey box shows the LP-GBT and the green box symbolizes the VTRx+ module.

The service hybrid of the 2S module
The 2S module's service hybrid (SH) is a flex board that is laminated onto a carbon fiber (CF) stiffener of 500 µm thickness. The final version of the board will have four copper layers. Part of the board is folded around the stiffener. The bias voltage circuit is located on the back side, providing the bias voltage via two flexible Kapton tails to the back sides of the sensors. A temperature sensor is also integrated into one of the Kapton tails, and glued to one of the sensors. The LP-GBT, the VTRx+ and the low voltage (LV) power components are located on the top side. The LP-GBT is a low power version of the GBTx chip [6]. It receives the readout data at 320 Mb/s from the CIC on the FE hybrid, and forwards them to the VTRx+ at 5 Gb/s. The LP-GBT distributes trigger, clock and reset signals to the CIC, as well as sending I 2 C commands to the CIC, the CBCs and the VTRx+. The SH houses a connector for the VTRx+. The challenge is to achieve a low profile form factor. Present prototypes still use some commercial components and are thus not radiation-tolerant; moreover, their geometry is still subject to change. In its present prototype version the VTRx+ comes as a small pluggable PCB, which mates with a connector on the SH.
Two supply voltages are required for the module. The CBCs, CICs, LP-GBT and VTRx+ require 1.25 V. The total current for this supply rail is estimated to be around 2.4 A. The VTRx+ requires in addition about 0.12 A at 2.55 V to drive the VCSELs. With an estimated power consumption of 4.7 W and 6.3 W for 2S and PS modules, respectively,1 the total tracker FE power will amount to around 72 kW. This power has to be provided via 80 m long cables by power supplies located in the counting room. The resistance of these cables leads to large Ohmic losses, and consequently to a low power system efficiency and a high heat load on the cables. In addition, voltage drops on the supply cables can be much larger than the actual ASIC supply voltages. A DC-DC conversion powering scheme is therefore foreseen, based on step-down DC-DC buck converters, building on the experience from the implementation of such a scheme for the CMS Phase-1 pixel detector 1These numbers include an estimate for the efficiency of the DC-DC converters, which are discussed in more detail below.
-3 - upgrade [7]. In this scheme the power is supplied to the FE at a higher voltage, V in , which implies a smaller current, I, for the same power value. This voltage is converted on-detector to the required one, V out . Hence voltage drops (proportional to I) and power losses (proportional to I 2 ) are reduced by the conversion ratio, r = V in /V out , or r 2 , respectively. A two-step DC-DC conversion scheme, with two DC-DC converters working in series, has been chosen to provide the two required voltages of 1.25 V and 2.55 V to the module, taking into account system efficiency, cabling aspects, and required development effort. Both DC-DC converters are located on the SH, so that each module comes with its own LV distribution. This has a number of advantages: each module works as a standalone entity, all cabling up to the module must only carry the small input current, which helps to reduce the material budget, and the distance between the DC-DC converter's output and the load is short, limiting subsequent voltage drops.
The two-step powering scheme is schematically shown in figure 3, left. In the first stage the upFEAST DC-DC converter by CERN will receive 11 V and convert this to 2.55 V, as required by the VTRx+. The second stage DC-DC converter, DCDC2S by CERN, converts 2.55 V into 1.25 V. Both these DC-DC converter chips are still under development. They both require an air-core inductor as the energy storage element (ferrite inductors would saturate in the CMS magnetic field), a number of passive filter components and an electro-magnetic shield.
It should be noted that the PS modules will use similar SHs, although split into a power board and a data transmission board, since the PS modules are much narrower. While the overall concept is the same, the details differ. For example, a third supply voltage is required, and the data transmission rates are higher.

Service hybrid prototypes
A prototype of the 2S module SH has been developed, as shown in figure 3, right. Due to the fact that all active components are still under development and are therefore currently not available for use, it differs in several aspects from the final design. The upFEAST DC-DC converter is replaced by its predecessor, the FEAST2 ASIC [8]. The functionality of the two chips is the same, however the upFEAST will feature increased radiation-hardness, to be compatible with HL-LHC applications. An air-core toroid with an inductance of 200 nH and a DC resistance of 38 mΩ is used, -4 -and the switching frequency is set to 2 MHz. The DCDC2S is replaced by a commercial device (LTC3412A). The inductor is the same as the one used for FEAST2, and this DC-DC converter is set to switch at 2.45 MHz. Pi-filters are implemented at the LV input and output, as well as between the two DC-DC converters. Both DC-DC converters reside under a common shield. A connector for the VTRx+ prototype is provided. In the absence of the LP-GBT, four miniature electrical connectors are implemented, allowing (differential) data to be fed to the VTRx+ from the outside, and data to be read back. The HV circuitry is integrated on the fold-over region.
The prototype board has two 18 µm thick copper layers. The board was laminated onto an FR4 stiffener, which has 18 µm thick copper surface layers to resemble the electrical properties of CF.
Even though these prototypes are far from the final product, they are very useful in many respects. For example, they allow the general behaviour of a two-step DC-DC conversion powering scheme to be studied, the electromagnetic shielding to be developed, experience with the data transmission to be gained, and system tests to be performed by using them to power 2S prototype modules, allowing the impact of the DC-DC converters on the module's performance to be studied.

Electromagnetic shielding
The operation of a DC-DC converter with an external inductor makes the usage of an electromagnetic shielding inevitable, so that the silicon sensors and the FE electronic components are protected from electromagnetic radiation. The shielding has to obey certain geometrical constraints and should be as light as possible. The shielding should ideally reduce the emissions to a level comparable with the emissions originating from outside the shield.
Prototypes of the shield have been produced using two different technologies. The first prototype (figure 4, left and center) is made from an etched aluminium foil of 150 µm thickness. An additional layer of tin of about 5 µm thickness was added to ensure that the shield can be soldered to the PCB. The corners are spot-welded, avoiding the use of large amounts of solder. With this technology very thin structures, such as pins for alignment or notches to spare out traces on the PCB, can be manufactured. The second prototype (figure 4, right) is based on a plastic body, made by rapid prototyping, onto which 60 µm of copper is galvanically deposited.
Both shields have been mounted onto SHs and the shielding performance was measured using an automated scan table, where a pick-up probe is moved in 1 mm steps across the SH. The picked up signal is measured with a spectrum analyzer. The measurement is not calibrated in units of Tesla,  as only relative comparisons of the emissions with and without shield and between different shields are targeted. For each scan position the highest measured emission within the frequency band of 1.8-2.8 MHz, which includes the switching frequencies of both DC-DC converters, is recorded and can be plotted in a geometrical representation of the scan. The results are shown in figure 5 for measurements both without a shield and for the two prototype shields. To quantify in a simple way the performance of the shields, we compare the highest measured induced voltage in the scanned region with and without shield. These peak emissions are reduced drastically by both prototypes: by a factor of 30 for the aluminium shield and by a factor of 16 for the copper shield. This is plausible, as the skin depth at a frequency of 2 MHz, corresponding to the FEAST2's switching frequency, amounts to 58 µm for aluminium and to 46 µm for copper, which is close to the copper shield's thickness. As is visible from the rightmost plot in figure 5, the remaining emissions are at a low level and originate from components located outside the shield.
Overall the aluminium shield is preferred, as it performs slightly better, represents less material and allows the manufacture of finer structures.

Common Mode and Differential Mode noise spectra
In DC-DC buck converters two power MOSFETs are used to alternately connect and disconnect the load to the input voltage. This switching of large currents at MHz frequencies results in noise propagating through the power lines, both at the converter's input and output. Two modes are distinguished: Differential Mode (DM) noise refers to the ripple on the power line, while Common Mode (CM) noise refers to noise propagating in parallel through the power and return line, and returning through the system ground via parasitic coupling. This is sketched in figure 6, left. In a dedicated set-up both noise modes were measured with current probes at the SH's input and output. Common Mode noise can be measured by feeding the power and return cables in parallel through the probe. The CM currents add up and the DM currents cancel. Differential Mode noise is measured by routing the cables anti-parallel through the probe. In this way the DM currents add -6 - up and the CM currents cancel. The routing through the probe is sketched in figure 6, right. The set-up and the method are explained in more detail in [9].
From the experiment's point of view the DM noise at the DC-DC converters' output is most relevant, as this is expected to potentially influence the performance of the front-end electronics. While any noise emissions should be as low as possible, ultimately system tests with silicon modules have to prove that noise levels are low enough and can be accepted.
The DM and CM spectra are shown in figure 7. In the DM spectrum only peaks from the first converter stage (FEAST2) are visible, while peaks associated with both conversion stages are present in the CM spectrum. Figure 8 shows quantitative comparisons under various conditions. For quantification both the height of the switching peak (i.e. the first harmonic, even though the second harmonic might be higher) and the quadratic sum of all peaks up to 30 MHz are considered. Amplitudes are converted to linear units. The left plot presents results for all four noise modes for two different inductors, the default one with 200 nH and one with 430 nH. The FEAST2 switching peak is decreased by using a larger inductance for all modes (figure 8, left, yellow versus grey entries), while the noise of the second stage increases in almost all modes (green versus dark blue entries in the same plot). The total CM noise is increased by using the higher inductance coil (orange versus light blue, CM-in and CM-out), but a decrease of the DM noise at the output is achieved (orange versus light blue, DM-out). This improvement in noise has to be balanced against integration aspects and the material increase accompanying a larger inductor.
-7 -  In a second study the geometry of the shield was varied. Since both converters are located under a common shield, the emission of one DC-DC converter could couple to the other DC-DC converter. To study this potential effect, the common shield was replaced by two separate shields as well as with a shield with an internal separation wall. As shown in figure 8, right, neither approach to separate the DC-DC converters leads to a significant reduction in noise; on the contrary, the separate shields increased the CM noise. The conclusion is that mutual influence of the DC-DC converters is -if at all -a small effect, and that a common shield with a simple geometry is sufficient.
All these studies will have to be repeated with the final DC-DC converters, which might exhibit a different behaviour.

Power efficiency
In a two-step powering scheme the power efficiency, defined as the output power divided by the input power, is a critical aspect, as the individual efficiencies of the two stages multiply. The targets are 75 % and 85 % for the first and second stage, respectively, leading to a total system efficiency of 65 %. Both the combined efficiency as well as the individual efficiencies have been measured on the SH, where the measurement of the individual efficiencies required a modification of the board. At present, the total efficiency that has been achieved is 48 % when using the parameters as expected for the final application ( figure 9). This is driven by the second stage, as the efficiency of -8 - the commercial converter drops rapidly with load current (figure 10, right). The efficiency of the first stage, however, is close to the target value ( figure 10, left). This aspect will have to be revisited once the final DC-DC converters are available.

System tests with a 2S mini-module
System tests have been performed to study potential effects of the powering from the SH on the module performance. Ideally the powering should not increase the noise of the silicon modules at all, but a slight increase of a few per cent is considered acceptable.
Since full 2S modules were not available for the test, a so-called 2S mini-module with two CBC2 readout chips and two sensors, each with one row of 5 cm long strips, has been used. The SH was used to power the module, and was itself powered from a prototype power supply with line drop recovery instead of sensing, as envisaged for the final application, via a 80 m long cable (resistance ≈ 0.4 Ω). Scans of occupancy versus threshold were performed and the noise was extracted from the width of the resulting S-curves. The noise was measured for various positions of the SH,  where the closest position, resembling the SH's position in a module, is shown in figure 11, left. The results are summarized in figure 11, right. No significant differences in noise were observed between powering the module directly from a lab power supply and powering through the SH, as long as the DC-DC converters were shielded. Without the shield, an increase in noise is observed, as expected.
These measurements provide a first indication that the operation of DC-DC converters close to the silicon module might not deteriorate the module's performance. They also indicate that the radiated and conducted emissions, discussed in sections 4.1 and 4.2, respectively, are at an acceptable level. System tests will continue using a full-size module, and will also be repeated once the final DC-DC converters are available.
In a second study the prototype VTRx+ module was used. It was powered from the SH and a Gigabit Link Interface Board (GLIB) [10] was used to push random data through the VTRx+ at 5 GB/s. These data were then looped back to the GLIB. No bit errors were observed and the module performance was not affected by this high-speed digital data traffic on the SH.
Finally the dynamic behaviour of the power system was studied with an oscilloscope and a dynamic load. A prototype of the envisaged power supply as well as an 80 m long cable was used. Switching on and off was smooth and overshoots for large load reductions were acceptable, e.g. the output voltage of the SH increased by about 80 mV for 10 µs for a drastic reduction of the load from 2 A to zero.

Summary and outlook
A two-step DC-DC conversion powering scheme was implemented on the service hybrid for the 2S modules of the CMS Phase-2 Tracker upgrade. Various aspects of performance have been studied and no major problems were identified. The investigated shields reduced the electromagnetic emissions to levels below those originating from outside the shield. The system test showed that the noise behaviour of the investigated mini-module is not influenced by the new powering scheme, indicating that both radiated and conducted noise emissions are at an acceptabe level. The total power efficiency was measured to be 48 % and is significantly below the target value of 65 %. This has however been traced back to the efficiency of the second conversion stage, realized with a commercial device, while the efficiency of the first converter stage is consistent with its target -10 -

JINST 12 C03090
value of 75 %. The studies presented in this paper represent a first step towards demonstration that a two-step DC-DC conversion scheme implemented on a silicon module will work. They will be continued with more final components once these become available, including in particular the final DC-DC converters and a full-size 2S module.