Parametrization of the radiation induced leakage current increase of NMOS transistors

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to silicon dioxide interface the leakage current as a function of the exposure time to ionizing radiation results. This function is fitted to data of the leakage current of single transistors as well as to data of the supply current of full ASICs.


Introduction
The radiation induced leakage current of NMOS transistors and the threshold voltage shift are well known and intensively studied challenges for the design of radiation hard application specific integrated circuits (ASIC). Hardness by design (HBD) techniques [1] [2] have been developed and extensively used in the circuit design in the 0.5 µm technology node for the LHC experiments [3]. The HBD techniques consist mainly of the use of enclosed gate transistors to mitigate the source to drain leakage current along the shallow trench isolation (STI) and guard ring structures surrounding the transistors to avoid leakage current between neighboring structures. The use of this technique requires an increased area as well as custom libraries. With the transition to the 0.13 µm technology node, the amplitude of the leakage current increase decreases by three orders of magnitude, with the result that the HBD techniques are needed in sensitive nodes of the design only for radiation hard designs [4]. However, while the chip is operational, the increase of the leakage current of NMOS transistors results in a significant increase of the supply current. A generic parametrization of the leakage current as a function of total ionizing dose (TID) of single NMOS transistors is presented in this paper. The resulting function is fitted to published data of a diversity of technologies in use or under investigation for use in extremely radiation intense environments. As demonstrated in this paper, this parametrization can be used as well to model the supply current shift with TID on full ASICs and to predict the current to be expected during operation of the ASICs as a function of the temperature and the dose rate, once the parameters of the parametrization are measured.

Parametrization of the leakage current
This model describes the leakage current increase of linear NMOS transistors independent of technology details. The increase of the leakage current as a function of total ionizing dose has been reported for a large number of technologies. It originates from parasitic transistor channels along the STI, in which the transistor is embedded as indicated in figure 1. With a positive space charge appearing in the STI due to ionizing radiation, an inversion layer is created along the STI, which results in a leakage current paths from source to drain [4]. This is indicated in the cross section in figure 2.
This leakage current paths can be described as the channel of a parasitic transistor. As can be seen in figure 3, the parasitic transistor has a layout analogue to a linear transistor with the only difference, that the electric field opening the transistor channel originates from the positive space charge in the STI instead of from the potential at the gate. The space charge in the STI is always positive and therefore in PMOS transistors this transistor channel is closed by the radiation induced space charge. Thus the leakage current increase is only observed in NMOS transistors. This analogue layout motivates to describe the leakage current increase due to the parasitic transistor using the transfer characteristics of the parasitic transistor.

Transfer characteristics of the parasitic transistor
The transfer characteristics (drain current as a function of the gate to source voltage) for transistors operated in saturation mode can be simplified by where sub-threshold leakage is neglected. I D is the drain to source current, V G the gate to source voltage, and V thr the threshold voltage. K is the proportionality constant containing the widths, lengths, oxide capacitance, and the mobility of the minority charge carriers in the channel of the transistor, etc. In the parasitic transistor (which is responsible for the leakage current) the electric field originates from the effective space charge.
Assuming an electric field in the silicon proportional to the effective space charge, the gate voltage of the parasitic transistor is in this model replaced by the effective number of charges N ef f . Similarly, the threshold voltage is expressed by the threshold number of charges N thr . The transfer characteristics of the parasitic transistor are then given by and thus the leakage current of the regular transistor I leak is given by for N ef f < N thr with I 0 leak the preirradiation leakage current of the transistor. N thr is constant in time (and therefore accumulated dose) and temperature. With these assumptions a parametrization of the number of effective charge carriers N ef f describes the leakage current shift in NMOS transistors.

Processes of charge generation
A combination of four processes results in the effective space charge in the STI. First, due to ionization of the atoms, the incident radiation generates free electron hole pairs in the silicon dioxide of the STI [5] [6]. Some of these pairs recombine quickly, but the mobility of the electrons is between six and twelve orders of magnitude larger than the mobility of the holes, depending on the temperature and the electrical field [7][8][9][10]. Therefore many electrons are quickly removed from the STI, while the left over holes move slowly in the silicon dioxide by hopping transport [5]. Sites with missing oxide atoms in the amorphous silicon dioxide result in energy levels above the valence band and thus electrically neutral deep hole traps [5]. These traps are distributed in the STI volume, and their concentration is largly influenced by the manufacturing of the STI, and thus it is technology dependent. During the movement some holes get trapped in these sites and a space charge is built. The holes have a certain probability to get detrapped by thermal energy. The lifetime τ ox of the holes in the traps depends on the energy level of the traps, and of the temperature.
Holes which are not trapped in the silicon dioxide can move to the silicon to silicon dioxide interface. At this interface are incomplete or dangling atomic bonds due to the abrupt transistion from amorphous to christalline material. The dangling bonds manifest themselves as energy levels in the band-gap, and thus they trap mainly electrons or holes, depending on the Fermi-level of the silicon [5]. This trapping of electrons in the case of NMOS transistors (p-type silicon) and holes in the case of PMOS transistors (n-type silicon) degrades the transistor performance, and therefore usually the dangling bonds are deactivated by the manufacturer using hydrogen. The radiation induced free holes can react with the hydrogen and the dangling bonds get re-activated [5]. In this case they are commonly called radiation induced interface traps.
In the case of NMOS transistors the activation of the interface traps results in a negative space charge, while the trapping of holes in the STI results in a positive charge [4]. The electric fields compensate each other, so that the effective number of charges N ef f : becomes relevant, with N ox the number of trapped holes in the STI, and N if the number of electrons trapped at the interface. The parametrization of these two numbers during and after ionizing radiation is explained in the following.

Parametrization of the number of positive charges trapped in the STI
During exposure to ionizing radiation with a constant dose rate D the number of holes getting trapped in the STI volume is proportional to the exposure time t with a proportionality constant k ox D, where k ox describes how many holes are trapped per dose unit. At the same time, the trapped holes have a life-time τ ox in the traps, until they are free again and can move out of the STI. Therefore, the number of holes trapped in the STI is defined by the differential equation which is solved by If the irradiation stops after an exposure time t 1 , only the second term of equation (4) stays and results in and exponential decrease of the number of holes trapped in the STI, which is usually called annealing. This decrease can be described by where N trap describes the number of holes captured in traps of the oxide which are too deep for detrapping at the given temperature.

Parametrization of the number of activated interface traps
The number of activated interface traps follows a very similar behavior, as motivated here. The holes travelling to the silicon to silicon dioxide interface and activating the radiation induced interface traps are generated again with a constant rate k if D. k if describes here the number of holes available to activate interface traps per dose unit. The number of interface traps that can be activated by the radiation is technology dependent and it is limited. Therefore the probability that the holes activate new interface traps decreases with time exponentially. This can be described equivalently using the analogue equation The needed temperature to anneal the interface traps is known to be well above room temperature and even more above the operational temperature of the ASICs. It is technology dependent and in the range of 100 • C to 300 • C. Therefore, the annealing of the interface traps is negligible for the presented parametrization.

Summary of the parametrization
The complete formula for the leakage current during irradiation is therefore given by and by for During the periods with no incident ionizing radiation (dose rate D = 0) N ox is similarly replaced by equation (6), and the number of activated interface traps N if stays constant because they do not anneal at the considered temperature range. Figure 4 presents the resulting leakage current increase as a function of time during an exposure to ionizing radiation with a constant dose rate. The exponential decrease step in the far right of the plot illustrates the annealing behavior when the radiation is switched-off. For many studies the leakage current is given as a function of the TID. The parametrization can be expressed during periods of constant instensity exposure Time Current Figure 4: Plot of the leakage current parametrization as a function of the time, including the abrupt switch-off of the ionizing radiation, resulting in the exponential decrease.
The temperature dependency of the parameters is not explicitely included here.
The generation of the positive space charge depends on the temperature. This can be modelled sufficiently well with a temperature dependent de-trapping probability, and neglecting the temperature dependence of the electron and hole mobility and generation [7] [11]. Then only τ ox directly depends on the temperature. The generation of the interface traps is also expected to be a function of the temperature, but it is not well known. A dedicated measurement campaign is ongoing to provide the data that are needed for the extraction of the temperature dependence of these terms. As these data are not yet available, here the parametrization is used to describe the measured leakage current increase at a given temperature.
In the following two sections this parametrization is first fit to published data of single NMOS transistors. Then the same function is used to describe the supply current shift of the ATLAS IBL pixel readout chip FE-I4 [12] as an example of the consequence of the leakage current shift for the ASIC operation in radiation intense environments. This is an example for the power of this parametrization to predict the ASIC supply current increase once the basic parameters are known for the given technology.

Fit to single transistor data
Equation (8), (9) and (10) are used to describe the leakage current shift of single NMOS transistors produced in a 180nm silicon on insulator (SOI) process [13]. The data have been published previously in [14], and were obtained at a dose rate D of 9 Mrad h −1 at a temperature of ∼ 25 • C. Because the proportionality factor K appears in the parametrization only in products with the other parameters, K was fixed to a value of 1 × 10 −19 A per effective charge carrier. The threshold charge N thr , the time constants τ ox and τ if , as well as the proportionality constants k ox and k if are free fit parameters. The data and the function are shown in figure 5 to 7 and demonstrate the good agreement of data and parametrization on single transistor level.

Fit to full ASIC supply current shift
ASICs composed of a large number of linear NMOS transistors can show a significant supply current shift when operated under ionizing radiation. This supply current shift is a serious challenge for the ASIC operation and impacts the design of the system, because the services need to be able to cope with this shift. The amplitude of the increase depends on the environmental conditions, such as dose rate and temperature. An intense investigation program is currently carried out on ATLAS FE-I4 readout chips. The ASIC, produced in IBM 130 nm technology, is composed of about 80 million transistors, and HBD techniques are not used for the large majority of the transisors. The ASIC is operated under controlled environmental conditions while being exposed to x-ray radiation. The supply current is measured as a function of the exposure time.
This measurement is carried out for various dose rates and temperatures. Some preliminary results are public [15] and used here to demonstrate the ability of the parametrization to describe the supply current shift of full ASICs. Figure 8 shows the fit to the supply current of the ASIC as a function of the exposure time using 120 krad h −1 dose rate at 38 • C. The same parameters are as in section 3 free during the fit, while K is fixed now to 1 × 10 12 A per effective charge in order to account for that the supply current is the convolution of the leakage current of about several ten millions of transistors. Additionally, the pre-irradiation supply current is added as offset. At the time t 1 = 215 500 s the irradiation was switched-off and the annealing as described in equation (6) is shown. The parameters are fit to the time interval 0 to t 1 only. For the annealing the same parameters are used, especially the same time constant τ ox . This reflects that the annealing is caused be the same process as the saturation of the number of positive charges trapped in the oxide during irradiation. Figure 9 shows the same fit to data taken at different temperature (15 • C). A slightly higher amplitude of the increase is observed, as expected  10 are taken again at 15 • C, but using a higher dose rate of 420 krad h −1 . The current maximum is significaltly higher due to the larger dose rate.
The exact dependencies of the fit parameters from the temperature and from the dose rate are currently under investigation. The good agree-  ment between the parametrization and the data demonstrate the power of this parametrization to predict the supply current during operation in radiation environment, once the basic parameters have been measured for the ASIC in the laboratory.

Conclusions
The presented parametrization of the leakage current of NMOS transistors uses simplified transfer characteristics of the parasitic source to drain transistor along the STI. The good agreement of single transistor measurement data and the resulting function show that the description of the gate potential and threshold voltage by the effective number of charges and threshold charge, as well as the description of their concentration as a function of the exposure time describes the observations. Furthermore, the parametrization can directly be used to predict the supply current increase of full ASICs in radiation environment, when HBD techniques are not used for the majority of transistors, once the parameters are known as a function of dose rate and temperature.