Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.


Introduction
The CERN laboratory has approved in 2016 the High Luminosity LHC project, HL-LHC, that will allow the detailed exploration of the TeV scale up to nearly 10 TeV. HL-LHC will increase substantially the rate of pp collision in order to reach 3000 fb −1 integrated luminosity in a decade period: precision measurement in the Higgs sector, searches of new particle at high masses and studies of rare B-decays will be possible.
Several experimental challenges have to be addressed in order to have fully performant experiments at HL-LHC, and therefore CMS and ATLAS have started since few years vigorous upgrades programs. In particular the particle fluxes, radiation dose and data bandwidth become more and more important when moving closer to the interaction point and the pixel detectors have to work in extreme conditions that require a vigorous R&D program both for electronics and sensors.
The CERN RD53 collaboration [1][2][3][4] was constituted in 2013 with the purpose to develop pixel readout Integrated Circuits (IC) for the next generation of pixel readout chips to be used for the ATLAS and CMS Phase 2 pixel detector upgrades and future CLIC pixel detectors. The IC challenges include: smaller pixels to resolve tracks in boosted jets, very high hit rates due to unprecedented particle fluence, much higher output bandwidth, radiation and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. Nineteen institutes from nine countries, for a total of about 120 members are part of RD53, with almost equal contributions from CMS and ATLAS experiments. This paper describes the main achievements of RD53 and in particular the steps towards a large scale prototype (about 2 cm 2 ), called RD53A readout chip(ROC). The main choices of the collaboration can be seen in the specification of RD53A, details can be found in [5] but the main ones are described in table 1. The maximum pixel rate has been derived from full simulation of ATLAS and CMS pixel detectors, assuming an inner layer at around 3 cm radius and a pile-up of 200. The ROC has been considered to be connected to a silicon detector with characteristics taken from the current R&D, in term of thickness (100-150 µm), pixel aspect ratio, capacitance and leakage current.

Analog Very Front End electronics and IP-blocks
Four different analog very front-ends (VFE) (CSA,1 discriminator, signal processing) have been developed [6,7]. All designs are: compact with area below 35 × 35 mum 2 ; low-noise with ENC below 100 electrons for a value of input capacitance of 50 fF typical for a silicon sensor; low power; fast, allowing correct time-stamp with 25 ns accuracy. Three designs use 4-bit Time Over Threshold technique (ToT) for signal digitisation, while one using a flash-ADC per pixel is limited to 3-bit in order to limit power consumption. All VFE are capable to provide to each pixel 10 nA leakage current to a silicon sensor. The main characteristics of the VFE are listed in table 2. A total of

Small demonstrators and RD53A prototype
Two small size demonstrators, consisting of a matrix of 64 × 64 pixels of dimension 50 × 50 µm 2 have been designed as intermediate step before moving to the design of a large scale prototype, and 1Charge Sensitive Amplifier -2 -   table 4. together with a comparison to RD53A. The pixel matrix digital architecture is distributed in single pixel regions providing hit local storage: only data relative to events trigger by the experiment are sent to the chip periphery (trigger matching). Additional sharing of digital circuitry comes with the adoption of digital cores that include several pixel regions. In order to allow this sharing, both in the horizontal and in the vertical direction, the VFE's have been organized into analog islands of (2 × 2) pixels.
The FE65-P2 demonstrator has been produced in the end of 2015. It is an evolution of the FEI4 chip, with a strong contribution from the institutes that designed it. The higher granularity is achieved thanks to the use of the CMOS 65 nm: the digital architecture in the pixel matrix is in particular strongly based on the (2 × 2) pixel regional architecture and the distributed latency buffers. Particular care has been taken to separate analog and the digital circuitry, placing them in separate triple wells isolated from the silicon substrate, to prevent pick-up from spoiling the analog noise performance. The triple well separation has been extended also to the chip pads. Early results have been obtained with bare chip and after the bump-bonding with planar silicon sensors. Preliminary measurements results on bare and bump-bonded devices show 40 e − ENC and 800 e − minimum threshold.
The CHIPIX65-FE0 demonstrator [12] has recently arrived from production in September 2016 and therefore has integrated several building blocks of the collaboration. The design has been developed independently from FE65P2, with different design team and exploring other solutions to -3 -solve similar challenges: only analog circuitry has been placed in triple well, while the digital is directly on the substrate; the concept of pixel region has been extended to (4 × 4) pixel, in order to share digital circuitry to a larger number of pixels, and to do so the local data storage is centralized. The CHIPIX65-FE0 integrates several RD53 building blocks and other two VFEs. This has allowed the development of the bias distribution of the whole chip together with a monitoring scheme of all current and voltage needed to the VFE, that has been eventually adopted and extended to RD53A. Early results show that the CHIPIX65-FE0 works correctly and the bare devices show 85 e − ENC and 500 e − minimum threshold.
The design of a large prototype of about 2 cm 2 and 400 × 192 pixels (columns and rows), called RD53A, is progressing well, with the effort of a focused team of about ten designers working together, merging the FE65-P2 and the CHIPIX65-FE0 design team plus additional designers. The floor-planning of the chip has been defined identifying several blocks with the chip periphery subdivided in the Analog-Chip-Bottom (ACB), the Digital-Chip-Bottom (DCB) and the I/O-frame.
The pixel matrix will consist of a matrix of (8 × 8) pixels cores and will be subdivided into the four VFE designs: their integration in RD53A is well advanced, since three designs have already been working in the demonstrators. The area reserved for the digital architecture in the pixel region is rather full, due to the long trigger latency and the high particle flux. Moreover requiring a more radiation hard design implies increasing the total area, as it forces to use larger than minimum size transistors and also larger buffers to preserve fast transitions and good timing. Solutions are under study and are evaluated for the two different architectures that have been used in the demonstrators.
In the periphery, the ACB includes all the biasing blocks and the monitoring, plus additional building blocks like the CDR/PLL generating the high frequency clock and recovering the data for the chip, the Power-on-Reset (POR) and the temperature sensors. The DCB, shown in figure 1, includes a Ch-Synch that generates the 40 MHz clock, synchronizes all the data input and sends it to the Command Decoder (CMD) to broadcast in-time commands and configuration data to the chip. Alternatively a JTAG can be used for the configuration of the chip. The pixel matrix data go to the Data Builder, then to an output FIFO and are encoded using an Aurora64/66 algorithm [13]. The data will be serialised either with four outputs at 1,28 Gbits/s or with a unique 5 Gbits/s and then sent to the I/O.
A fundamental feature of RD53A is the implementation of serial powering: for this reason the chip includes two Shunt-LDOs [14], one dedicated to analog and the other to digital power, providing stable voltage to the chip while requiring a constant current and a constant output voltage. A maximum power consumption is defined and variations from it are absorbed by the shunt resistor. It is important to analyse the variation in time of current consumption, specially for the digital circuitry, that is strongly dependent on the particle flux and has a clocked activity. For this reason a sophisticated simulation and verification environment [15] of the digital architecture has been used.

Radiation effects
The degradation of the performance of 65 nm MOSFETs upon radiation exposure was investigated, using 10-keV X-rays as in previous studies but also using 3-MeV protons. X-rays provide a good way to compare old with new data, even though very long exposure times are needed to reach TID levels up to 1 Grad: a review of the results can be found in [16]. The results show significant degradation above 100 Mrad, particularly in core minimum size pMOSFETs. In order to obtain -4 - increased radiation hard tolerance, minimum size MOS have to be avoided. Models that parametrize the effect of TID on MOS performance have been defined according to the measurements made, in particular for 200 and 500 Mrad.
In the design of analog circuitry and of building blocks, the use of very small MOS has been avoided: in case of need a set of custom digital cells has been designed. All crucial building blocks and very front end analog chains needed for RD53A production have been designed and sent for production: most of those have been successfully tested before and after 5-800 Mrad total dose. In particular an irradiation up to 6-800 Mrad for VFE-2 and VFE-3 showed a slight decrease (below 5%) in the gain of the pre-amplificaiton stage, an increase of 10-20% in the noise and a higher peak time, but without a substantial compromise of the performance.
A chip has been designed to study the effect of TID on several different types of standard cell libraries provided by the foundry (Digital-RAD, DRAD chip). In particular ring oscillators have been designed in different flavors, so to measure how much the digital transitions are slowed down by irradiation. The intention is to evaluate how the radiation models describe correctly the degradation of performance, so that the digital design can be implemented with more robust cells. The modification of digital standard cells, with larger dimension where needed, is also an on-going activity of RD53. Early results show for 200 Mrad an average increase of 5-15% in gate delay or speed reduction, depending on the dimension of the cell.

Conclusions
The pixel detectors for the future upgrade of HL-LHC require a new generation readout chip (ROC), to provide higher granularities and extraordinary performance in term of noise, speed, data storage and readout, including to survive to unprecedented levels of radiation fluence and dose.

JINST 11 C12058
The RD53 collaboration is a common effort of experts from ATLAS and CMS communities focused on the deliverable of a large scale prototype of a pixel chip satisfying the main specification of the CMS and ATLAS experiments for the HL-LHC. Building blocks, VFE, and small demonstrators showed very promising results. The important deliverable of RD53A, with an area of about 2 cm 2 , is progressing very well and is planned for spring of year 2017. RD53A will be fully characterized as bare chip, after the bump-bonding to different silicon detectors defined by the sensor R&D and after irradiation.