Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.


Introduction
Active pixel sensors based on the High-Voltage CMOS (HV-CMOS) technology [1] are promising candidates for the next generation of pixel tracking detectors in High Energy Physics experiments. The operating principle is based on a thin p-type silicon bulk containing a deep n-well that implements CMOS pixel electronics (e.g. preamplifier, discriminator). A reverse bias voltage is applied to the diode formed by n-well with respect to the substrate to create a depletion region. The charge carriers, created by ionization, drift towards the n-well that acts as a collecting electrode. As the transistors are physically isolated from the substrate, a relatively high bias voltage (∼100 V) can be applied to enlarge the depletion zone. A readout ASIC coupled to the HV-CMOS sensor is used to collect the signal and perform further digital processing. This paper reports on the testbeam results obtained for a HV-CMOS sensor prototype produced in 180 nm technology by ams AG [2] (AMS). This manuscript is organized as follows. Section 2 describes the experimental setup and the telescope used for track reconstruction. Section 3 describes the Device Under Test (DUT). The offline analysis framework is briefly explained in Sec. 4. Finally, Sec. 5 presents the main results.  Figure 1: A rendered view of the FE-I4 beam telescope. The coordinate system is defined with the Z-axis along the beam-axis, the Y -axis pointing vertically upwards and the X-axis pointing horizontally.

Experimental setup
The AMS HV-CMOS detector prototype was tested in November 2015 at the H8 beamline of the CERN Super Proton Synchrotron (SPS), that provided a 180 GeV π + beam. A dedicated beam telescope (hereafter called FE-I4 telescope) was used to provide a standalone measurement of the trajectories of the incoming particles independently of the device under test.

The FE-I4 beam telescope
The FE-I4 telescope [3] consists of six ATLAS Insertable B-Layer (IBL) [4] double-chip (DC) pixel modules [5] arranged in two arms of three modules each (see Fig. 1). Within a given arm, the first and last planes are installed vertically, with the most precise pixel coordinate (50 µm-pitch, see below) along the Y -axis. The module in the middle is rotated by 90 • to improve the spatial resolution along the X-direction. Each DC module uses a 200 µm-thick n + -in-n planar silicon sensor produced by CiS [6]. The detector is segmented in a matrix of 336 rows × 160 columns with a pixel size of 50 × 250 µm 2 . The p + back-side implant used for the high-voltage bias is surrounded by 13 guard rings shifted under the edge pixels, with a resulting total inactive area of only 200 µm from the sensor edge. Two FE-I4B [7] ASICs produced in IBM 130 nm CMOS technology are bump-bonded to the detector for the signal readout. Although the sensor can be readout by two ASICs, only one of them was active during data-taking. The chip active area of 20.2 × 16.8 mm 2 holds 26'880 identical 50 × 250 µm 2 pixels organized in a matrix of 336 rows × 80 columns. Each pixel cell contains a two-stage amplifier followed by a discriminator with adjustable threshold, so that collected charge is translated into a 4-bit Time-over-Threshold (ToT) value measured in units of 25 ns (Bunch Crossing units or BC, corresponding to the LHC bunch spacing). The digital architecture is implemented such that four analog pixels share one common logic cell. The hit information is stored locally at the pixel level until reception of a trigger signal. For test and calibration purposes, a test charge with selectable amplitude can be directly injected into each pixel pre-amplifier input. A threshold tuning Digital-to-Analog Converter (DAC) is used to apply a per-pixel threshold correction. At this testbeam, the discriminator thresholds of the telescope modules FEs were tuned to a charge of 2 ke − , with a final threshold dispersion of 70 e − . The ToT to charge conversion was tuned for each pixel to 9 ToT units for a deposited charge of 16 ke − .

Data Acquisition System
The Data Acqusition System (DAQ) of the FE-I4 telescope is based on the Reconfigurable Cluster Element (RCE), a generic computational element for DAQ systems developed at SLAC and based on System-on-Chip (SoC) technology. An Advanced Telecommunication Computing Architecture (ATCA) crate integrates several RCEs that are connected via optical links to a High Speed Input/Output (HSIO) development platform. The HSIO is a custom-made board based on the Xilinx Virtex-4 [8] FPGA developed by SLAC as a generic DAQ interface for both ATLAS Pixel and Strip detectors.

Trigger
The FE-I4B ASIC can provide a HitBus signal corresponding to the logical OR of selected pixel discriminator outputs. In the testbeam, the trigger signal for event acquisition is given by the coincidence (within one BC) of the HitBus signals of the first and last telescope modules. A pixel mask applied to the FE-I4B allows a precise definition of a Region-Of-Interest (ROI) on the triggering planes. By setting the ROI size to slightly exceed that of the device under test the data acquisition rate is optimized. A trigger rate of ∼18 kHz has been measured with the telescope in standalone mode (without DUT), and of ∼6 kHz with up to two FE-I4-based DUTs [3].

Device under test
The DUT, referred as AMS180v4, is the fourth version of a series of prototypes produced in the HV-CMOS technology by the AMS foundry. The AMS180v4 has been produced in 180 nm with the AMS H18 process. The unit cell structure contains six pixels arranged in two columns and three rows, each pixel having an area of 125 × 33 µm 2 . The substrate resistivity is 20 Ω · cm. The sensor (see Fig. 2a) has a total size of ∼ 2.4 × 2.9 mm 2 , a thickness of 250 µm and it implements various pixel types. The results presented in this paper correspond to the baseline flavour, so-called STime, where each pixel implements a two-stage amplifier followed by a discriminator with tuneable output amplitude. Though the discriminator threshold is common to all pixels in the sensor, a 4-bit DAC (TuneDAC or TDAC) is used to provide a per-pixel threshold dispertion correction. The sensor has been designed to be compatible with either a pixel or a strip readout chip. For this measurement, a FE-I4B pixel readout ASIC was capacitively coupled to the HV-CMOS sensor by means of a < 1 µm-thick epoxy glue layer (see Fig. 2b). The SET ACCµRA 100 flipchip bonder [9] was used to bond the assembly with a post-bonding accuracy of 1 µm and good coplanarity (maximum deviation of 100 nm over a total length of 2.9 mm). After assembly, both the HV-CMOS sensor and the FE-I4B ASICs are wire-bonded to auxiliary boards (see section 3.2), providing all input voltages and control lines for both ICs.
As the FE-I4B pixel size is 250 × 50 µm 2 , the unit cell, made by six HV-CMOS pixels, corresponds to two FE-I4 pixels (see Fig. 3). In this respect, we define macro-pixel as the set of three HV-CMOS single pixels (half the unit-cell) connected to a single FE-I4B readout pixel. For simplicity of operation in the testbeam, the signal amplitude of the discriminator output of each of these three sub-pixels were set to the same voltage level.

Charge calibration
In order to perform a voltage-to-charge calibration, a setup with a 55 Fe radioactive source was used. The most intense emission of this X-ray source is at 5.9 keV (K α peak). Photons are absorbed in the silicon bulk creating photoelectrons that can then be collected. The 55 Fe spectrum was recorded by monitoring with an oscilloscope the output signal of a single pixel after the amplification stage. The measurement was performed at room temperature with the sensor biased at 80 V. In order to estimate the intrinsic noise level of the setup, a first acquisition without the source was performed. The threshold of the oscilloscope was then set at five times the r.m.s. of the (Gaussian-distributed) noise distribution. By determining the position of the K α peak and assuming 3.65 eV as the ioniza-  tion potential for silicon at room temperature, the resulting calibration factor is ∼8.6 e − /mV. The nominal operating threshold of the sensor corresponds to ∼600 e − .

Threshold tuning
The powering, configuration and control of the AMS180v4 prototype was performed using the CaRIBOu [10] (Control Readout Itk BOard) test system. CaRIBOu is a modular readout system developed by the Brookhaven National Laboratory and the University of Geneva groups to characterize HV-CMOS sensor prototypes in laboratory and testbeam measurements. A Xilinx Z0706 evaluation board [8] with embedded ARM processor, based on the Zynq R -7000 All Programmable SoC, acts as main DAQ board. The system comprises various additional custom-designed and interconnected boards (see Fig. 4): • The CaR (Control and Readout) board provides powering rails, adjustable bias DACs, CMOS level translators, LVDS and clock signals, a digital injection circuitry and ADC channels. It is connected to the Xilinx Z0706 board via a FPGA Mezzanine Card (FMC) to a Very-High-Density Cable Interconnect (VHDCI) interface.
• The FE-I4 board contains the external high-voltage input for the sensor bias, the bonding pads for the FE-I4B ASIC and the required circuits for both the HV-CMOS and the FE-I4B ASIC.
• The CCPD board simply contains passive SMD components and the bonding pads for the HV-CMOS sensor. The CCPD board is attached to the FE-I4 board via a PCI Express miniconnector. While the Z0706 and CaR boards were used to configure and control the HV-CMOS sensor, the glued FE-I4 chip was readout by the same RCE system as the telescope. A binary tuning procedure was implemented to minimize the threshold spread among all channels of the sensor. The tuning method consists in selecting a target threshold and then finding the optimal TDAC setting for each pixel so that the resulting threshold is close to the target within a defined tolerance. At each threshold scan, the TDAC is varied by a single unit step. A Gaussian fit to the threshold distribution obtained in the DUT after tuning resulted in a mean and sigma of 607 e − and 73 e − , respectively.

Off-line analysis
The raw data from all six telescope planes and from the DUT are stored in ROOT [11] format for off-line processing. The software analysis framework is based on the Judith [12] program, a C++ software package originally developed for the Kartel telescope (composed of six MIMOSA-26 pixel sensors [13]). The Judith package has been adapted for the FE-I4 telescope configuration and module geometries. The off-line analysis compares the response of the DUT to tracks reconstructed with the beam telescope. The internal alignment of the different telescope planes is performed using an iterative algorithm that minimizes the track residuals, i.e. the difference between the hit position measured in the plane being aligned and the predicted hit position from the track extrapolation into that plane. Noisy pixels are masked at software level before clustering. The first telescope plane is kept fixed at its nominal position as an anchor reference to define the Xand Y -axis. The track reconstruction algorithm recursively searches for clusters in consecutive planes within a limited solid angle to deal with multiple scattering. A straight line fit is then performed to the different cluster positions. The alignment algorithm corrects for the translations in the transverse plane and for the in-plane rotation around the Z-axis. Results from the telescope alignment can be found in [3]. Upper limits on the spatial resolution of the telescope were found to be 11.7 µm and 8.3 µm at the DUT position.
After the internal alignment of the FE-I4 telescope, reconstructed tracks are used to align the DUT. Due to the small size of the HV-CMOS sensor there was not enough sensitivity to correct for the in-plane rotation, so in this case only the two translations were considered. Single track events were selected. Tracks were required to have one hit in each of the six telescope planes, a good χ 2 from the track fit and small track gradients with respect to the beam axis.

Cluster size distributions
The cluster size is the number of neighbouring pixels (along both measuring directions) with a signal above threshold. It is an effective measurement of charge sharing. Figure 6 shows the cluster size distribution for the DUT at nominal operating conditions (85 V bias-voltage and 600 e − threshold). At the SPS testbeam the track incidence was almost perpendicular to the detector planes. In ∼78% of the events single-pixel clusters were recorded, while clusters formed by two pixels were observed in ∼20% of the cases. The occurrence of clusters with sizes of three or more pixels was less than 2% and thus can be safely neglected in what follows. Among the possible mechanisms leading to signal leakage into neighboring pixels (e.g. cross-talk between channels from capacitive coupling, diffusion of charge carriers, δ -electrons), diffusion is the dominant one. This diffusion component is only relevant for unirradiated sensors, as it is largely suppressed by Figure 6: Cluster size distribution for normal incidence tracks and nominal operating conditions. The distribution has been normalized to unity.
charge trapping for fluences typically above 10 15 n eq /cm 2 , as measured on irradiated HV-CMOS prototypes with an edge-TCT technique [14] and with testbeam data [15]. Figure 7a shows the timing distribution (i.e. the timestamp difference of the recorded hit with respect to the trigger in units of BC, see Sec. 2.1) for all cluster sizes. The distribution shows a long tail of late (slow) hits. This tail is mainly due to a known timewalk effect in this HV-CMOS sensor design [15], so that low amplitude signals such as resulting from diffusion have a larger timing because of the slower discriminator rise time. In Figs. 7b and 7c we investigated the contribution from clusters of size one and two, respectively. In the latter case, the timing of both hits in the cluster are shown. The timing distribution of clusters of size one is very similar to that of the fastest hit of the two-pixel clusters. The slowest signals in the tail of the distribution of Fig. 7a thus correspond to the diffused charge in large multiplicity clusters (charge sharing). In order to focus on the properties of the charge collected by drift, and to limit the effects of the known timewalk present in this version of the HV-CMOS sensor, only results for the fastest hit are shown in the following.

Efficiency
One of the most important parameters to be studied of the AMS180v4 prototype is the tracking efficiency. For this measurement, a detector plane is considered to be efficient if the interpolated track position is located within an ellipse centered around the measured cluster with semi-axes being one and a half times the size of the macro-pixel (see Fig. 8). The lengths of the ellipse semiaxes correpond to five times the standard deviation of the residual distributions (see Fig. 5). The cluster position is computed as the geometrical center of the macro-pixel. Single track events and the track quality cuts as defined in Sec. 4 are used. The interpolated track position is required to be inside the DUT sensitive area, otherwise the event is discarded. The efficiency of a macro-pixel is thus simply computed as ε = N eff /N tot , where N eff is the total number of efficient events in the pixel as just defined, and N tot is the total number of selected events. Inefficient events are taken into account (these are events in which for a valid track interpolation at the DUT position, no hit has been measured in the DUT). Fig. 9 shows the resulting efficiency map for a bias voltage of 85 V and a threshold of 600 e − . Excluding the outermost columns and rows to avoid edge-effects due to the finite telescope resolution, an average global efficiency ofε = 99.7% is obtained.
Thanks to the pointing resolution of the FE-I4 telescope [3] a sub-pixel resolution was achieved. Fig. 10a shows the efficiency map after merging all STime pixels into a single histogram representing a macro-pixel (125 × 100 µm 2 , corresponding to three HV-CMOS pixels connected to a single FE-I4B readout channel). Figs. 10b to 10d show the relative contributions to the efficiency of different cluster sizes. The high efficiency in the central region of Fig. 10a results dominantly from events where the cluster size is exactly one (∼78% of the cases, see Fig. 6). Events with a cluster size of two (∼ 20% of the cases) contribute mainly to the edge regions, as expected from charge sharing between neighbouring pixels. The less common events in which the cluster contains three or more pixels are localized at the four corner regions.
The efficiency as a function of the discriminator threshold is shown in Fig. 11 for a bias voltage of 80 V. As expected, the efficiency drops in the low-threshold (noise dominated) and highthreshold (low signal) regions. The region for which the efficiency is higher than 99.5% is between   The efficiency as a function of the sensor bias voltage is shown in Fig. 12a for a threshold of 600 e − . The large statistical uncertainty of the first data point (10 V bias voltage) is due to the fact that, accidentally for this particular run, the ROI region was not set. Fig. 12b shows the in-pixel efficiency for a bias of 20 V (to be compared with Fig. 10a where the bias voltage was 85 V at the same threshold). The lower depletion region is source of inefficiencies at the pixel edges. Overall, the relatively high efficiency at lowest bias voltages indicates that, in addition to drift, part of the charge is collected by diffusion. The efficiency has been evaluated in each of the sixteen 25 ns time intervals used for the readout of the DUT. Figure 13a shows the efficiency per time-bin for different bias voltages for the fastest hit in the cluster. The shape of the distributions are similar to that already shown in Fig. 7b. Due to some existing delays (e.g. different cable lenghts, clock-jitter) between the trigger and the DUT readout, it is assumed that the time-bin for which the maximum is reached corresponds to that of the passage of the incident particle. Most particles are detected in a two-bin interval. For increasing bias voltages the depletion region enlarges and the maximum efficiency increases. The reduced efficiency on the vertical edges is due to a higher charge sharing as from the finer pixel granularity along the vertical direction (the macro-pixel shown corresponds to three 125 µm × 33 µm pixels). Fig. 13b shows the cumulative efficiency as a function of 25 ns time-bins. The distribution has been computed with respect to the consecutive maxima in Fig. 13a. At 85 V bias voltage, an efficiency higher than 90% is achieved after three BCs. Figure 14 demonstrates the effect of the threshold on the timing distribution of the DUT. As the threshold is lowered, it can be observed that the dispersion of the time of arrival of the hits is reduced. This is further evidence of the large variation of the rise time of the signal. In the case where the rise time of the signal would be the same for small and large signal, a reduction of thresh-  old would only yield an increase in efficiency. However it is observed here that the improvement of the timing distribution spread is occurring even when the threshold is reduced within the plateau of efficiency featured in Fig. 11.

Conclusions
A HV-CMOS sensor prototype produced in the AMS 180 nm technology has been tested in November 2015 at the H8 beamline of the CERN SPS. A FE-I4B ASIC has been glued to the HV-CMOS sensor to read the signals via capacitive coupling. For the first time, the CaRIBOu system has been used to power, configure and control the AMS180v4 chip. A threshold uniformization using a binary tuning algorithm yielded a final threshold dispersion of ∼70 e − about a mean of ∼610 e − . The FE-I4 beam telescope has been used to reconstruct the tracks to evaluate the performance of the HV-CMOS prototype. An average global efficiency of 99.7% has been measured for a bias voltage of 85 V and an operating threshold of 600 e − . It has been measured that the sensor can be operated with an efficiency higher than 99.5% within a threshold range between ∼400 and ∼700 e − . The timing performance of this prototype is not yet sufficient to be operated in a HL-LHC experiment as an efficiency higher than 90% is measured within a three 25 ns BC window. New versions of the AMS chip have already been produced in both 350 and 180 nm technologies to improve the time response of the sensor.