Development of a sub-nanosecond time-to-digital converter based on a field-programmable gate array

The present time-to-digital converter (TDC) chips for the monitored drift tube (MDT) chambers at the ATLAS experiment will be replaced with new ones for the High-Luminosity LHC, expected to begin operation in 2026. The design and the performance of a 24 channel TDC with a variable time binning of down to 0.28 nsec based on a Xilinx Kintex-7 field programmable gate array are reported. The time measurement is provided by a multisampling scheme with quad phase clocks synchronized with an external reference clock. The differential and integral nonlinearities have been measured to be less than half of the time binning. The temperature dependence on the performance is observed to be small. In conclusion the obtained performance of the time measurement is sufficiently high for the use with MDT chambers.

: The present time-to-digital converter (TDC) chips for the monitored drift tube (MDT) chambers at the ATLAS experiment will be replaced with new ones for the High-Luminosity LHC, expected to begin operation in 2026. The design and the performance of a 24 channel TDC with a variable time binning of down to 0.28 nsec based on a Xilinx Kintex-7 field programmable gate array are reported. The time measurement is provided by a multisampling scheme with quad phase clocks synchronized with an external reference clock. The differential and integral nonlinearities have been measured to be less than half of the time binning. The temperature dependence on the performance is observed to be small. In conclusion the obtained performance of the time measurement is sufficiently high for the use with MDT chambers.

K
: Front-end electronics for detector readout; Particle tracking detectors (Gaseous detectors)

Introduction
The High-Luminosity LHC (HL-LHC) is expected to begin operation in 2026, with a nominal leveled instantaneous luminosity of 5 × 10 34 cm −2 sec −1 . The present time-to-digital converter (TDC) chips for the monitored drift tube (MDT) chambers at the ATLAS experiment [1] will be replaced with new ones to fully exploit the hit rate capabilities of the chambers with a new trigger and readout scheme [2]. The proposed new readout system fulfils not only the full detector readout rate at 1 MHz but also a new MDT hardware trigger at Level-0. A TDC based on a field-programmable gate array (FPGA) is proposed as a candidate for the HL-LHC. The advantages of developing a TDC with an FPGA are the flexibility of modifying the logic and the simplicity of handling high-frequency clocks and high-speed data transfer based on pre-implemented circuits. Figure 1 shows a simplified schematic of the readout system for the MDT chambers proposed for the HL-LHC. The TDC works in synchronization with a 40 MHz reference clock taken from the system of the LHC accelerator. There are two types of TDCs to be implemented. The TDC for the Level-0 trigger is a counter based TDC whose time binning is 12.5 nsec. On the other hand, the TDC for readout is based on a multisampling scheme using quad phase clocks, whose time binning is 0.78 nsec. There are 24 channels for both TDCs.
In this study, a demonstrator of the TDC for MDT chambers at the HL-LHC is developed using Xilinx Kintex-7 FPGA [3]. The performance of the time measurement is evaluated for the TDC for readout. The study is provided not only for the designed time binning of 0.78 nsec but also for a time binning down to 0.28 nsec, which provides useful information about TDC development using FPGAs. The study is provided also with temperature from −10 • C to 60 • C.   Figure 3 shows a picture of the demonstrator used for the evaluation of the TDC performance. The performance is evaluated for 8 out of 24 channels. The reference clock and the signals are provided from a pulse generator (Agilent 81150A [4]). The standard deviation of time difference between the two leading edges of the pulses is measured to be 30 psec. The data output from the TDC is read out using Ethernet.  The differential nonlinearity (DNL) and the integral nonlinearity (INL) have been measured. The DNL is defined for each bin as

Demonstrator and test setup
where T BIN is the ideal time binning and T i is the time difference between the specific bins i and i + 1. For the measurement of DNL, the output from the core of the TDC is read out for the time difference of the leading edges between the signal clock and the reference clock. By scanning the time difference between signal and reference clocks, the width of a typical time bin can be focused on. The scan is performed with a step size of 100 psec for the time binning of 0.78 nsec and 33 psec for 0.28 nsec.
The results of the measurement of the DNL are shown in figure 4 for the two cases. The measured DNL is less than half of the time binning in both cases. The nonlinearity is dominated by the time difference between signal paths in FPGA. We observe a periodic structure with a cycle of four bins, where the four bins correspond to the four divided signal paths illustrated in figure 2. The nonlinearity for the time binning of 0.28 nsec is larger than the one for 0.78 nsec since signal -3 -path difference with respect to the time binning is larger for the former. The obtained nonlinearity is consistent with the time difference between signal paths obtained from simulations, which is described in section 2. As a measure of the nonlinearity, the deviation σ is defined by The obtained value of σ for the time binning of 0.78 nsec (0.28 nsec) is 0.104 ± 0.004 (0.28 ± 0.01), respectively.
INL is parameterized in this study by where T input is the time difference between the leading edges of input signal clocks and T measured is the mean of the time difference measured by the TDC. The time difference is scanned up to 100 µsec.
The results of the measurement of the INL are shown in figure 5 for the two cases. The measured INL is consistent with zero up to 100 µsec. Table 1 shows the result of a linear fit using the parameterization INL = AT ideal + B. The uncertainty for the parameter A corresponds to 25 psec over 100 µsec range.

Measurement of the linearity depending on temperature
The temperature dependence of DNL and INL is evaluated using thermostat chamber ESPEC SH-641 [5].

Conclusion
A sub-nanosecond TDC has been developed using Xilinx Kintex-7 FPGA. The time measurement is provided with a multisampling scheme with quad phase clocks synchronized with a reference clock. The time binning is variable depending on the reference clock frequency. The performance is evaluated for the reference clock frequency of 40-110 MHz, which corresponds to a time binning of 0.78-0.28 nsec. The number of implemented channels is 24, eight of which are employed for the measurements. The differential nonlinearity is measured to be less than half of the time binning. The integral nonlinearity is consistent with zero up to the dynamic range of 100 µsec. Temperature dependence on the differential and integral nonlinearity is small in a range from −10 • C to 60 • C. No significant difference is observed between different channels. The obtained performance of the -5 -time measurement is sufficiently high for the drift time measurement of the MDT chambers at the ATLAS experiment. For the actual use of the FPGA-based TDC at the ATLAS experiment, the radiation tolerance needs to be tested.