Design of a constant fraction discriminator for the VFAT3 front-end ASIC of the CMS GEM detector

In this work the design of a constant fraction discriminator (CFD) to be used in the VFAT3 chip for the read-out of the triple-GEM detectors of the CMS experiment, is described. A prototype chip containing 8 CFDs was implemented using 130 nm CMOS technology and test results are shown.


A
: In this work the design of a constant fraction discriminator (CFD) to be used in the VFAT3 chip for the read-out of the triple-GEM detectors of the CMS experiment, is described. A prototype chip containing 8 CFDs was implemented using 130 nm CMOS technology and test results are shown.

K
: VLSI circuits; Analogue electronic circuits; Front-end electronics for detector readout

Introduction
The triple-GEM detector is a Micro Pattern Gas Detector (MPGD) that will be installed in the first station of the forward region (1.5 < |η| < 2.2) of the CMS muon spectrometer as part of its upgrade for the high luminosity phases of the CERN LHC [1]. One of the objectives of this upgrade is the improvement of the muon trigger efficiency, thus the time resolution is an important parameter to be considered for the correct assignment of the event to the LHC bunch crossing. The triple-GEM is made of four gas gaps separated by three GEM foils and the typical signal is shown in figure 1.
In CMS, the triple-GEM detector will be read-out by the VFAT3 front-end chip, currently under design, whose block diagram is shown in figure 2. The VFAT3 architecture is made of 128 channels, each one composed of a charge sensitive preamplifier, shaper and comparator. The comparator output is then synchronized with the LHC clock and sent both to a fixed latency path  for trigger signal generation and to a bunch of memories for storage and readout. The front-end amplifier is programmable in terms of gain and pulse shaping time, in order to adapt it to a wide range of gaseous and silicon detectors [1].

Simulation
The time resolution, which is an important parameter for the use of the GEM detectors at the first CMS trigger level, has been studied with Monte Carlo simulations. The simulations are based on the GARFIELD [2] software to compute the CMS triple-GEM signals, taking into account the ionization statistics, the charge drift and amplification processes inside the gas volume of the detector [3]. The detector signal is then convolved with the expected transfer function of the front-end amplifier of VFAT3 chip and the time resolution (figure 3) and latency (figure 4) for various VFAT3 peaking times are computed using the constant fraction discriminator (CFD) and the time-over-threshold (TOT) techniques.
The simulation study showed that it was possible to extend the VFAT3 front-end shaping time in order to fully integrate the GEM detector signal charge and avoid ballistic deficit and that the most efficient method, in terms of combined time resolution and latency, is the CFD method. Using this

CFD implementation 3.1 Principle of operation
Constant fraction discrimination is a technique to provide amplitude-independent information about arrival time of an event. The principle operation is based on detecting the zero-crossing of the bipolar pulse obtained by subtracting a fraction of the input unipolar signal to its delayed copy ( figure 5). It can be demonstrated that the bipolar pulse crosses the baseline at a fixed time with respect to the start of the pulse [4].

Architecture
Several practical implementations of integrated CFD have been proposed in literature [5]. In this project, the solution proposed by S. Garbolino et al. [6] has been adopted. It is based on a fully differential architecture for better noise rejection and the delay and fraction implementation is realized using a shaping network with the cross-coupling topology shown in figure 6. Since the VFAT3 analog front-end will have a programmable shaping time ranging between 25 ns and 100 ns, the same programmability has been introduced in the time constants of the CFD shaping network, in order to fully exploit the CFD technique for each VFAT3 shaping time. The resulting    figure 7. The differential input signals are sent to the shaping network and the resulting bipolar pulses are amplified by the post-amplifier that recovers the signal attenuation introduced by the passive shaping network and also applies a dynamic offset compensation. Finally, the differential bipolar pulses are sent to the zero-crossing (ZC) comparator that produces a digital pulse whenever its differential input crosses the baseline. The input signals are sent in parallel to an arming circuitry, in order to enable the CFD output only when the input signal is larger than the programmed threshold provided by a global 8-bit digital-to-analog-converter (DAC). Moreover, both arming and ZC comparators of each channel have their own 6-bit DAC to compensate mismatches among channels.

Prototypes
A prototype chip containing 8 CFDs has been produced using 130 nm CMOS technology to prove the effectiveness of the proposed technique before its integration in the VFAT3 chip. The biases and thresholds are provided by internal DACs remotely controlled by an SPI interface. The test setup, shown in figure 8, consists of an arbitrary waveform generator (Lecroy Arbstudio 1102) capable of injecting into the chip inputs two semi-gaussian differential signals with tunable amplitude, peaking time (25 ns to 100 ns) and offset, and a 10 GS/s oscilloscope to perform the measurement on the outputs. Finally, a custom SPI controller allows to write/read the internal DACs, while a multimeter can be used to monitor internal voltages/currents. First of all, the local DACs have been set to equalize the channel thresholds. Then, using a global threshold of 10 mV, a set of time measurements have been performed injecting differential pulses with amplitude ranging between 10 mV and 1 V for different peaking time.

Test results
In figure 9 a comparison between the timing response of the arming comparator (on the left) and the CFD (on the right) for Tpeak = 100 ns are shown: it can be noticed that, skipping the point at the threshold of 10 mV, the arming comparator exhibits an amplitude time walk in the order of some tens of ns, while the CFD time response is almost independent of the input amplitude, showing a residual time walk < 1 ns for the individual channel and < 2 ns considering the 8 channels of the chip. Similar results are obtained also for the other peaking times. The rate capability depends on the peaking time and ranges between 400 kHz for Tpeak = 100 ns and 1 MHz for Tpeak = 25 ns. Another set of measurements was performed to evaluate the double pulse resolution. Two consecutive pulses with different amplitude and different time spacing ∆T (figure 10) were sent to the CFD: using signals with Tpeak = 75 ns, a large pulse (1 V) can be followed by small pulse (20 mV) after t > 1.5 µs with no timing degradation, while if Tpeak = 25 ns, a large pulse (1 V) can be followed by small pulse after t > 800 ns with no timing degradation.

Conclusions
The measurements on the CFD prototypes confirm the effectiveness of the proposed implementation and encourage us to use it in the VFAT3 chip for time walk correction when using peaking time longer than 25 ns.