Radiation Tolerance of 65nm CMOS Transistors

We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.


Introduction
The need for extremely radiation tolerant electronics is one of the major issues confronting high energy physics in the era of High Luminosity running at the CERN [1] Large Hadron Collider (HL-LHC). Tests by Bonacini, et al. [2] at CERN, published in 2012, established 65 nm CMOS as the leading candidate technology for HL-LHC electronics. Using an X-ray beam, Bonacini, et al. exposed 65 nm transistors to a total dose of 200 Mrad. Their results showed, with one exception, relatively small changes in transistor parameters for normal layout standard gate oxide thickness (core) transistors. The exception was a dramatic loss of maximum drain-source current in the narrowest PMOS transistors. The CERN group concluded that 65 nm CMOS technology could be used for HL-LHC applications with no special design considerations, except that all core devices should have width greater than 360 nm. The RD53 collaboration was formed in 2014 to further explore the feasibility of using 65 nm CMOS technology to design a pixel readout chip for use at the HL-LHC [3]. The group established a total ionizing dose tolerance goal of 1 Grad. The measurements reported in this paper were done in the context of RD53. Discussions late in 2013 within RD53 centered on the fact that the data presented in reference [2], and also subsequent data collected by the CERN group and by a group from CPPM [4], contain evidence of significant room temperature annealing during the time between X-ray exposures. Both CMS and ATLAS currently plan to operate their HL-LHC pixel vertex detectors at approximately −20 • C. This choice is because the silicon strip trackers will operate at −20 • C in order to limit leakage current in the silicon sensors, which would otherwise require much more cooling and therefore more mass in the tracking volume. Concern was expressed that because of reduced annealing, 65 nm circuits might experience greater radiation damage than had been observed in room temperature exposures if the circuits were maintained at −20 • C during irradiation.
We report the results of an irradiation of 65 nm transistors performed using the Gamma Irradiation Facility [5] at Sandia National Laboratories [6]. The devices under test were maintained at a temperature −20 • C during irradiation.

Test ASIC
A 65 nm CMOS Application Specific Integrated Circuit (ASIC) containing individual transistors connected to wire bond pads was designed at Fermilab and fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) [7].1 The test ASIC was part of a multi-project wafer submitted to TSMC through the Metal Oxide Semiconductor Implementation Service (MOSIS) [8]. The chip was divided into two parts, one part intended primarily for lifetime studies of devices operated at liquid argon temperature, and one part intended for radiation tolerance testing. Transistors intended for radiation tolerance testing were laid out in groups of similar transistors (for instance, NMOS transistors with channel length L = 60 nm and width W from 120 nm to 1000 nm). Within a group, all transistors share a diode-protected gate pad, and an (unprotected) source/drain pad. The other drain/source of every transistor is connected to its own (unprotected) wire bonding pad. We tested PMOS and NMOS core (1.2 V) transistors, and NMOS I/O (2.5 V) transistors (with double thickness gate oxide).

ASIC package, test equipment, and measurement procedures
The test ASICs were wire bonded into (64-pin) pin grid array (PGA) chip carriers so that they could be irradiated on simple printed circuit boards (PCBs) containing only sockets for the ASICs and connectors for bias voltages. Transistor characteristics were measured by mounting one chip carrier at a time on a test board containing switches that allowed individual transistors to be measured independently. The number of pads on the test ASICs was too large to allow all pads to be wire bonded in one package, given the chosen chip carrier, so three different packages with different wire bonding patterns were made. One package had bonds only to devices intended for cold tests. NMOS transistors were wire bonded in the second package, and PMOS transistors were wire bonded in the third package. The devices intended for cold tests are all large transistors unlikely to be used in a pixel readout ASIC. They have been excluded from this analysis.
A different PCB was used to test each ASIC package. A simplified schematic of the PCB used to test NMOS transistors is shown in figure 1. The PCB used to test PMOS transistors was very similar. Two Keithley [10] 237 Source Measurement Units (SMUs) [11] were used, one to bias transistor gates, and one to measure drain-souce current. A Labview [12] program running on a laptop computer was used to sequence and control the measurements. The two SMUs were controlled via General Purpose Interface Bus (GPIB) [13]. Logic on the test PCB was controlled via USB using a National Instruments [14] USB-6501 I/O board [15], connected to the test PCB by a ribbon cable. Bias voltage for the protection diodes was generated by a voltage regulator on the test PCB from the 5 V provided by the laptop USB port. The Labview program controlled solid state switches on the test PCB that connected one of the SMUs to a single gate pad at a time; unused gates were grounded. The program controlled LEDs on the test PCB to indicate how mechanical (rotary) switches on the test PCB should be set to connect the other SMU to a single transistor drain (unused drains were left floating). All three voltage sources were referenced to a common ground plane on the test PCB, and the source pads for all transistors in a package were connected directly to this ground. The fact that we did not separate the return current path for the two SMUs, together 1Our test chip was fabricated at TSMC fab 14; the devices tested earlier at CERN were fabricated at TSMC fab 12 [9]. with possible parasitic circuits involving the protection diodes and the solid state switches in the OFF state, made it impossible for us to accurately measure the leakage current of transistors in the ASIC packages.

Irradiation
The Sandia National Laboratories Gamma Irradiation Facility (GIF) uses 60 Co sources to provide controlled doses of ionizing radiation. 60 Co decays by beta decay to an excited state of 60 Ni. 60 Ni relaxes to the ground state by emitting two gamma rays of energy 1.17 and 1.33 MeV [16]. At the Sandia GIF, 60 Co is held in stainless steel "source pins" that are 3/8 inch diameter and 18 inches long. A number of source pins are mounted in an array and to first order, none of the beta electrons escapes the steel source pins. When not in use, the sources are kept at the bottom of an 18 foot deep pool of deionized water which provides shielding. The facility has three shielded irradiation cells in a single high bay area above the shielding pool. Each irradiation cell has an opening in the floor that allows a source array to be raised out of the water into the cell by an elevator. The cell that was used in these irradiations contained an array of 40 source pins arranged in a straight line. The array contained approximately 225 kCi of 60 Co. Our test ASICs were held inside stainless steel thermos bottles (see figure 2) positioned approximately 2 inches from the face of the source array.2 Cooling was provided by vortex tube coolers [17] mounted in holes drilled through the plastic thermos bottle lids.
2The standard practice for 60 Co irradiation calls for the electrical devices being tested to be shielded with 1.5mm of lead followed by 0.7-1.0 mm of aluminum [20] "in order to minimize dose enhancement effects caused by low-energy scattered radiation." Our setup did not include a lead-aluminum shielding structure.
-3 - Pictures are shown of a thermos bottle assembly, including an irradiation board with four chip carriers, before insertion of the irradiation board into the thermos bottle. In the left photo, the red arrow points to the vortex tube [17] on top of the thermos bottle lid. In the right photo, the red arrow points to an antistatic bag which wraps the irradiation board and (LEMO) low-voltage cable before irradiation. These bags separate the boards and voltage cables from the not-very-dry thermos bottle environment, and provide protection from the metal thermos bottle wall (the test structures are as close to the inner thermos bottle wall as is safe, but not touching). During irradiation, copper pipe was used to deliver air to the vortex tubes.
The dose rate was 1425 rad/second as measured by an ion chamber placed inside one of the thermos bottles.3 The uniformity of the radiation field was checked by irradiating thermoluminescent dosimeters (TLDs) taped to each of the chip carriers on the irradiation PCBs. The TLDs were read at the Radiation Metrology Laboratory at Sandia National Laboratories. The nonuniformity was measured to be less than 6% RMS by comparing the truncated mean (middle two of four) of the four TLDs at each chip carrier position to the average of truncated means, for measurements taken at the start and end of the irradiation. This variation, which we did not correct for because it showed no obvious pattern at the different chip carrier positions, dominates the error on the ion chamber measurement. The TLD measurements also provided a check of the dose rate measured with the ion chamber.
During irradiation, gamma rays interacted in the walls of the thermos bottles and directly heated the inside of the thermos bottles. In order to maintain the temperature of the test devices at less than −20 • C during long irradiations, especially during daytime when the outside temperature was ∼ 35 • C, it was necessary to precool the compressed air input to the vortex tubes and to insulate the copper tubes carrying air to the vortex tubes. Figure 3 shows the temperature of the two thermos bottles during long irradiations. Temperatures were measured using a K-type thermocouple in each thermos bottle, read out and recorded with a Fluke 52 II digital thermometer [18]. The calibration error for K-type thermocouples used near −20 • C is ±2.2 • C [19]. The precooling of the compressed air was improved after the first two long irradiations, during which the temperature in one of the two thermos bottles reached −15 • C. During irradiation the chip carriers were mounted in sockets on irradiation PCBs. Each irradiation PCB held four chip carriers (see figure 2), two for PMOS packages, and one each for NMOS and cold transistor packages. Transistor bias voltages were provided by Keithley 237 SMUs (located outside the shielded irradiation cell) connected to the irradiation PCBs by 20 foot long triax cables. The PMOS transistors were biased in two different ways. In one package, the drains, sources, and gates were held at 1.2 V and the substrate was grounded; the other package was biased with all the gates and the substrate grounded, while the drains and sources were held at 1.2 V. The gates of both the core NMOS and the I/O NMOS were biased at 1.2 V; all other nodes were grounded. Twelve irradiations were performed over 15 days, as shown in table 1. After each irradiation step, a single characteristic curve was recorded for each transistor. All measurements were made at room temperature. The drain-source voltage was set to 1.2 V and the drain-source current was measured as the gate-source voltage was swept from 0 to 1.2 V. It took ∼10 minutes to test the transistors in each package. The ASIC packages were kept at −20 • C in a freezer when not being tested or irradiated.
Pre-irradiation measurements of the transistors showed that a small number of transistors were broken either in fabrication or in the wire bonding process. Approximately half of the transistors that were irradiated failed during the 15 days at Sandia. One group of 12 NMOS transistors was broken mechanically by mishandling. Most of the other transistors that failed also did so in groups, but without an obvious cause. We replaced the package containing the group of 12 failed NMOS transistors partway through the irradiation. The replacement package received a total dose of 878 Mrad. Tables 2 and 3 list all of the transistors included in this study and note which transistors failed and when the failures occurred. Broken transistors were easily identified. For many, the -5 - The most likely cause of transistor failures is electrostatic discharge (ESD). We took a number of steps to reduce the probability of ESD, but our procedures had some deficiencies. The chip carrier packages were transported in an antistatic box and when a package was mounted on, or removed from a PCB, the work was done on a grounded antistatic mat by a person wearing a wrist grounding strap. The PCB was grounded before a chip carrier was inserted into or removed from a socket, but no ESD precautions were taken when the irradiation PCBs were inserted into the thermos bottles or when bias cables were connected. All transistor gate pads were diode protected on-chip, but none of the source or drain pads was ESD protected. Moreover, bias for the on-chip protection diodes was provided through only one pin of the PGA chip carriers. If this pin failed to make contact before other pins while a package was being inserted into a socket, the protection diodes may not have been biased when they were needed most.
After the irradiations, the devices were kept at −20 • C in a freezer that could be powered either by 120 V or by 12 V and transported to Fermilab. Once at Fermilab the transistors were removed from the freezer and kept at room temperature for one week. Multiple measurements were taken during this time. Then the transistors were held in an oven at 100 • C for another week and a final set of measurements was made. This annealing schedule can be seen in table 4. The transistors were not biased during transport or annealing.

Analysis and results
Two quantities were extracted from each transistor characteristic: the maximum drain-source current and the (saturation) threshold voltage V th . The quadratic extrapolation method was used to determine the threshold voltage [21]. As shown in figure 4, V th is defined to be the voltage at which a line -6 - dV gs intercepts the I ds = 0 axis. We determined the slope of the curve by fitting it with a fifth order polynomial and differentiating the fit function. In figure 4, the red squares were computed using finite differences V gs (N +1)−V gs (N ) ; the black line is the result of differentiating the fit to the curve √ |I ds | vs V gs .
-7 -     PMOS decreased by more than a factor of two. The maximum drain-source current of core NMOS transistors also decreased, but only by ∼ 5-10%. No significant threshold shift was observed for any of the core transistors, but the threshold voltage of NMOS I/O transistors increased by 100-200 mV. No error bars are included in the figures because the uncertainty in the SMU measurements is smaller than the symbols used to plot the measurements.
No significant difference was observed between the radiation-induced changes of PMOS transistors biased during the irradiation with the gate in the ON state and PMOS transistors biased with the gate in the OFF state. This is illustrated in figure 6. Figure 7 demonstrates the annealing effects observed in our data. Both the PMOS core transistors and the NMOS I/O transistors recovered significantly during the annealing period. Figures 8 and 9 show the evolution of the maximum drain-source current for a representative selection of PMOS and NMOS core transistors during irradiation and annealing. We did not observe any significant differences in the effect of radiation on the various different types of NMOS transistors tested (normal layout, enclosed layout, triple well, and zero V th ). Figure 10 shows the threshold shift of a representative selection of NMOS I/O transistors during irradiation and annealing.

Summary
Previous measurements have established 65 nm CMOS as the leading candidate technology for HL-LHC electronics. After an exposure of 200 Mrad, Bonacini, et al. reported [2], with one exception, only minor changes in transistor parameters. The exception was a significant loss of maximum drain-source current by narrow PMOS core transistors. They reported a 50% reduction in maximum drive current for a 120/60 PMOS core transistor and a 35% loss for a 360/60 PMOS core transistor. This irradiation of "cold" 65 nm CMOS transistors was motivated by a concern that damage to pixel vertex detector readout electronics operated at −20 • C might be greater than observed in room temperature irradiations. Our measurements show the same pattern of effects as observed previously, but the damage is less severe than was observed at room temperature, rather than more severe. The graph on the right shows the recovery of maximum drain-source current for the same 4 transistors during and after annealing. As in figure 6, lines are included to make the plots easier to read. Once again, lines are not drawn through the points corresponding to measurements made after 754 Mrad of transistors in IC5. The measurements shown for the 5000/5000 transistor are for the transistor in IC7. For this transistor, no point is included corresponding to an integrated dose of 641 Mrad; we believe that the rotary switch was not set correctly during the measurement of this transistor characteristic since the recorded drain-source current was very small for all values of the gate bias.  The graph on the left shows the loss in maximum drain-source current after each irradiation step for 9 NMOS core transistors. The graph on the right shows the change in maximum drain-source current for the same 9 transistors during and after annealing.