The CLIC Vertex Detector

The precision physics needs at TeV-scale linear electron-positron colliders (ILC and CLIC) require a vertex-detector system with excellent flavour-tagging capabilities through a measurement of displaced vertices. This is essential, for example, for an explicit measurement of the Higgs decays to pairs of b-quarks, c-quarks and gluons. Efficient identification of top quarks in the decay t → Wb will give access to the ttH-coupling measurement. In addition to those requirements driven by physics arguments, the CLIC bunch structure calls for hit timing at the few-ns level. As a result, the CLIC vertex-detector system needs to have excellent spatial resolution, full geometrical coverage extending to low polar angles, extremely low material budget, low occupancy facilitated by time-tagging, and sufficient heat removal from sensors and readout. These considerations challenge current technological limits. A detector concept based on hybrid pixel-detector technology is under development for the CLIC vertex detector. It comprises fast, low-power and small-pitch readout ASICs implemented in 65 nm CMOS technology (CLICpix) coupled to ultra-thin planar or active HV-CMOS sensors via low-mass interconnects. The power dissipation of the readout chips is reduced by means of power pulsing, allowing for a cooling system based on forced gas flow. This contribution reviews the requirements and design optimisation for the CLIC vertex detector and gives an overview of recent R&D achievements in the domains of sensors, readout and detector integration.


Introduction
The proposed ILC and CLIC concepts [1][2][3][4] for linear colliders with centre-of-mass energies from a few hundred GeV up to 3 TeV and with luminosities of a few 10 34 cm −2 s −1 both have a large physics potential, complementing and extending the measurements of the current LHC experiments. They will allow for precision measurements of Standard Model physics (e.g. Higgs, top) and of new physics potentially discovered at the 14 TeV LHC (e.g. SUSY). Moreover, direct and indirect searches for new physics over a large range of mass scales will be performed. In the case of CLIC the higher energy of up to 3 TeV comes at the price of high rates of beam-induced backgrounds overlapping with the physics events within the bunch trains of only 156 ns duration [5]. Time stamping of hits on the few ns level is therefore required for most sub-detectors at CLIC, in order to separate physics events from beam-induced backgrounds. The demands for precision physics, in combination with the challenging experimental conditions at CLIC, have inspired a broad detector R&D program. In particular, the vertex-detector system has to fulfil unprecedented requirements in terms of material budget and spatial resolution in a location close to the interaction point, where the rates of beam-induced background particles are highest. The ongoing CLIC vertex-detector studies focus on ultra-thin hybrid pixel detectors and aim for integrated solutions taking into account constraints from mechanics, power delivery and cooling.

JINST 10 C03025
2 Vertex-detector requirements The primary purpose of the CLIC vertex detector is to allow for efficient tagging of heavy quarks through a precise determination of displaced vertices. Monte Carlo simulations show that these goals can be met with a high-momentum term in the transverse impact-parameter resolution of a ≈ 5µm and a multiple-scattering term of b ≈ 15µm, using the canonical parametrisation where p is the momentum of the particle and θ is the polar angle with respect to the beam axis. These requirements can be met with multi-layer barrel and endcap pixel detectors with an inner radius of approximately 30 mm, operating in a magnetic field of 4-5 T and using sensors with a single-point resolution of ≈ 3µm and a material budget of ≈ 0.2% of a radiation length (X 0 ) for the beam-pipe and for each of the detection layers.
Beam-induced backgrounds are expected to lead to an occupancy of up to 3% per bunch train in the innermost layers [5]. Time slicing of hits with an accuracy of ≈ 10 ns will be required to separate such backgrounds from physics events.
The radiation exposure of the vertex-detector is expected to be moderate, compared to the present LHC pixel detectors. For the inner-detector layers a total 1-MeV neutron-equivalent fluence of less than 10 11 n eq /cm 2 /y and a total ionising dose of less than 1kGy are expected [5].
The R&D aims at achieving the single-point resolution target with pixels of ≈ 25µm × 25µm and analog readout. The material-budget target corresponds to a thickness equivalent to less than 200 µm of silicon, shared by the active material, the readout, the support and the cooling infrastructure. This implies that no active cooling elements can be placed inside the vertex detector. Instead, cooling through forced air-flow is foreseen, limiting the maximum power dissipation of the readout to ≈ 50 mW/cm 2 . Such low power consumption can be achieved by means of power pulsing, i.e. turning off most components on the readout chips during the 20 ms gaps between bunch trains.

Flavour-tagging performance
In the following we give examples showing the importance of achieving an excellent flavourtagging performance with the CLIC vertex-detector system. All studies have been performed based on simulation models fulfilling the requirements outlined in the previous section and using the multi-variate flavour-tagging package LCFIPlus [6].

Measurement of the top Yukawa coupling
Linear electron-positron colliders allow for a direct measurement of the top Yukawa coupling through the process e + e − → ttH. A full-simulation study for CLIC with an energy of √ s = 1.4 TeV, an integrated luminosity of 1.5 ab −1 and assuming unpolarised beams has been performed [7], following a similar study for ILC at 1 TeV [8]. It includes physics background events as well as pile-up overlay from γγ →hadrons. The Higgs boson is reconstructed in the H → bb decay mode and the top quarks through the decay t → W b, with subsequent fully hadronic or semi-leptonic The LCFIPlus flavor-tagging package assigns each jet with a band c-probability. Figure 1(a) shows the distribution of the third-highest b-tag in each event for signal and background simulation samples in the analysis that includes the semi-leptonic W -decay channels. A clear distinction between signal and background is observed with this variable, which is an important input to the multi-variate final event selection based on a boosted-decision-tree (BDT) classifier ( figure 1(b)). The statistical uncertainty on the cross-section measurement of the ttH process achieved in this analysis is 12.0% (10.9%) in the semi-leptonic (fully hadronic) decay channels, resulting in a combined uncertainty of 8.1%. The resulting uncertainty on the ttH coupling g ttH is 4.3% for the combination of all considered decay channels. The systematic uncertainties are expected to be negligible. The achievable precision on the determination of the couplings at the LHC, for comparison, is approximately 7-10%, assuming a dataset of 3 ab −1 collected at an energy of 14 TeV [9].

Impact of detector geometry on flavour-tagging
Design optimisation studies for the vertex detector were performed using simulated full-detector band c-tagging performance results as benchmarks and considering constraints from mechanical engineering and cooling-system studies [10]. The flavour-tagging performance was assessed for jets at various energies and directions. Figure 2(a) shows one of the simulated layouts with a spiral arrangement of the end-cap detectors, allowing for air-flow into and out of the barrel region. The obtained performance for this geometry is similar to the one for the corresponding disk geometry, except for the barrel-endcap transition region, where the spiral layout leads to a reduction in the number of layers for a small azimuth-angle range. (figure 2(b)).
The comparison between a geometry with 5 single detection layers and one with 3 double layers with common support results in similar overall performance for jet energies above 100 GeV. For jet energies below 100 GeV the double-layer geometry shows a small improvement, due to the reduced amount of material for the supports ( figure 3(a)).
A significant degradation in performance is observed after doubling the amount of material per layer from the reference simulation value of 0.1%X 0 to the design target of 0.2%X 0 , as shown in figure 3(b) for the case of c-tagging. The background-rejection of the geometry with doubled material budget is approximately 5-35% worse, depending on the type of background and the analysis-dependent required signal efficiency.

Impact of flavour-tagging on physics performance
The impact of a decrease in flavour-tagging performance on the physics-analysis results was estimated for the example of Higgs production in the vector-boson fusion process with subsequent decay of the Higgs to pairs of band c-quarks: e + e − → Hνν, H → bb, cc. This analysis was performed for an energy of 3 TeV and an integrated luminosity of 2 ab −1 . Typical jet energies are of the order of 130 GeV. The analysis results obtained with nominal flavour-tagging parameters were scaled following a change in fake rates of ±20%, corresponding approximately to a change of the amount of material in the vertex-detector region by a factor of two (see previous sub-section). The resulting change in statistical precision for the cross-section determination amounts to ±6 − 7% (±15%) for the H → bb (H → cc) decay channels. Approximately 30% more integrated luminosity would be required to compensate for a loss in statistical precision by 15%, corresponding to approximately 1 year of additional running at the highest energy.

Hybrid detector-readout technology
In order to meet the vertex-detector requirements discussed in section 2, hybrid-pixel-detector systems are under study, combining fast charge collection through drift in high-field sensors with high-performance readout ASICs. The target thickness for both the sensor and readout layers is only 50 µm each.

Thin-sensor assemblies
Planar pixel sensors with 55µm pitch and different thicknesses (50-300 µm) were procured from different vendors and bump-bonded to Timepix [11] readout ASICs (100 and 700 µm thickness). Slim-edge sensor designs (250-450 µm, two guard rings) are compared to designs with active edges (20-50 µm, one guard ring above the edge pixels). Preliminary beam-test results show very good efficiencies in both cases, extending beyond the edge pixels [12]. For 50 µm sensor thickness and nominal readout parameters, the fraction of multi-pixel clusters is approximately 20%. Singlepoint resolutions of approximately 3 µm have been extracted for clusters of two pixels using charge interpolation and taking into account non-linear charge sharing.

CLICpix readout chip
The CLICpix hybrid readout chip [13] will be implemented in a 65 nm CMOS process. A CLICpix demonstrator chip has been produced in 65 nm CMOS technology, including a 64 × 64 pixel matrix and power-pulsing capability. The pixel size is 25 µm×25 µm. 800 µs (for 10% occupancy), using a 320 MHz readout clock and zero suppression. The power consumption of the chip is dominated by the analog frontend with a peak power corresponding to 2 W/cm 2 . The total average power consumption can be reduced to a value below the target of 50 mW/cm 2 by means of power gating for the analog part and clock gating for the digital part.
Readout tests have confirmed that the CLICpix demonstrator chip is fully functional and the power consumption and performance are in agreement with simulations [14].

Active sensors with capacitive coupling
The first hybrid assemblies of CLICpix prototype chips with CCPDv3 active sensors have been produced and tested. The sensors are implemented in a 130 nm high-voltage CMOS process [15]. A deep n-well above the p substrate surrounds low-voltage p-wells and acts as the signal collecting electrode. A nominal operation voltage of -60 V at the n-well results in a depletion layer of approximately 10 µm. The fast drift signal collected in this depletion layer passes through a two-stage transimpedance amplifier in each pixel and the resulting voltage signal is capacitively coupled to the CLICpix ASIC through a layer of glue a few microns thick ( figure 4(a)).
Laboratory tests with radioactive sources show a good signal-to-noise performance for the active sensor output ( figure 4(b)). Preliminary test-beam results with CLICpix-CCPDv3 assemblies suggest a detection efficiency of > 99% for minimum ionising particles and a high fraction of single-pixel clusters with a position resolution of approximately 7 µm, as expected for 25 µm pixel pitch.

Through-Silicon Via (TSV) technology
Through-Silicon Via (TSV) vertical interconnects remove the need for wire bonding connections on the side of the readout ASICs and therefore allow for an efficient tiling to form larger modules with minimal inactive areas.
A "via last" TSV process developed in collaboration with CEA-LETI has demonstrated the feasibility of TSVs on functional detector chips from the Medipix/Timepix chip family [16]. The project uses Medipix3 readout wafers produced in 130 nm CMOS technology. A "via last" process is used that includes thinning of the ASIC wafers to 120 µm and results in vias of 60 µm diameter.
-6 -Tests on the processed wafers show good results, with a low resistivity of the vias (< 1 Ω) and a sufficient isolation to the outside (leakage current < 1 µA at 1 V). Preliminary functional tests on a sub-sample of the chips before and after TSV processing indicate no significant deterioration of the performance.
A continuation of the TSV project with CEA-LETI aims to produce TSV assemblies with Timepix3 ASIC wafers thinned to 50 µm.

Detector integration
The detector performance requirements lead to challenging constraints for the mechanical and electrical integration of the vertex-detector components and its cooling system. An integrated approach is followed, addressing several of the critical R&D issues in these domains: • Power delivery and power pulsing. A low-mass power-pulsing and power-delivery system optimised for the small duty cycle of the CLIC machine has been developed [17]. Controlled current sources deliver a low and almost constant current (< 300 mA per ladder) into the vertex region through low-mass cables. The energy needed by the readout ASICs during the time of the collisions and detector readout is stored locally in silicon capacitors. Lowdropout regulators provide the necessary stability of the output voltage for the analog (∆V ≈ 16mV) and the digital part (∆V ≈ 70mV) of the readout ASICs. Prototypes have been tested successfully with dummy loads emulating the power consumption of the 12 readout ASICs in a half ladder. The total contribution of the powering infrastructure to the material budget of each barrel layer is approximately 0.1%X 0 . It is expected to decrease to less than 0.05%X 0 with evolving silicon-capacitor technology.
• Cooling. Even with power pulsing a total power of approximately 500 W will be dissipated in the vertex detectors alone. To limit the amount of material in the vertex-detector region, a cooling system based on forced air flow is under development [18]. Finite-element Computational Fluid Dynamics (CFD) simulations show that air cooling is feasible. For a mass flow of 20 g/s, the temperature increase in the vertex detector is limited to approximately 40 o C. The proposed cooling scheme is being validated in thermal mockups. Preliminary results confirm the validity of the simulations. • Assembly and access scenarios. Assembly and access scenarios for in-situ testing have been developed, taking into account the constraints from the surrounding detector elements. Realistic cabling layouts are proposed and evaluated in terms of their impact on the global and local material budget.

Conclusions
The precision physics requirements at CLIC pose challenging demands on the performance of the vertex detector system. Full-simulation flavour-tagging studies have been performed to assess the influence of the detector design on the physics performance and to optimise the proposed detector layouts. A broad hardware R&D program is in place, addressing the challenges for the CLIC vertex detector in an integrated approach.