2 ps Time-to-Digital Converter for Frequency Synthesis in 55 nm CMOS Technology

This paper presents a 2-ps time-to-digital converter (TDC) in 55 nm CMOS technology for all-digital phased-locked loop (ADPLL) system. Innovative inverter delay chain and Vernier delay chain cascade structure is adopted in the TDC to expand the measurement range while ensuring high resolution, so as to meet the wideband application requirements. Time window technology is employed to reduce circuit working frequency to save power by extracting single rising/falling edge of clock signal. Multiplexing technology is exploited to further reduce the power consumption by reusing the rising/falling edge detection delay chain of the first-level TDC, and also the time deviation detection circuit and resolution scaling factor detection circuit of the second-level TDC. The TDC features a differential nonlinearity (DNL) of 0.31 least significant bits (LSB) and an integral nonlinearity (INL) of 0.62 LSB, with a total current consumption of 4 mA from a 1.2 V supply voltage.