130 nm Low Power CMOS Analog Multiplier

Processing analog signal often involves analog multiplier and the multiplier is part of system on chip (SoC). Designing such system with a low power consumption is crucial nowadays. It is very important to increase the system battery lifetime. The design also must be smaller in size. In order to reduce the power consumption of the multiplier, an architecture that require smaller current must be designed and the approach is to use a design that is able to function at a low voltage supply. This project has designed the analog multiplier with a low power consumption using Silterra 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. A four quadrant technique is applied in the design. The scaling of transistor will help in reducing the size of the analog multiplier, and the proposed circuit architecture has produced a compact multiplier. Cadence electronic design automation (EDA) Tools is used to design the circuit. The schematic, layout, physical verification and parasitic extraction with post layout simulation are done to verify the multiplier circuit is functioning. The analog multiplier is operated with 1.2 V voltage supply and the power consumption is 98 µW. At 1 V, the power consumption is 32 µW. The total area for the design is 99 µm².


Introduction
Analog circuit deals with continuous time signal that are used to generate, detect, measure, amplify, attenuate or filter signal.In analog circuits such as in adaptive filters, frequency doublers, and modulators [1], [2], analog multiplier plays an important part in it.It is used extensively in the field of telecommunication, control, instrumentation, measurement, and signal processing [3].The output of analog multiplier, v, is a linear product of two continuous input signals v 1 and v 2 .Therefore v = k v 1 v 2 where k is a multiplication constant or gain of suitable dimension [4].Figure 1 shows the basic idea of an analog multiplier.

Figure 1.
Basic idea of multiplier [5] In portable applications, analog multiplier has to operate with a low voltage to improve power efficiency [6].Hence, analog multiplier must be designed in the low voltage environment too.

Analog Multiplier
An analog multiplier had been designed in [7], and the design is claimed to be very compact.However, the circuit has an extra voltage reference terminal connected between the resistive loads.The extra voltage reference makes the circuit consumed more power and the circuit complexity is high [8].Thus the analog multiplier circuit cannot be called compact.In [9], a fully differential four quadrant multiplier was designed with supply voltages of ± 1 V.The circuit consumed 0.326 mW of static power and was designed in 0.25 μm CMOS technology.A proper biasing is needed in this circuit in order to produce a correct output.A 180 nm analog multiplier is designed in [10] with a power consumption of 0.43 mW.The circuit works well with ± 0.8 V supplies but the power consumed is considered high.Another 180 nm analog multiplier is designed in [11] at the supply voltage of 1 V.The power consumed by the circuit is very low which is 1.2 μW, but the circuit has to work in weak inversion region.Hence a proper biasing is critical in this circuit.As for the multiplier circuit in [12], the technology is 130 nm and with a supply of 1 V, the power consumed is 25.14 mW.
The analog multiplier in this paper is designed to eliminate extra voltage reference in order to produce a compact circuit.With the help of current CMOS technology which has been scaled down over the years, a smaller transistor size of 130 nm is used which will yield higher device density, higher speed and reduced power consumption.For the operating supply of the circuit, a 1.2 V or 1 V can be applied.Cadence EDA Tools is used to design and simulate the analog multiplier in this project.
Figure 2 illustrates the proposed circuit of the analog multiplier that is designed in this project.The proposed analog multiplier comprises of a pair of common source amplifier with input transistors m1 and m2.This will give output currents in terms of squaring functions of input voltages (V1 and V2).A suitable value of resistance for resistors R in the circuit has been determined to ensure all the transistors in the circuit are working in the proper region.The basis for the circuit is a four quadrant multiplier circuit as mentioned in [1], [8], [13] and [14].

The Designed Circuit
Figure 3 shows the schematic circuit of the analog multiplier designed using Cadence software in 130 nm CMOS technology.The circuit contains 10 transistors consist of 8 PMOSs and 2 NMOSs.The circuit also includes 2 resistors, R1 and R2 with the value of 2.5 kΩ.Transistor m1 and m2 are the input transistors for the input voltage V1 and V2 respectively.These two transistors give output currents in terms of square functions of the two input [8].Transistors m3-m10, serve as a square root circuit which act as non-linear cancellation path.The output currents of the input transistors are directed into the square root block to produce a differential output current of the overall circuit and resulting in a multiplication function of two input signal V12 and V34.Table 1 shows the transistor dimension used to design the analog multiplier.

Result and Discussion
The analog multiplier circuit in Figure 3 was designed and simulated using Cadence with 130 nm CMOS technology with two different supply voltages of 1.2 V and 1 V.The amplitude of V1 and V2 are varied with its sinusoidal carrier signal frequency of 25 kHz multiplied with V3 and V4 which are also varied with sinusoidal modulating signal frequency of 1 kHz.Figure 4 shows the simulated circuit with its input amplitude and frequency.

Transient Analysis
This analysis includes time versus voltage.The differential input voltage V12 is defined as V1-V2 while the differential control voltage V34 is equal to V3-V4.The output for this circuit is the product of the carrier signal V12 (Figure 5 (a)) with the modulating signal V34 (Figure 5 (b)) and the produced waveform is shown in Figure 5(c).The result obtained in Figure 5(c) is from Vout = V O1 -V O2 .The result is correct and according to the theory.The result obtained is similar to the result in [8] and [14], thus proved the analog multiplier circuit has been successfully designed.The circuit is also simulated with different voltage supplies to investigate the maximum and minimum input voltages that can be applied to the circuit.The simulation result listed in Table 2 are for 1.2 V and 1 V.It is found that with 1.2 V voltage supply, a higher amplitude of input signal can be applied.The power consumption of the proposed analog multiplier at 1.2 V is 98 µW while at 1 V the power consumption is 32 µW.A 1 V power supply consumed less power but the range of the input signal is lower.A supply voltage of lower than 1 V cannot be applied to the circuit because the output waveform is incorrect.A higher voltage than 1.2 V can be applied but the power consumed will be higher too.Nevertheless, the proposed analog multiplier has been shown to consume less power as compared to the design in [9], [10] and [12].6 show the layout for the proposed design.Transistors M9 and M10 occupied more area as compared to other transistors in the circuit.The total physical area for the analog multiplier is 99 µm².The area taken is smaller if compared to the circuit in [7] and [8].This result is expected since these circuits were designed using a bigger CMOS technology.

Conclusion
An analog multiplier circuit has been constructed using 130 nm CMOS technology with an area of 99 µm², the circuit is more compact than previous work.A smaller transistor size had been used in this design.The circuit can be used with a voltage supply of 1 to 1.2 V with a power consumption of between 32 to 98 µW.The circuit has been simulated and performed well as an analog multiplier.

Figure 2 .
Figure 2. The proposed analog multiplier circuit

Figure 3 .
Figure 3.The schematic circuit of analog multiplier

Figure 6 .
Figure 6.Layout design of the multiplier LVS physical verification is vital tool to verify the connectivity comparisons between the layout and schematic.The result from the LVS test done on the multiplier circuit has shown the schematic and layout are equivalent.

Table 2 .
Comparison of different voltage supply 4.2 Design Rule Check (DRC) and Layout Versus Schematic (LVS) TestDRC is a step imposed on the layout.It verifies the physical layout to ensure that none of the design rule is violated.Figure