Multilayer ion trap technology for scalable quantum computing and quantum simulation

We present a novel ion trap fabrication method enabling the realization of multilayer ion traps scalable to an in principle arbitrary number of metal-dielectric levels. We benchmark our method by fabricating a multilayer ion trap with integrated three-dimensional microwave circuitry. We demonstrate ion trapping and microwave control of the hyperfine states of a laser cooled $\,^{9}$Be$^{+}$ ion held at a distance of 35$\,\mu$m above the trap surface. This method can be used to implement large-scale ion trap arrays for scalable quantum information processing and quantum simulation.


Introduction
Trapped ions are not only one of the most promising platforms for the practical implementation of quantum computing and quantum simulations, but also sensitive systems for measuring very small magnetic and electric fields. Typically, they are held in Paul or Penning traps at high vacuum, laser cooled close to absolute zero temperature, and their internal states coupled to their motion can be manipulated with high fidelity by either laser fields [1,2] or microwave radiation [3,4]. However, scaling these elementary demonstrations to larger systems remains a formidable technological challenge [5].
Surface-electrode ion traps [6] represent a strong candidate for the realization of a quantum charge-coupled device (QCCD) [7,8] for scaling quantum logic operations. Such an ion trap array could feature dedicated zones for storing, manipulation and read-out, thus promising a modular hardware for quantum computation and quantum simulation [9]. Conventionally, in surface-electrode ion traps all electrodes are built in a single plane by standard microfabrication techniques [10]. First integration of key scalable elements into a single layer chip such as micro-optical components [11], nanophotonic waveguide devices [12] or microwave conductors [13] have been demonstrated. However, interconnecting separated components built in this system imposes new challenges on trap design where signal lines have to be routed around other elements. Therefore, the realization of a highly integrated large-scale ion trap device requires a more flexible approach where signal routings can be distributed on vertically well-separated levels of interconnects.
Demonstrations of multilayer processes in ion traps so far are based on techniques borrowed from MicroElectroMechanical Systems (MEMS) [14,15] or CMOS [16,17]; however the resulting trap structures are limited to thin interconnect levels. Moreover, there is a need of a nearly material-independent processing capable of including most dielectric substrates and thick metallization. Any fabrication process will have to comply with the specific requirements of an ion trap, such as a material mix which features extremely low material outgassing and needs to be compatible with ultra-high vacuum (UHV) operation, low dielectric losses and non-magnetic metal surfaces. Often one is concerned about shielding the ion(s) from patch potentials due to exposed dielectrics. Specially, for the top-level the electrode interspacings should have at least a width equal to its height [18], or in other words electrode gaps of an aspect ratio higher than 1:1.
Here we present a robust fabrication method, scalable to an in principle arbitrary number of planarized thick metal-dielectric layers, enabling the realization of scalable ion trap devices. The method complies with the stringent requirements of a scalable ion trapping array, allowing the fabrication of complex trap designs using relatively forgiving fabrication techniques on nearly any type of substrate. To demonstrate the approach, we fabricate and operate a multilayer ion trap chip with three-dimensional (3-D) microwave circuitry towards the realization of high fidelity muli-qubit gates [13,19].

Fabrication Methods
Methods for building surface-electrode ion traps [6] or atom chips [20,21] are typically based on standard semiconductor processing. For the simplest case, in which all metal electrodes are aligned in a single plane, a generic fabrication workflow consists of a three-step processing: wafer patterning, electrode formation and electric insulation. Depending on the requirements one will choose between different materials and processing methods at hand. In what follows we will describe our own fabrication methods to build single layer and multilayer microfabricated ion traps.

Single Level Processing (SLP) Method
For the Single Level Processing (SLP) method all steps are carried out on 3-inchdiameter wafers in a fabrication line located at Physikalisch-Technische Bundesanstalt (PTB), Braunschweig. We have fabricated similar structures to the ones presented in Fig. 1 on AlN, sapphire, organic polymers and high resistivity (HiR) float zone (FZ) Si wafers, demonstrating the compatibility of the method with a wide range of substrates suitable for ion trap technology. The first step during wafer preparation involves the deposition of a Ti adhesion layer (15 nm thin) and an Au seed layer (50 nm thin) on top of the substrate by resistive evaporation. The first film acts as an adhesion promoter between the substrate and the Au seed layer, and the second film serves as a starting conductive layer for a later electrodeposition step.
Second, to define the trap geometry, a 25-µm-thick positive or 16-µm-thick negative resist is spin coated on top of the Au seed layer and the wafer is exposed to UV light by contact lithography. A subsequent development of the exposed resist results in open areas on the substrate which are filled to a desired thickness by electrodeposition of Au in a sulphite-based bath.
Finally, after gold electroplating the resist mask is removed chemically and the wafer is cleaned under oxygen-based plasma etching. Additionally, the wafer is exposed to a fluorine-based plasma to further remove possible resist debris. Immediately afterwards the seed Au layer is removed via Ar etching and the Ti layer removed by a fluorine-based plasma etching.
This method allows the fabrication of gold structures with high aspect ratios as exemplified in Fig 1. Gold structures with a width as narrow as 5 µm and gap separation as narrow as 2 µm are shown in Fig. 1(a). Another example is depicted in Fig. 1(b) consisting of a pair of gold electrodes separated by a gap with an aspect ratio of 14:1. One additional advantage of the method is that after dry etching of the Au/Ti bilayer the resulting trap surfaces have a superior finishing quality compared to the commonly used wet etching.

Multilevel Processing (MLP) Method
In this section a Multilevel Processing (MLP) method is presented, which combines techniques borrowed from MicroElectroMechanical Systems (MEMS) and Integrated Circuits (IC) processing. The method is also compatible with other common substrates used for ion trap technology such as silicon, sapphire, borosilicate glass and quartz.
To demonstrate the simplicity and robustness of our method we have fabricated an ion trap with integrated (3-D) three-dimensional microwave circuitry. It comprises a lower interconnect level L 1 and an upper electrode level L 2 . An additional vertical interconnect access V 1 , called via, allows microwave signals to be transmitted between levels. A more detailed description of the microwave and quantum logic aspects of the trap design and the corresponding characterization will be covered elsewhere [22].
The method presented here mainly consists of six processing steps: (a) wafer preparation, (b) metallization of lower level L 1 , (c) metallization of via V 1 , (d) removal of seed layer, (e) deposition and planarization of dielectric layer D 1 and (f) metallization of upper level L 2 . A schematics of the fabrication flow is given in Fig. 2.
The supporting material is a 3-inch silicon wafer with high resistivity (σ > 1 × 10 4 Ω cm). On top of it and as shown in Fig. 2(a), a 2-µm-thick film of Si 3 N 4 is deposited by physical enhanced chemical vapor deposition (PECVD). This dielectric film may improve trap operation by avoiding detrimental diffussion of Au into silicon and increasing the flashover voltage as demonstrated in Ref. [23]. Thereafter, a 10nm-thin layer of Ti and a 50-nm-thin layer of Au are thermally evaporated on top of Si 3 N 4 .
To build the lower level L 1 on top of Si 3 N 4 /Si, a negative resist is spin coated and patterned via UV lithography. Once the negative resist is developed to form a resist mold, gold electrodes are grown by electroplating as depicted in Fig. 2(b). After electroplating is completed, the resist mask is stripped and the wafer cleaned under plasma etching.
For the metallization of the via V 1 we repeat the photolithography and electroplating steps presented in (b) but this time on top of L 1 by using a thick (> 12 µm) developed negative resist as a plating mold. Electroplated vias on top of L 1 are depicted in Fig. 2(c) after stripping the negative resist mask and plasma cleaning of the wafer.
To remove the Au seed layer and the Ti adhesion layer we use the last dry etching step from the SLP method. This step allows a controllable etch of Au and Ti of 50 nm min −1 and 10 nm min −1 respectively, resulting in a minimal change of the surface quality on top of both L 1 and V 1 surfaces. The electrically isolated elements on V 1 and L 1 are schematically illustrated in Fig. 2(d).
A dielectric layer is then spin coated on top of L 1 and V 1 and thermally cured (Fig. 2(e)). After thermal curing, excess material is present on top of the underlaying structures in L 1 and V 1 . The imprinted dielectric topography is globally planarized through a chemical-mechanical polishing (CMP) step, which is stopped at the top of V 1 or close to it. To assure electrical contact between V 1 and the subsequent level L 2 a local etch-back process is performed.
To define the top metal layer the SLP method is again employed but this time on top of the planarized polymer surface (Fig. 2(f)). Once the plating has been completed and the resist mold removed, the remaining polymer film between gaps underneath L 2 is etched down to the Si 3 N 4 layer by a fluorine-based plasma to hide possible patch potentials built on the exposed insulator.

Fabrication outcome and trap operation
Here we briefly present the design and characterization of a trap with 3-D microwave conductors integrated into a microfabricated ion trap using the MLP method. The microwave circuitry is embedded to implement quantum logic operations using nearfield microwaves [24,13,25,26]. The specific design is discussed elsewhere in detail [?] and here only described as one of many scenarios that benefits from the multilayer technology.
In the upper level (L 2 ) the trap includes two RF electrodes and ten DC electrodes to confine the ions to a local minimum (x 0 , z 0 ), see Fig. 3(a). A microwave signal (white arrows) of frequency 1 GHz can be applied on a 3-D microwave meander (MWM) conductor between two contact points labeled as "F" and "G", thus generating an oscillating magnetic near-field gradient B in the xz−radial plane with a local minimum at (x 1 , z 1 ). The three apparent independent microwave conductors indicated by the white arrows are indeed part of a single 3-D microwave meander connected to L 1 by vias and routed over L 1 as inidicated in Fig. 3. A central part of a diced trap chip (5 mm×5 mm) fabricated using the MLP method is presented in Fig. 3(a). There are also two additional microwave conductors (MWC) surrounding the central DC electrodes, in which an oscillating current (black arrows) can be applied to produce an oscillating B field.  A cleaved chip revealing a cross-section view of the metal-dielectric stack around position "F" position "G" is shown in Fig. 3(b) and Fig. 3(c)), respectively. The ion trap (RF and DC electrodes) as well as the uppermost part of the MWM conductor are entirely located in L 2 , whereas the microwave signals and the ground plane are routed between L 1 and L 2 through vias in V 1 (not visible in the micrograph but behind D 1 in Fig. 3(b) and (c)).
Removing both Au and Ti films by means of dry etching has improved the trap surface quality. For a similar chip as the one here presented an rms roughness R rms = 8.3(5) nm is obtained by atomic-force microscopy over an area of 25 µm × 25 µm. This represents a two-order of magnitude improvement when compared to a wet etching process using aqua regia [27]. These nearly mirror-like surfaces are relevant since there is a reduction of stray light scattered in the direction perpendicular to the trap surface during resonance fluorescence imaging for ion state detection. Also an ion trap with minimal surface roughness might be less prone to anomalous motional heating at cryogenic temperatures [28]. The diced trap chip is glued onto a copper block and wirebonded to a custom printed circuit board for filtering and signal routing. The whole assembly is installed in a vacuum system at a pressure better than 1 × 10 −11 mbar and connected to an in-vacuum coaxial resonator similar to the one used in Ref. [29]. For ion loading we employ a laser ablation scheme [27] and subsequent two-photon ionization using 235 nm light [30]. Single 9 Be + ions are loaded at 35 µm above the upper surface of L 2 around the position "X" (see Fig. 3(a)).
We supply to the trap an RF drive frequency of Ω RF = 2π × 176.5 MHz with amplitude V RF = 100 V and DC voltages ranging within ±25 V. To determine the trap frequencies we apply an oscillating tickle voltage to one of the DC electrodes and scan the frequency [31]. Once the tickle drive is resonant with a secular frequency, the motion of the ion is excited and the ion fluorescence drops (Fig. 4(a)). We measure secular trap frequencies of (ω y , ω LF , ω HF ) = 2π·(4.02, 5.23, 8.59) MHz, where the high-frequency (HF) and low-frequency (LF) radial modes form an angle of −5.9 • relative to the x-axis and z-axis, respectively.
Finally we employ the integrated microwave conductors to manipulate the internal state of the ion. Fig. 4(b) shows Rabi oscillations on the qubit transition |F = 2, m F = +1 → |F = 1, m F = +1 [27] of the electronic ground state 2 S 1/2 of a single 9 Be + ion at an external magnetic field of |B 0 | = 22.3 mT when applying a microwave current of frequency ω 0 1082.55 MHz to one of the MWC conductors. Here, F is referring to the total angular momentum F and m F the quantum number of its projection on B 0 . The state readout is carried out via ion fluorescence detection on the closed-cycling transition |S 1/2 , F = 2, m F = 2 → |P 3/2 , m J = +3/2, m I = +3/2 , combined with suitable microwave transfer pulses [27].

Conclusion and Outlook
We have presented a novel multilayer method for fabricating scalable surface-electrode ion traps. The flexibility and robustness of the method allows to benchmark the integration of 3-D microwave circuitry into a multilayer ion trap. Furthermore, we have demonstrated successful trapping of 9 Be + and basic qubit manipulation by applying microwave oscillating currents on one of the conductors.
The MLP method presented here can in principle be extended to a nearly arbitrary number of layers to comply with the stringent needs of scaling surface-electrode ion traps. Moreover, the method permits the integration of three-dimensional and planarized features with high aspect ratio. This technique opens new routes towards the realization of more complex and powerful ion trap devices. In contrast to a typical CMOS situation where the "device" is fabricated on top of the substrate, with interconnect layers on top of the device, in our case the "device" is the top electrode layer which is controlling the ion(s), whereas the layers closer to the substrate are used as interconnects. In the future, these lower interconnects may be combined with through-wafer vias to achieve contacting of the ion trap chip from the backside, eliminating the need of wirebonds and likely obstruction of laser beams. Through-wafer slots for back-side ion loading can also be produced in the same way. These same techniques could be applied to realize so-called analog quantum simulators in ion trap arrays [32,33,34], possibly with integrated control [35]. Moreover, such an approach may enable the embedding of complex integrated components such as trench capacitors [36,37], low-loss integrated waveguides [38]; or the realization of more elaborate devices including reliable ion-transport junctions [39,40], increased optical access [17] or manipulation of scalable arrays of two-dimensional trapped ion systems [33,34].
The MLP method can also be used to extend multilayer "atom chips" [21,41,42] or to fabricate scalable hybrid atom-ion traps [43,44] for quantum many-body physics experiments and quantum sensing with neutral atoms. In this context the thick metal conductors can support substantial currents required for magnetic trapping and the planarization together with the demonstrated minimized surface roughness allows the implementation of mirror-like surfaces and transfer coatings for integrated magneto-