Cryogenic silicon surface ion trap

Trapped ions are pre-eminent candidates for building quantum information processors and quantum simulators. They have been used to demonstrate quantum gates and algorithms, quantum error correction, and basic quantum simulations. However, to realise the full potential of such systems and make scalable trapped-ion quantum computing a reality, there exist a number of practical problems which must be solved. These include tackling the observed high ion-heating rates and creating scalable trap structures which can be simply and reliably produced. Here, we report on cryogenically operated silicon ion traps which can be rapidly and easily fabricated using standard semiconductor technologies. Single $^{40}$Ca$^+$ ions have been trapped and used to characterize the trap operation. Long ion lifetimes were observed with the traps exhibiting heating rates as low as $\dot{\bar{n}}=$ 0.33 phonons/s at an ion-electrode distance of 230 $\mu$m. These results open many new avenues to arrays of micro-fabricated ion traps.


Introduction
Processing information using a quantum system allows problems to be solved which are difficult or impossible to compute classically [1], and trapped atomic ions provide a promising platform for such quantum information processors [2,3,4]. Ions can be confined using a combination of radio-frequency (RF) and static (DC) electric fields [5]. The electrode structures required to create the appropriate fields can take a variety of geometries, and great progress has recently been made using planar structures [6,7]. For these, all electrodes are located in a plane above which the ions are trapped. Notable among the advantages of such a structure is the scalability: arrays with hundreds or thousands of traps can in principle be built on a single chip using very-large-scale integration (VLSI) technologies like optical lithography and etching [8], far exceeding what is possible using bulk fabrication.
In making such traps a reality, a number of features must be considered. It is essential that scalable trap architectures have low RF losses: if the losses are too high the RF voltage applied in order to trap will be dissipated in the chip. Beyond this, microfabrication has become highly developed and it would be desirable to bring these techniques to bear on ion traps. For large arrays of traps the creation of throughwafer vias [9], so that electrical connections can be made throughout the array, is a prerequisite. Optical addressing of ions in an array can be facilitated by fabrication of holes through the substrate. Moreover, the integration of on-chip electronics, such as would be afforded by CMOS (Complementary Metal-Oxide-Semiconductors), would open up untold possibilities for ion traps.
Surface ion traps can be broadly divided into two groups, according to the type of substrate material: dielectric or semiconductor. Dielectric substrates like sapphire or fused silica have a very low RF power dissipation. For such traps the electrodes are created by simple optical lithography combined with lift-off processes or electroplating on top of the substrate [10]. However, dielectric materials are difficult to pattern by means of wet or dry etching and not suitable for features such as through-wafer vias. The second type of substrate materials are semiconductors, such as silicon, which are easy to structure. Slots, holes and vias with aspect ratios up to 160 can be etched by standard techniques [11]. However, the RF power dissipation is significant and therefore a ground electrode is required to shield the substrate from RF fields. This in turn necessitates a more complicated fabrication process and precludes vias for RF electrodes [12,13].
In this paper, we report on a new silicon surface ion trap built for cryogenic applications. The design permits the use of standard silicon processing techniques, while mitigating the problems of RF loss: silicon becomes an insulator at low temperature and consequently the RF loss decreases by several orders of magnitude [14]. This obviates the need for a shielding electrode and so simplifies the trap design. The cryogenic environment inheres several additional advantages. Ultra-high vacuum can be attained within a few hours due to cryogenic pumping, without baking the system [15]. This facilitates fast turn-around times for trap installation (∼1 day). Furthermore, operation at liquid-helium temperatures reduces the rate at which the ions' motion is heated, typically by around two orders of magnitude [16]. This is beneficial as it increases the coherence time of the ions' motion, which is used to transfer quantum information between different ions.

Trap design and fabrication
The planar design used for this work is illustrated in figure 1. To fabricate the traps an undoped silicon substrate is patterned by optical lithography and deep reactive ion etching (see figure 2(b)).
Deep undercut trenches are etched in the substrate and mark the gaps between the individual electrodes. Following a thermal growth of 2 µm of SiO 2 the electrodes are formed by evaporation of gold perpendicular to the surface. Due to the undercuts, there is no electrical connection between the different electrodes (figure 1(b), 2(b)) and no further lift-off or etching steps are necessary. There are no further cleaning steps and, to avoid any contamination of the surface, the gold electrodes are never brought into contact with liquids such as solvents for cleaning. The fabrication process and the packaging are explained in detail in Appendix A.1.
Ions are trapped 230 µm above the centre electrode by applying an RF voltage to the two RF electrodes. Lasers used to Doppler cool the ions are aligned parallel to the plane of the trap, to minimise scatter from the surface. To efficiently cool the ions along all three principal axes of their motion, each axis must have a projection along the direction of the cooling laser beam. Consequently, none of the principal axes of motion should be perpendicular to the trap surface. The RF electrodes have thus been fabricated with unequal widths ensuring that the two radial principal axes both have a component parallel to the trap surface [17]. Seven segmented electrodes are located on each side of the two RF electrodes. DC voltages are applied to these electrodes and create confinement along the axial (z ) direction. Ions can be shuttled along the z -axis by changing the DC voltages. Stray electric fields arising from contamination of the trap or imperfection in trap fabrication can cause micromotion [18], which is minimised by adding suitable DC voltages to the segmented DC electrodes.
Initially, the operation of a single trap (trap #1) was characterised in detail over several weeks. To demonstrate the reproducibility of the results, a further five traps from two different silicon wafers were tested, and shown to exhibit similar behaviour.

Cryogenic setup
The silicon ion trap is cooled to 10 K in a closed-cycle, two-stage, Gifford McMahon cryostat equipped with a vibration-isolation system [19,15] to reduce the vibrations at the trap to around 100 nm at 2 Hz. The trap is attached to the second cooling stage of the cryostat (figure 2(a)). It is enclosed by a copper shield, also cooled to 10 K. This minimises the incident black-body radiation and reduces the number of background molecules at the trapping site, as they freeze on the shield walls. To reduce surface contamination caused by molecules freezing out on the trap electrodes during the cool down, the second stage of the cryostat is kept at 320 K till the first stage has reached a temperature of 240 K. Thereafter the second stage is cooled to 10 K, while the first stage reaches a final temperature of 50 K. 40 Ca + ions are loaded from a neutral Cabeam produced by a resistively heated oven located within the vacuum chamber but not mechanically connected to the cold stage. The atoms are introduced to the trapping region through a small hole in the copper shield (diameter ∼3 mm) and are ionized by a two-photon process [20] in the trapping region.
The voltage on the RF electrodes (amplitude U 0 = 140 V, frequency Ω T /2π = 20.6 MHz) is provided by an LC lumped-circuit resonator driven by a function generator [19] and creates a trapping potential with trap depth of 75 meV. The power dissipation in the resonator goes as P D = U 2 0 CΩ T /2Q, where C is the resonator capacitance and Q the quality factor of the resonator. To keep P D low, C must be kept small. This can be achieved by locating the resonator in vacuum next to the trap on the cold stage of the cryostat (see figure 2(a)). This reduces C to 9.5 pF, which is mainly limited by the capacitance of the RF electrodes. The power necessary for trapping is less than 10 mW, which is well below the cryostat's cooling power of 500 mW and increases the temperature measured next to the trap by only 0.2 K. Filters with a cut-off frequency of 4.8 kHz are mounted on the cold stage next to the resonator in order to filter the voltages applied to the DC electrodes (see Appendix A.2 for further details on the LC resonator and DC filters).

Silicon at cryogenic temperatures
Intrinsic silicon is already used for several superconducting-qubit applications in the mK-range [21,22]. In contrast, all silicon-based ion traps to date have been designed for room-temperature operation. In some cases, the issue of RF losses was mitigated by using highly doped silicon for the trap electrodes [23,24] or substrate [25]. This method would not, however, work in a cryogenic environment because of the silicon's low electrical conductivity at low temperatures. In other cases there was an additional ground electrode which shielded the silicon against the trapping RF voltage [12,13]. At low temperature the charge carriers in intrinsic silicon freeze out, leaving the substrate as . Resonator quality factor as a function of temperature. The inductive and capacitive parts of the LC resonator are predominantly provided by a copper air-coil and the trap RF electrodes, respectively. At room temperature, the entire RF driving power is absorbed by the silicon substrate and there is no measurable resonance. On cooling, the conductivity of the inductor increases (thereby increasing its quality factor, Q L ). Cooling also reduces the charge-carrier concentration in the silicon and, below 100 K, causes a steep decrease of its electrical conductivity and loss tangent (thereby increasing the capacitive quality factor, Q C ). These effects all serve to increase the overall Q, with the plateau around 100 K being due to the non-linear response of the material properties. Below 20 K, the quality factor is comparable to that measured with a fused-silica trap, meaning that Q is limited by Q L and that Q C Q L . The data shown were measured in trap #1 (cf. table 1). The other five traps tested showed similar behaviour. a good insulator with low RF loss. This obviates the need for a shielding electrode, which in turn reduces the trap capacitance and the power dissipation, as well as permitting a range of new fabrication techniques.
The traps presented here are especially built for low-temperature applications. The characterisation of the RF resonator (including the trap) as a function of temperature is shown in figure 3. The inductor of the LC resonator is provided by a copper coil with an air (vacuum) core and the capacitance primarily comes from the trap RF electrodes. The quality factor, Q, was recorded while the cryostat was slowly heated up. The temperature was measured by a silicon diode mounted on the copper trap carrier. Q follows the relation 1/Q = 1/Q L + 1/Q C , where Q L and Q C are the quality factors of the inductor and the capacitor, respectively.
At room temperature the silicon substrate, which supports the RF electrodes, has a very high loss tangent [14], tan δ, of 1.5 at the driving frequency Ω T /2π = 20.6 MHz. For comparison [26], under the same conditions, tan δ of fused silica is around ∼10 −4 . Due to the high loss tangent, at room temperature the entire RF driving power is absorbed by the silicon substrate. There is no measurable resonance: using an impedance analyser the resonator Q was indistinguishable from zero. In contrast, a quality factor of 400 was measured in a similar trap fabricated on a fused-silica substrate and operated at room temperature. Cooling leads to a reduction of the charge-carrier concentration in the silicon and, below 100 K, to a steep decrease of the electrical conductivity and loss tangent. Ultimately, electron-hole pairs freeze out at ∼25 K and the silicon becomes an insulator [14]. In addition to these changes in the silicon, the electrical conductivity of the coil increases with decreasing temperature, and therefore the inductor quality factor, Q L , goes up [19]. Increasing Q C and Q L leads to an increasing overall resonator quality factor, Q, with decreasing temperature, as shown in figure 3. Below 20 K the value of Q > 1200 is comparable to that measured with a fused-silica trap at the same temperature indicating that Q is then only limited by Q L and not by RF absorption in the silicon.

Trapped ion lifetime
A trapping parameter which becomes especially important with a large number of trapped ions is the length of time for which an ion can be trapped, sometimes called the trapped-ion lifetime. Assuming a mean lifetime of 1 hour, which follows an exponential decay, a trap array holding 1000 ions would loose ions at a rate of around one per second. Ions are usually lost by collisions with background gas molecules or by motional heating. A cryogenic setup is an ideal tool to achieve long lifetimes since it provides extremely high vacuum and helps to reduce heating rates [15,16].
In trap #1, ion lifetimes of up to 9 hours were observed without laser cooling. With laser cooling, no ion losses were recorded over a total experimental period of more than 50 hours with a single ion. The trap is therefore suitable for scaling up to hundreds of ions without the need for continuous reloading. Five further traps were tested for shorter periods and the results from these traps were consistent with the more extended observations made with trap #1.

Heating rates
For many quantum-information applications ions should be at or near their motional ground state, and heating of the ions' motion degrades the quality of quantum operations. Trapped ions are predominately heated by electric-field noise resonant with the ions' motional frequencies. To measure the heating rate [27], the axial motion of a single ion was cooled to near the ground state by resolved-sideband cooling. Following a predefined waiting time, the mean phonon number was determined by two different methods: measurement of the transition probability on the red and blue sidebands and Rabi flops on the blue sideband [27]. The heating rate was determined by the change in phonon number with different waiting times ( figure 4).
Over a period of six weeks, the heating rate in trap #1 was measured several times and found to be constant, within the error bars, atṅ = 0.6(2) phonons/s. The electricfield noise inferred to underlie this heating [16] is S E = 4.4 × 10 −15 V 2 m −2 Hz −1 . Heating Figure 4. Heating-rate measurement. Mean phonon numbern of the axial mode (ω z /2π = 1.069 MHz) as a function of the waiting time after ground state cooling. n was determined by measuring the Rabi flops on the blue sideband [27]. In this instance the heating rate, taken to be the gradient of a linear fit to the data, iṡ n = 0.37(6) phonons/s. Taking data on different days over a period of six weeks the trap exhibited a heating rate ofṅ = 0.6(2) phonons/s. Table 1. Heating rates of different Si traps. Heating rates of six traps, all of the same design, with an ion-electrode separation of 230 µm. Measurements were made over 84 days. Traps #1-5 were taken from a single Si wafer, with trap #6 being from a second wafer. The heating rate measured in trap #5 is 0.33(4) phonons/s, which is the lowest rate ever reported. Trap #5 exhibits a heating rate of 0.33(4) phonons/s, which is the lowest rate ever reported: the lowest previously-reported heating rates are 0.83(10) phonons/s at room temperature, in a trap with a 3.5 mm ion-electrode separation [28], and 2.1(3) phonons/s at cryogenic temperatures in an trap with a 100 µm ion-electrode separation [29]. Trap #6 exhibits a heating rate of 21.5(8) phonons/s. This falls well within the range of heating rates observed in other cryogenic ion traps [16,30], but is is significantly higher than the other five traps tested here. The second wafer, from which trap #6 was taken, was patterned separately from the first, using slightly modified etch parameters. It is conjectured that this may be the reason for the higher heating rate.

Conclusion
We have presented a new ion-trap design based on a silicon substrate. This will allow trap fabrication to benefit from well-developed silicon-fabrication processes. The design was made possible by exploiting the fact that, at low temperatures, silicon becomes an insulator with low RF losses. The traps exhibit a high Q and reproducibly low ion-heating rates. Fabrication can be easily extended to include slots for increased optical access and through-wafer vias. Unlike room-temperature silicon traps, vias in our design would also work at RF frequencies, allowing the realization of a 2D trap array with adjustable RF electrodes [31]. Heating-rate and lifetime measurements indicate that a trap array based on our design with several hundred sites should be practicable. Moreover, one might ultimately envision such trap arrays integrated with a wide variety of other silicon-based technologies including CMOS electronics, microoptics, micro-and nano-mechanical systems, and sensors. This would ultimately mean that the entire science package, including optical, mechanical, and electronic functions could be integrated on a single substrate to provide a quantum lab on a chip.

Appendix A.
Appendix A. 1

. Trap fabrication and packaging
High-purity float-zone silicon wafers (diameter: 100 mm, thickness: 525 µm) with specific resistivity larger than 5000 Ωcm were used. The wafers were coated by the positive photoresist AZ1518 with a thickness of 2.4 µm. The resist was patterned by means of standard optical lithography. The wafers were deep reactive ion etched by gas chopping based on SF 6 and C 4 F 8 to create trenches with slight undercuts separating the different electrodes of the ion traps. The 10 µm gaps between the electrodes were etched to a depth of ∼100 µm with an undercut of ∼1 µm. The resist was then removed by O 2 plasma cleaning. A 2 µm thick SiO 2 layer was grown on the silicon surface by thermal oxidation to prevent metals from diffusing into the silicon. Each wafer provided 52 traps and the individual trap chips were separated by laser scribing. To form the electrodes, titanium and gold layers of a thickness of 2 nm and 500 nm respectively were deposited on the substrate surface by electron-beam evaporation. No further cleaning steps were performed after evaporation.
Traps were mounted on a copper carrier. To ensure good thermal contact between the trap and the carrier, each trap was coated on the backside with a thin layer of heat-conducting grease and then clamped in place by two stainless-steel forks. Printed circuit boards (PCBs) supporting the DC filters and the LC resonator where glued to the carrier. The trap electrodes were connected to the PCBs by 25 µm thick gold wirebonds. The copper traces on the PCBs were partially gold-electroplated to increase the adhesion of the bonding wires. The entire fabrication and assembly process took place in a cleanroom to reduce surface contamination. The only exception to this was installing the trap in the cryostat itself which was not located in a cleanroom, though this step took less than ten minutes.

Appendix A.2. LC resonator and DC filter
The lumped-circuit LC resonator is similar to that reported by Gandolfi et al. [19] and is formed by a copper air-coil inductor with an inductance of 6.3 µH mounted next to the trap, a capacitance of 9.5 pF provided by the trap's RF electrodes, and a capacitive voltage divider. The circuit's resonance frequency is 20.6 MHz at 10 K. The capacitive divider, which allows the measurement of the voltage on the RF electrodes, has a ratio of 1:400 and a total capacitance of 2.5 pF. Furthermore, there is a matching network to match the LC circuit to 50 Ω. This consists of a tunable capacitor (12-100 pF) and an inductor (186 nH) connected in series and parallel, respectively.
For best trapping performance all DC electrodes must be properly RF-grounded which can be accomplished by installing capacitors as close as possible to the DC electrodes. For this reason, small surface-mounted NP0 capacitors with a capacitance of 470 pF are located ∼15 mm from the electrodes. Additionally, RC low-pass filters are used to filter RF noise on the DC lines. The filters each consist of a 100 Ω thin-film resistor and a 330 nF NP0 capacitor placed ∼30 mm from the trap. The cut-off frequency of these filters is 4.8 kHz. The resistors and capacitors used are cryo-compatible and do not significantly change performance during cooling. In addition to these filters there are 6th-order RC low-pass filters outside of the vacuum chamber with a cut-off frequency of 80 Hz.