Cryogenic surface ion trap based on intrinsic silicon

Trapped ions are pre-eminent candidates for building quantum information processors and quantum simulators. To scale such systems to more than a few tens of ions it is important to tackle the observed high ion-heating rates and create scalable trap structures which can be simply and reliably produced. Here, we report on cryogenically operated intrinsic-silicon ion traps which can be rapidly and easily fabricated using standard semiconductor technologies. Single 40Ca+ ions have been trapped and used to characterize the trap operation. Long ion lifetimes were observed with the traps exhibiting heating rates as low as n ¯ ˙ = ?> 0.33 phonons s−1 at an ion-electrode distance of 230 μm. These results open many new avenues to arrays of micro-fabricated ion traps.


Introduction
Processing information using a quantum system allows problems to be solved which are difficult or impossible to compute classically [1], and trapped atomic ions provide a promising platform for such quantum information processors [2][3][4]. Ions can be confined using a combination of radio-frequency (RF) and static (dc) electric fields [5]. The electrode structures required to create the appropriate fields can take a variety of geometries, and great progress has recently been made using planar structures [6,7]. For these, all electrodes are located in a plane above which the ions are trapped. Notable among the advantages of such a structure is the scalability [8]: arrays with hundreds or thousands of traps can in principle be built on a single chip using very-large-scale integration technologies like optical lithography and etching, far exceeding what is possible using bulk fabrication.
In making such traps a reality, a number of features must be considered. It is essential that scalable trap architectures have low RF losses: if the losses are too high the RF power applied in order to trap will be dissipated in the chip. Additionally, microfabrication has become highly developed and it would be desirable to bring these techniques to bear on ion traps. For large arrays of traps the creation of through-wafer vias [9], so that electrical connections can be made throughout the array, is a prerequisite. Optical addressing of ions in an array can be facilitated by fabrication of holes through the substrate. Moreover, the integration of on-chip electronics, such as would be afforded by complementary metal-oxide-semiconductors (CMOS), would open up untold possibilities for ion traps [10,11].
Surface ion traps can be broadly divided into two groups, according to the type of substrate material: dielectric or semiconductor. Dielectric substrates like sapphire or fused silica have a very low RF power dissipation. For such traps the electrodes are created by simple optical lithography combined with lift-off processes or electroplating on top of the substrate [12]. However, dielectric materials are difficult to pattern by means of wet or dry etching and not suitable for features such as through-wafer vias. The second type of substrate materials are semiconductors, such as silicon, which are easy to structure. Slots, holes and vias with aspect ratios up to 160 can be etched by standard techniques [13]. However, the RF losses in intrinsic (i.e. undoped) silicon at room temperature are significant.
In some cases, the issue of RF losses was mitigated by using highly doped silicon for the trap electrodes [14,15] or substrate [16]. This method would not, however, work in a cryogenic environment because of the siliconʼs low electrical conductivity at low temperatures. In other cases there was an additional ground electrode which shielded the silicon against the trapping RF voltage [17][18][19]. This type of trap can also be operated at cryogenic temperatures [20], though it necessitates a more complicated fabrication process and precludes vias for RF electrodes.
At low temperatures, the charge carriers in intrinsic silicon freeze out, leaving the substrate as a good insulator with low RF loss. This obviates the need for a shielding electrode. By operating intrinsic-silicon traps at cryogenic temperatures and omitting the shielding groundplane, the trap capacitances and the amount of power dissipated can be reduced. A range of fabrication techniques also become available, which would have otherwise have been precluded either by the substrate material or the ground plane. Intrinsic silicon is already used for several superconducting-qubit applications in the mK-range [21,22], though all silicon-based ion traps to date have been designed to operate at room-temperature.
In this paper, we report on silicon-based surface ion traps built for cryogenic applications. The cryogenic environment inheres several advantages which are well known. Ultra-high vacuum can be attained within a few hours due to cryogenic pumping, without baking the system [23]. This facilitates fast turn-around times for trap installation (∼1 day). Furthermore, operation at liquid-helium temperatures reduces the rate at which the ions' motion is heated, typically by around two orders of magnitude [24]. This is beneficial as it increases the coherence time of the ions' motion, which is used to transfer quantum information between different ions. In addition to these benefits, the novel use of intrinsic silicon as a trap material means that the traps neither need nor have a ground plane to shield the substrate. This allows for a very simple basic fabrication procedure and permits the use of standard silicon processing techniques, while mitigating the problems of RF loss.

Design overview and fabrication
The planar design used for this work is illustrated in figure 1. The electrode layout is based on a similar design used elsewhere [25]. Ions are trapped 230 μm above the centre electrode by applying an RF voltage to the two RF electrodes. Lasers used to Doppler cool the ions are aligned parallel to the plane of the trap, to minimize scatter from the surface. To efficiently cool the ions along all three principal axes of their motion, each axis must have a projection along the direction of the cooling laser beam. Consequently, none of the principal axes of motion should be perpendicular to the trap surface. The RF electrodes have thus been fabricated with unequal widths ensuring that the two radial principal axes both have a component parallel to the trap surface [26]. Seven segmented electrodes are located on each side of the two RF electrodes. Dc voltages are applied to these electrodes and create confinement along the axial (z) direction. Ions can be shuttled along the z-axis by changing the dc voltages. Stray electric fields arising from contamination of the trap or imperfection in trap fabrication can cause micromotion [27], which is minimized by adding suitable dc voltages to the segmented dc electrodes.
To fabricate the traps an intrinsic silicon substrate is patterned by optical lithography and deep reactive ion etching (see figure 2(b)). Deep, undercut trenches are etched in the substrate and mark the gaps between the individual electrodes. Following a thermal growth of 2 μm of SiO 2 the electrodes are formed by evaporation of gold perpendicular to the surface. Due to the undercuts, there is no electrical connection between the different electrodes (figures 1(b) and 2(b)) and no further lift-off or etching steps are necessary. There are no further cleaning steps and, to avoid any contamination of the surface, the gold electrodes are never brought into contact with liquids such as solvents for cleaning. The fabrication process and the packaging are explained in detail in appendix A.1.
Initially, the operation of a single trap (trap #1) was characterized in detail over several weeks. To demonstrate the reproducibility of the results, a further five traps-randomly selected from two different silicon wafers-were tested and shown to exhibit similar behaviour.

Cryogenic setup
The silicon ion trap is cooled to 10 K in a closed-cycle, two-stage, Gifford McMahon cryostat equipped with a vibration-isolation system [23,28] to reduce the vibrations at the trap to around 100 nm at 2 Hz. The trap is attached to the second cooling stage of the cryostat (figure 2(a)). It is enclosed by a copper shield, also cooled to 10 K. This minimizes the incident black-body radiation and reduces the number of background molecules at the trapping site, as they freeze on the shield walls. Surface contamination caused by background gas molecules freezing out on the trap electrodes during the cool down can be reduced by temporarily heating the trap. Since the background gas mainly consists of water, it is sufficient to keep the trap at 320 K till the first stage of the cryostat has reached a temperature of 240 K. Thereafter the second stage is cooled to 10 K, while the first stage reaches a final temperature of 50 K. 40 Ca + ions are loaded from a neutral Ca-beam produced by a resistively heated oven located within the vacuum chamber but not mechanically connected to the cold stage. The atoms are introduced to the trapping region through a small hole in the copper shield (diameter ∼3 mm) and are ionized by a two-photon process [29] in the trapping region.
The voltage on the RF electrodes (amplitude = U 140 0 V, frequency Ω π = 2 20.6 T MHz) is provided by an LC lumped-circuit resonator driven by a function generator [28] and creates a trapping potential with trap depth of 75 meV. The power dissipation in the resonator goes as , where C is the resonator capacitance and Q the quality factor of the resonator. To keep P D low, C must be kept small. This is achieved by locating the resonator in vacuum next to the trap on the cold stage of the cryostat (see figure 2(a)). The measured C is 9.5 pF, which is mainly limited by the capacitance of the RF electrodes. The power necessary for trapping is less than 10 mW, which is well below the cryostatʼs cooling power of 500 mW and increases the temperature measured next to the trap by only 0.

Silicon at cryogenic temperatures
The characterization of the RF resonator (including the trap) as a function of temperature is shown in figure 3. The inductor of the LC resonator is provided by a copper coil with an air (vacuum) core and the capacitance primarily comes from the trapʼs RF electrodes. The quality factor, Q, was recorded while the cryostat was slowly heated up. The temperature was measured by a silicon diode mounted on the copper trap carrier. Q follows the relation = + Q Q Q 1 1 1 L C , where Q L and Q C are the quality factors of the inductor and the capacitor, respectively.
At room temperature the silicon substrate, which supports the RF electrodes, has a very high loss tangent [30], tan δ, of 1.5 at the driving frequency Ω π = 2 T 20.6 MHz. For comparison, under the same conditions, tan δ of fused silica is around ∼10 −4 [31]. Due to the high loss tangent, at room temperature the entire RF driving power is absorbed by the silicon substrate. There is no measurable resonance: using an impedance analyzer the measured resonator Q was less than 20, and within the measurement uncertainty it was indistinguishable from zero. In contrast, a quality factor of 400 was measured in a similar trap fabricated on a fused-silica substrate and operated at room temperature. Cooling leads to a reduction of the charge-carrier concentration in the silicon and, below 100 K, to a steep decrease of the electrical conductivity and loss tangent. Ultimately, all free charge carriers freeze out at ∼25 K and the silicon becomes an insulator [30]. In addition to these changes in the silicon, the electrical conductivity of the coil increases with decreasing temperature, and therefore the inductor quality factor, Q L , goes up [28]. Increasing Q C and Q L leads to an increasing overall resonator quality factor, Q, with decreasing temperature, as shown in figure 3. Below 20 K the value of > Q 1200 is comparable to that measured with a fused-silica trap at the same temperature indicating that Q is then only limited by Q L and not by RF absorption in the silicon.
Photocharging of trap structures has previously been observed in a number of experiments [32,33]. In the traps reported here, it is in principle possible that photons could also excite charge carriers in the silicon of the trenches' sidewalls which are not covered by gold. Such an effect could disturb trap operation. To investigate this possibility, the resonatorʼs quality factor was measured at low temperature both with trapping lasers on and off to determine the influence of the laser light. The trap was directly illuminated with around − 10 mW cm 2 of laser light at each of the wavelengths used to trap 40 Ca + ions (375 nm, 397 nm, 422 nm, 729 nm, 854 nm and 866 nm). However, no changes in performance were observed. Furthermore, while trapping 40 Ca + ions, no effects due to photocharging of the substrate were observed.

Trapped ion lifetime
A trapping parameter which becomes especially important with a large number of trapped ions is the length of time for which an ion can be trapped, sometimes called the trapped-ion lifetime. The loss of a single ion can complicate the implementation of, for example, a quantum algorithm. While trapping lifetimes of a few minutes may be acceptable for experiments using small numbers of ions, experiments with many ions require significantly longer ion lifetimes, as the probability of losing an ion increases. Ions are usually lost by collisions with background gas molecules or by motional heating. A cryogenic setup is an ideal tool to achieve long Resonator quality factor as a function of temperature. The inductive and capacitive parts of the LC resonator are predominantly provided by a copper air-coil and the trap RF electrodes, respectively. At room temperature, the entire RF driving power is absorbed by the silicon substrate and there is no measurable resonance. On cooling, the conductivity of the inductor increases (thereby increasing its quality factor, Q L ). Cooling also reduces the charge-carrier concentration in the silicon and, below 100 K, causes a steep decrease of its electrical conductivity and loss tangent (thereby increasing the capacitive quality factor, Q C ). These effects all serve to increase the overall Q, with the plateau around 100 K being due to the nonlinear response of the material properties. Below 20 K, the quality factor is comparable to that measured with a fused-silica trap, meaning that Q is limited by Q L and that ≫ Q Q C L . The data shown were measured in trap #1 (see table 1). The other five traps tested showed similar behaviour.
lifetimes since it provides extremely high vacuum and helps to reduce heating rates [23,24,34,36].
Cooled and uncooled ion lifetimes were investigated using trap #1. With laser cooling, no ion losses were recorded over a total experimental period of more than 50 h with a single ion. To investigate uncooled lifetimes, the lasers were turned off and, after some waiting time, turned back on to see if the ion was still trapped. Waiting times of up to 9 h were used, and the ions were never lost. The trap is therefore suitable for scaling up to hundreds of ions without the need for continuous reloading. Five further traps were tested for shorter periods and the results from these traps were consistent with the more extended observations made with trap #1.

Heating rates
For many quantum-information applications ions should be at or near their motional ground state, and heating of the ions' motion degrades the quality of quantum operations. Trapped ions are predominately heated by electric-field noise resonant with the ions' motional frequencies.
To measure the heating rate [35], the axial motion of a single ion was cooled to near the ground state by resolved-sideband cooling. Following a predefined waiting time, the mean phonon number was determined by two different methods: measurement of the transition probability on the red and blue sidebands and Rabi flops on the blue sideband [35]. The heating rate was determined by the change in phonon number with different waiting times ( figure 4).
Over a period of six weeks, the heating rate in trap #1 was measured several times and found to be constant, within the error bars, at = ṅ 0.6(2) phonons s −1 . The electric-field noise inferred to underlie this heating [36] Heating rates were measured in five further traps, four from the same wafer and one (trap #6) from a second wafer, with the results given in table 1.
Trap #5 exhibits a heating rate of 0.33(4) phonons s −1 , which is the lowest measured heating rate ever reported: the lowest previously-reported heating rate at room temperature was 0.83(10) phonons s −1 in a trap with a 3.5 mm ion-electrode separation [37]. The lowest previously-reported ) as a function of the waiting time after ground-state cooling. n was determined by measuring the Rabi flops on the blue sideband [35]. In this instance the heating rate, taken to be the gradient of a linear fit to the data, is = ṅ 0.37(6) phonons s −1 . Taking data on different days over a period of six weeks the trap exhibited a heating rate of = ṅ 0.6(2) phonons s −1 .
heating rate at cryogenic temperatures was 2.1(3) phonons s −1 in a trap with a 100 μm ion-electrode separation [38]. It is not known to what extent the lower heating rate in the present trap can be attributed to the use of silicon, rather than the lower temperature (compared to [37]) or larger trap dimensions (compared to [38]). The reason for the variation in heating rates between traps on the same wafer is not known, though it is not necessarily surprising, given the level of variation which is often observed in nominally identical traps [36]. Trap #6 exhibits a heating rate of 21.5(8) phonons s −1 . This falls well within the range of heating rates observed in other cryogenic ion traps [36,39], but is is significantly higher than the other five traps tested here. The second wafer, from which trap #6 was taken, was nominally identical to the first, but was patterned separately. Slightly modified etch parameters were used, so that the underetch initially proceeded at a steeper angle. It is not known whether this is related to the higher heating rate.

Conclusion and outlook
We have presented a new ion-trap design based on a silicon substrate. This will allow trap fabrication to benefit from well-developed silicon-fabrication processes. The design was made possible by exploiting the fact that, at low temperatures, intrinsic silicon becomes an insulator with low RF losses. The traps exhibit a high Q of >1200 and reproducibly low ion-heating rates of around 1 phonon per second at a trap frequency of 1 MHz. Fabrication could be extended to include slots for increased optical access [17] and through-wafer vias [9]. Unlike room-temperature silicon traps, vias in our design would also work at RF frequencies, allowing the realization of a 2D trap array with adjustable RF electrodes [40]. One may ultimately envision such traps integrated with a wide variety of other silicon-based technologies including CMOS electronics [10,11], micro-optics [41], micro-and nano-mechanical systems, and sensors. This would ultimately mean that the entire science package, including optical, mechanical, and electronic functions could be integrated on a single substrate to provide a quantum lab on a chip. reason, small surface-mounted NP0 capacitors with a capacitance of 470 pF (Kemet-C0805C471J1GACTU) are located ∼15 mm from the electrodes. Additionally, RC lowpass filters are used to filter RF noise on the dc lines. The filters each consist of a 100 Ω thinfilm resistor (VPG-Y1625100R000Q9R) and a 330 nF NP0 capacitor (Kemet-C2220C334J1GACTU) placed ∼30 mm from the trap. The cut-off frequency of these filters is 4.8 kHz. The resistors and capacitors used are cryo-compatible and do not significantly change performance during cooling. In addition to these filters there are 6th-order RC low-pass filters outside of the vacuum chamber with a cut-off frequency of 80 Hz.