Double-gated graphene-based devices

We discuss transport through double gated single and few layer graphene devices. This kind of device configuration has been used to investigate the modulation of the energy band structure through the application of an external perpendicular electric field, a unique property of few layer graphene systems. Here we discuss technological details that are important for the fabrication of top gated structures, based on electron-gun evaporation of SiO$_2$. We perform a statistical study that demonstrates how --contrary to expectations-- the breakdown field of electron-gun evaporated thin SiO$_2$ films is comparable to that of thermally grown oxide layers. We find that a high breakdown field can be achieved in evaporated SiO$_2$ only if the oxide deposition is directly followed by the metallization of the top electrodes, without exposure to air of the SiO$_2$ layer.


Introduction
The ability to isolate and embed single-and multi-layer graphene in double gated structures is paving the way to reveal unique electronic properties of these systems [1,2,3,4,5,6,7,8,9,10,11,12,13]. The ability to change the voltages applied to a nano-fabricated top gate and to the back-gate offers the possibility to gain local control of the charge density and of imposing locally a perpendicular electric field. This device configuration was used recently to show how the band structure of graphene-based materials can be tuned continuously [8,12]. In particular, bilayer graphene exhibits an electric field induced insulating state due to the opening of a gap between valence and conduction band [8], and in trilayers, which are semi-metals, the band-overlap can be increased substantially [12]. Cleverly designed top gates on a graphene single layer have also been used successfully for engineering p-n junctions [1,2,3,5,6,7], necessary for the investigation of Klein tunneling [1,3,4], and to attempt the fabrication of controlled quantum dots [15,16]. Key to the fabrication of top gated structures is the ability to deposit good quality thin gate oxides, with high breakdown field and low leakage current. Here, after reviewing the relevance of double gated devices on the electric field modulation of the band structure of double and triple layer graphene, we discuss in some details technological aspects related to the properties of the SiO 2 layers used as gate insulators. In particular, we discuss how we can routinely achieve high breakdown fields in electron-gun evaporated thin SiO 2 films (15 nm), comparable to the breakdown fields of thermally grown SiO 2 , which is surprising given that SiO 2 deposited by evaporation was long believed to be a poor quality insulator. To unveil the reasons behind the good insulating quality of our evaporated SiO 2 films, we conducted a statistical study of leakage current and breakdown voltage in capacitors, where two metallic electrodes are separated by a SiO 2 layer fabricated in different ways. We demonstrate that if SiO 2 and top gate metal electrodes are deposited subsequently without exposing the SiO 2 to air, the electrical performance of electron-gun evaporated SiO 2 is comparable to that of thermally grown SiO 2 . In contrast, exposure to air of the SiO 2 layer before deposition of the counter-electrode leads to much worse insulating characteristics. Our findings indicate that extrinsic degradation -probably due to the absorption of humidity-has limited in the past the insulating quality of electron-gun evaporated SiO 2 .

Device and fabrication
Single and few layer graphene flakes used for the device fabrication were obtained by micro-mechanical cleavage of natural graphite crystals, and by their subsequent transfer onto a highly doped Silicon substrate (acting as a gate) covered by a 285 nm thick thermally grown SiO 2 layer. The thickness of the graphene layers can be simply identified by analyzing the shift in intensity in the RGB green channel relative to the substrate (i.e. Relative Green Shift) [8,12,14,17,18]. A plot of the relative green shift, as extracted from optical microscope images of various samples taken with a digital camera, exhibits plateaus corresponding to the discrete thickness values -see Fig. 1a. Subsequent transport measurements (quantum Hall effect, resistance dependence on a perpendicular electric field, etc.) confirm the validity of this optical method (Fig. 1b). The fabrication of nanostructures is accomplished by conventional electron-beam lithography. Metallic contacts and top gates were deposited by electron-gun evaporation, respectively of Ti/Au (10/25nm thick with a back ground pressure of 9 * 10 −7 torr) for contacts and SiO 2 /Ti/Au (15/10/25nm thick with a back ground pressure of 3 * 10 −7 torr) for top gates, followed by lift-off. We took special care to fabricate all the ohmic contacts within 60 nm from the edges of the top gated areas, so that two probe resistance measurements are dominated by the resistance of the double gated region [19]. All transport measurements in double gated devices (see Fig. 1c) were made using a lock-in technique (excitation frequency: 19.3Hz), in the linear transport regime, at temperatures ranging from 300 mK up to 150K. To understand why, contrary to expectations, we manage to achieve high breakdown field in thin, electron-beam evaporated SiO 2 films, we conducted a macroscopic study of the breakdown characteristics on two types of capacitor test structures. The first -which we refer to as type A-is characterized by subsequent evaporation of SiO 2 /Ti/Au without breaking the vacuum in between the deposition of the different materials. For the second -type B SiO 2 -we exposed the device to ambient for one hour after the SiO 2 deposition, before evaporating the Ti/Au counter electrode. The breakdown test measurements were made with a Keithley-2400 source-meter on more than 130 different capacitors (with three different surface areas: 125 × 115µm 2 , 175 × 150µm 2 and 215 × 195µm 2 ).

Transport experiments in double gated few layer graphene devices
The measurement configuration used for double gated devices is shown in Fig. 1c. A finite voltage applied to either one of the gates (back or top gate) changes the position of the Fermi level in the corresponding gated region of the graphene layer, by an amount corresponding to the induced charge density. In addition, by biasing the two gate electrodes with opposite polarity, a large external electric field applied perpendicular to the layer is generated, which is equal to E ex = (V bg − V tg )/d tot (d tot = 15 + 285nm is the total SiO 2 thickness). In this device configuration, we can monitor the evolution of the in plane transport properties for each few layer graphene device as a function of E ex . Fig. 1d, e and f show the typical behavior of the square resistance measured respectively in double gated single (d), double (e) and triple (f) layer graphene, when sweeping the top gate, while keeping the back gate at a fixed potential. It is apparent that the overall electric field dependence of R sq is markedly distinct for graphene layers of different thickness. In all cases, the resistance exhibits a maximum (R max sq ) whose value and position in gate voltage depend on the voltage applied to the gate on which a fixed potential is applied during the measurement. At E ex = 0 V/m we find that for single and bilayer graphene R max sq ∼ 6KΩ, close to a conductance per square of 4e 2 /h, as expected,  indicating that the fabrication of top gate structures does not damage significantly the material (for trilayers the square resistance is somewhat lower, owing to the presence of an overlap between valence and conduction band). Increasing the external electric field induces a well defined -and different-response for the square resistance of layers of different thickness. Respectively, in a single layer R max sq is not affected by a finite E ex ; in bilayers at low temperature R max sq increases from 6KΩ to very large values (> 100 KΩ); in trilayers R max sq decreases with increasing E ex . These experimental findings, confirmed in a number of different samples (3 single layers, over 10 double and 10 triple layers) provide a clear indication that each few layer graphene is a unique material system, with distinct electronic properties. Transport measurements over a wide range of temperatures (from 300mK up to 150K) underline the unique electronic properties of these few layer graphene devices. In bilayer graphene the larger E ex , the more pronounced is the temperature dependence of R max sq , see Fig. 2a and b. At E ex = 0 V/m, R max sq is only weakly temperature dependent (as it is typical of zero-gap semiconductors), and at E ex = 0 V/m the observed behavior is the one typical of an insulating state. On the contrary, trilayer graphene devices display a decrease of R max sq when lowering the temperature, stemming for the semimetallic nature of the constituent material.
At a more quantitative level we find that R max sq in bilayer graphene is well described by ∝ exp(T 0 /T ) 1/3 , with T 0 ≈ 20 K at the maximum applied external electric field (see inset in Fig. 2b). This temperature dependence is indicative of variable-range hopping in a two dimensional material where an energy gap has opened, and where disorder causes the presence of sub-gap states (T 0 is related to this subgap density of states [8]) -making it difficult to estimate ∆ from transport experiments. Indeed, in a disorder free bilayer graphene, at E ex = 0 a gap (∆) opens in the band structure and the density of states in the gapped region is zero. In this ideal case, when the Fermi level is in the middle of the gapped region the value of R max sq at a finite temperature is entirely determined by thermally activated charge carriers (R max sq ∝ exp(∆/2k B T )). Therefore, ∆ can be accurately determined from a plot of ln(R max sq ) versus 1/T . On the other hand, in real devices the presence of disorder creates a finite density of states in the the band gap of bilayer graphene. Now charge carriers can conduct via variablerange hopping at R max sq . In this case R max sq is a function of the density of states at the Fermi level and not any more simply a function of ∆. The fact that a gap opens in the band structure of bilayer graphene at finite E ex is evident from the temperature dependence of R sq as a function of charge density. In particular, when the Fermi level lays deep into the conduction and/or valence band, a temperature independent R sq is expected. However, when the Fermi level is shifted across the energy gap region R sq should display an insulating temperature dependent behavior. Experimentally this is achieved by measuring R sq at a fixed value of either of the gates (e.g. V bg ) and for different voltage applied on the other gate (e.g. V tg ) (see Fig 2a and b). The cross over from band transport to variable hopping range in the gap occurs at the edge of the valence and conduction band (see Fig. 2b). Similar previous transport experiments in double gated bilayer [8] reported an energy scale of 1-10mV associated with the insulating state induced by E ex = 0. This energy scale seen in transport is much smaller than the energy gap recently probed in optical spectroscopy experiments (∆ ∼ 200mV at E ex = 2V /nm [22]). Possibly the finite sub-gap density of states induced by the disorder is at the origin of the small energy scale measured in transport experiments, however the specific mechanism responsible for these experimental observations remains an open question. The temperature dependence of the resistance in trilayer graphene is opposite to the one observed in bilayers, and it reveals that this material system is a semimetal with a finite overlap (δε) between conduction and valence band. This band overlap can be estimated within a two band model [12,20,21], where the number of thermally excited carriers increases with temperature according to n(T ) = (16πm * /h 2 c)k B T ln(1 + e δε/2K B T ) (m * effective mass and c equal to twice the layer spacing). Measurements at finite E ex show that δε decreases when increasing external electric field (δε goes from 32 meV to 52 meV in the measurements of Fig. 2d). These experiments demonstrate that a perpendicular electric field applied on few layer graphene is a valuable tool to change the band structure of these materials. Double gated structures lead to the discovery of the only known electric field tunable insulator, i.e. bilayer graphene, and of the only known electric field tunable semimetal, i.e. trilayer graphene.

Evaporated Silicon oxide as top gate dielectric
The opening of a sizeable band gap in bilayer graphene, and large changes in the band overlap of graphene trilayers require the application of large external electric fields to these material systems. It is the breakdown field of the gate-dielectric that imposes a limit to the maximum value of E ex experimentally accessible in double gated structures. To optimize this aspect of the devices, we conducted a systematic study of the breakdown electric field of SiO 2 gate oxide for devices with different areas, fabricated under different conditions. Here we discuss the details of this investigation. From our statistical analysis we conclude that what is crucial is not the SiO 2 deposition method, but the details in the metallization of top gate electrodes afterwards, which affect the final quality of the oxide gate dielectric. We compare capacitor devices fabricated following two different procedures for one of the oxide dielectric/metal electrode interfaces. In particular, the devices were fabricated on a Si/SiO 2 substrate (identical to the one used for the graphene devices previously described) on which we deposit a Ti/Au (5/20 nm) film -common electrode for the capacitors. In devices of type A, the SiO 2 deposition and top electrode (Ti/Au 5/20 nm) metallization processes were carried without breaking the vacuum. On the contrary in devices of type B, the SiO 2 gate dielectric was exposed to air for one hour prior to the deposition of the top electrode metals. The SiO 2 deposition was carried out typically at 3 * 10 −7 torr back ground pressures. We did not observe a dependence of the insultating properties of the SiO 2 dielectric, breakdown field and leakage current over the background pressure range from 1 * 10 −7 to 5 * 10 −7 torr. Fig. 3a and b show various I − V traces, measured in ambient condition, for type A and type B devices. A first clear difference between the two types of devices is the magnitude of the leakage current, visible by plotting the I −V curves both in linear and logarithmic scale, see Fig. 3. For a surface area of 215×195µm 2 , we find I leakage ≃ 2.5 * 10 −10 A/µm 2 for the best type B devices which is one order of magnitude larger than that measured in the worst type A devices (the difference for typical devices are much larger than one order of magnitude). This extremely different level of leakage current already indicates that the exposure of SiO 2 to air previous to the deposition of top metals has a large negative influence on the insulating performance of the oxide. The I − V characteristics further show that for a fixed surface area (215 × 195µm 2 ), the breakdown voltage V BD for type A is typically in the range 8V < V BD < 9V whereas type B devices breakdown anywhere in the range 0V < V BD < 6V . The differences in the failure of device types are best summarized in the histogram plots of V BD -see Fig. 4a. For type B we find a large spread in the distribution of V BD , in contrast to  the narrow distribution characteristic of type A devices. Furthermore, the comparison of V BD for type A devices with different surface areas shows that V BD increases slightly with decreasing the device area, possibly indicating that the properties of SiO 2 in type A close to breakdown are determined by small defects present in the film with rather small probability. However, we cannot rule out that the differences between the different sample populations originate from small differences (2-3 nm) in the thickness of the SiO 2 layers. Note, in fact, that the leakage currents of these devices at low bias have only small sample-to-sample fluctuations, suggesting that the SiO 2 layers in type A devices are very uniform.
To try to quantify better our observations and analyze the role played by the specific fabrication technique and surface areas on the device performance (e.g. breakdown field), we adopt a failure analysis methodology [24]. In what follows we provide a statistical description of the breakdown probability introducing the cumulative probability (P) as the probability of a device to breakdown at a given voltage. From failure method-  ology, we notice that possibly the most flexible distribution for the failure of a population of samples, is the Weibull distribution [24,25] capacitor surface area, S 0 reference surface area, β and V 0 are the Weibull parameters). The parameter β, also known as Weibull shape parameter, determines the shape of the probability density function -i.e. higher β indicates distributions with low dispersion of V BD . V 0 is the Weibull scale parameter, whose only effect is to scale the V BD distribution (the larger V 0 , the more "stretched" the distribution). Depending on the value of the Weibull parameters, this distribution mimics the behavior of other statistical distributions such as the normal and the exponential. Given a sample population, the Weibull parameters provide a quantitative measure of the failure probability. Both β and V 0 are strongly affected by the failure mechanism which can eventually be identified when comparing the Weibull parameters for different sample populations. For instance, a value of β that does not depend on the capacitor surface area -i.e., the variance does not change with the surface area-, means that the microscopic mechanism of breakdown is common to all the samples, independent of the specific area [25]. The good agreement between a fit to the Weibull distribution of the cumulative probability for each different surface area and device types shows that the data of each different device population is well described by the Weibull distribution. To evaluate whether a single Weibull scaling law can explain breakdown results for all the different surfaces, we notice that -for type A-we can fit all the cumulative probability distributions with the same value β = 52, see Fig. 4b. This is made apparent by plotting ln(−ln(1 − P )) = ln(S/S 0 ) − βln(V 0 ) + βln(V BD ) as a function of ln(V BD ) for data sets corresponding to different surface areas. Fig. 4b and c show clearly that all the data are lined up on parallel linear slopes (i.e., β is the same in all these cases). This finding implies that the breakdown mechanism is the same for all studied surface areas. Note that V 0 varies slightly with surface area, and that, as mentioned above, we cannot exclude that the origin of these variations is a small difference in the thickness of the SiO 2 layers for the different device populations (a difference of 2-3 nm would suffice to explain this observation). We notice that β = 52 -estimated from the fit in Fig. 4b and c-is comparable to values found for thermally grown thin SiO 2 films, and it is compatible with failure of the devices due to surface roughness [23] probably being transferred to the dielectric film from the Ti/Au substrate. This quantitative analysis make it possible to state that electronbeam evaporated SiO 2 , directly coated by a metallic layer without exposure to air has an essentially identical quality to that of thermally grown oxide. A similar analysis of P for type B devices, gives a β = 3.3 -i.e. a much higher dispersion of breakdown field (see Fig. 4d). This small value for β in type B devices quantifies the much larger statistical spread of the oxide properties in these devices. Since the only difference between type A and B devices is the fabrication step of the SiO 2 /Ti interface, we conclude that exposure of the SiO 2 to air is indeed the cause for the poor insulating qualities. Indeed it is well known that SiO 2 is an hygroscopic material, that easily absorbs humidity in air. The humidity absorbed can affect the composition of the entire layer providing paths for the leakage current, and creating weak spots at which breakdown occurs already at low voltage.

Conclusions
In conclusion we have briefly reviewed transport in double gated bilayer and trilayer graphene devices. Motivated by the need for large electric fields, we have conducted a statistical study of the breakdown field for over 100 top gated structures fabricated in different conditions and with different surface areas. Adopting a failure analysis based on the Weibull distribution, we show that the most reliable top gates are obtained when depositing in SiO 2 /Ti/Au without breaking the vacuum. Electron-beam SiO 2 layers evaporated in these ways have insulating characteristics as good as those of thermally grown SiO 2 layers.