High-Yield of Memory Elements from Carbon Nanotube Field-Effect Transistors with Atomic Layer Deposited Gate Dielectric

Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. This study includes 94 CNT FET samples, providing an unprecedented basis for statistics on the hysteresis seen in five different CNT-gate configurations. We find that the memory effect can be controlled by carefully designing the gate dielectric in nm-thin layers. By using atomic layer depositions (ALD) of HfO$_{2}$ and TiO$_{2}$ in a triple-layer configuration, we achieve the first CNT FETs with consistent and narrowly distributed memory effects in their transfer characteristics.

The quasi-one-dimensional, nearly perfect, crystalline structures of CNTs make them promising candidates [1,2,3,4] to extend the down-scaling of electronic components beyond the limitations of present Si-based technology. Featuring either semiconducting or metallic transport properties, they can in principle replace both active components as well as their interconnects. It was suggested that CNT-based devices could be mounted with an integration level of up to 10 12 cm −2 [5], which is about 4 orders of magnitude higher density than in current technology. Field-effect transistors have been made out of CNTs with impressive device parameters, e.g. subthreshold slopes close to 60 mV/decade [6], and carrier mobilities of up to 9000 cm 2 /Vs [7]. But there are many challenges with incorporating CNTs into logic devices, such as being able to separate the semiconducting CNTs from the metallic ones, or to control their placement with nanometer accuracy. Another challenge with CNT FETs is that often they display some degree of hysteresis in their transfer characteristics. For a CNT FET this is an unwanted feature, rendering it unpredictable in its output, and it has motivated several studies to find ways to prevent or remove these tendencies [6,8,9,10,11]. On the other hand, the presence of hysteresis opens up the possibility to utilize the device as a memory element instead. This has been pointed out by several studies [7,12,13,14,15,16], demonstrating CNT FETs with ON and OFF states which are well separated and addressable with positive or negative gate voltage pulses. However, the challenge is to be able to control the presence of hysteresis, which so far has been reported as a more or less random property among the studied CNT FETs [13,15,17]. In this letter, we use Hf-based ALD-grown gate dielectric to control hysteresis and achieve a 100 % yield in memory effect, as well as study the origin of the hysteresis in our devices. This is to our knowledge the first report on CNT FETs featuring consistent memory effects.
Several different models have been suggested to explain the hysteresis in the transfer characteristics of a CNT FET. First it was pointed out that, especially for CNT FETs with a gate insulator of SiO 2 , it may have the same origin as the hysteresis sometimes seen in conventional Si-MOSFETs [7,12,15]. There it was shown that mobile ions or charges within the SiO 2 layer could relocate in response to the applied gate voltage, and as a result modify the local electric field sensed by the charge carriers in the conduction channel. But this is not the only proposed mechanism. It has also been suggested [7,18,19] that the charge traps may not be mobile, but located stationary in the near vicinity of the CNT. An applied gate voltage could then assist in filling or emptying the charge traps with charge carriers moving in the CNT, which in turn screens the applied electric field and causes hysteresis to appear in the gate voltage response. Yet another possibility is that surface chemistry plays an important role. E.g. water molecules adhered to the surface have been shown 1 [8,10] to give a large contribution to the hysteresis of some CNT FETs. A fourth model suggests that defects in the nanotube itself could provide charging centers, which can be filled or emptied in response to the gate modulation. A charging center in this case may be a carbon atom substituted with a different atom or molecule, which can donate or accept electrons from the conduction channel. This study includes in total 94 SWCNT FETs with varying gate insulator, which by far exceeds the number of samples included in earlier studies of hysteresis in CNT FETs [7,8,12,15,10,14,18,19]. An atomic force microscope (AFM) image of a typical sample is shown in Fig. 1. The samples were built in a bottomup approach, described in detail in the Methods section and ref. [20]. A schematic of the measurement setup is drawn in Fig. 1. Measurements were carried out at ambient conditions, and are described in the Methods section. 17 of the 94 samples had the backgate covered with ALD of Al 2 O 3 (nominal thickness: 20 nm), 14 with an ALD of HfO 2 (20 nm), 11 with an ALD of HfO 2 -TiO 2 -HfO 2 (40-0.5-3 nm), 27 with an ALD of HfO 2 -TiO 2 -HfO 2 (40-0.5-1 nm), and the remaining 25 with thermally grown SiO 2 (300 nm).
The focus of this study is on the appearance of hysteresis in the transfer characteristics of our CNT FETs. A typical example is shown in Fig. 2a for a SWCNT resting on a backgate dielectric of 20 nm thick HfO 2 with 10 mV applied between the drain and source electrodes. Most SWCNT FETs displayed typical unipolar p-type behavior [25,26], with strongly suppressed conductance at positive gate voltages and a transition into a highly conducting state at negative gate voltages. A few devices showed ambipolar dependence with a somewhat increased conductance at high positive backgate voltages, which has been attributed to semiconducting nanotubes with a small bandgap [27,28]. Upon scanning the backgate voltage back and forth, the threshold voltage attains in some, but not all, of the CNT FETs a higher value for the reverse sweep than for the forward sweep, resulting in a highly reproducible hysteresis loop with different conductance values at zero backgate voltage depending on the sweep direction. In Fig. 2b it is demonstrated how the current response of such a CNT FET can be switched between the two states by sending either a positive or negative voltage pulse to the backgate.
All mass-fabricated electronic devices have a natural variation of characteristic parameters, which is acceptable as long as the parameter distribution is narrow enough not to interfere with its intended function. The large number of devices in this study allows us to estimate the distribution of hysteresis response seen for differing gate dielectrics. We quantify the memory effect in each device in terms of the shift in threshold voltage, called the hysteresis gap (see Fig. 2a). This measure relates directly to the reconfiguration of charges trapped in the close vicinity of the SWCNT, and is sensitive to the gate voltage scan rate, the scan range, as well as the hold time at the turning points of the scanning interval before starting the next scan. While the scan rate was kept at 10 mV/s and the hold time at the turning points was close to 1 second throughout the study, the gate voltage scan range was altered between the samples due to differing gate insulator thicknesses. The samples with 300 nm thick SiO 2 dielectric were measured with a gate voltage scan range of ± 10 V, while the ALD based samples with gate insulator thicknesses of 20-43.5 nm had gate voltage scan ranges of ± 2-3 V. To allow comparison between these different cases, we calculated the relative hysteresis gap, where the hysteresis gap is normalized by the gate scan range.
Our results are plotted in Fig. 3. Each column represents a 5 % interval of the relative hysteresis gap along the x-axis. We show in Fig. 3a that from 25 SiO 2based CNT FETs, 12 devices do not exhibit hysteresis at all. The remaining 13 display a relative hysteresis gap almost evenly spread within the interval 30-65 %. The result is in agreement with earlier reports [13,15] on SiO 2 -based SWCNT FETs, finding that only a fraction of the produced devices show hysteresis in their transfer characteristics. The picture is very similar in Fig. 3b, where the SWCNT FETs have a gate dielectric of 20 nm thick ALD grown Al 2 O 3 . 5 devices show no hysteresis while 12 devices have their relative hysteresis gap within the interval 25-65 %.
For the remaining three panes of Fig. 3, there is a distinct difference in that all the fabricated devices display a clear relative hysteresis gap. With memory devices in mind, this translates into a 100 % fabrication yield. In Fig. 3c, the gate dielectric is 20 nm thick ALD grown HfO 2 . The 14 devices made have their relative hysteresis gaps spread from 10 % up to 70 % of the total gate scan range. While all CNT FETs in this set show a memory effect, the distribution of the relative hysteresis gaps is very wide, having a standard deviation of 22 %. The following two panes of Fig. 3 show data from a specially designed three-layered ALD structure. It was made in order to study the hypothesis that the lower interface of the top most HfO 2 layer plays an important role in controlling the amount of charge traps available. The first deposited layer is a 40 nm thick  Fig. 3d and Fig. 3e, respectively. More so, the latter pane with a top layer of only 1 nm thickness displays a distribution of relative hysteresis gap values that closely resemble the normal distribution. This indicates that the distribution is not likely to change noticeably if we were to add more samples to the study. Our results are summarized in Table 1, displaying  Fig. 3. Clearly, the triple layer with thinner upper HfO 2 layer is the better choice as gate insulator when preparing a memory storage device. More important, we show here that memory effects in a CNT FET can be controlled in ambient conditions, even without applying any kind of surface passivation layer on to the device.
To test the influence of surface chemistry (e.g. adhered H 2 O molecules) on the memory effects seen, 12 samples with the thinner triple-layer ALD dielectric were measured in a chamber with dry nitrogen gas flow, reducing the relative humidity to less than 1 %. The relative hysteresis gap was not affected for about half of the samples, while the other half saw a slight decrease. The changes in relative hysteresis gap were in all cases less than 10%. The ON and OFF states remained unaffected. It is therefore reasonable to assume that molecules adhered to the surface play a minor role in the memory effects seen. The fact that changes in memory effects follow changes in gate dielectric, with relatively narrow distributions in two cases, discredit the model that defects in the SWC-NTs are providing the charge traps responsible for the hysteresis. The reason for the differences seen between single layer dielectrics of SiO 2 , Al 2 O 3 and HfO 2 is difficult to discern, but may be related to differing charge trap densities, or even types of charge defects.
Turning our attention to the rapidly narrowing distribution in hysteresis gap when going from single layer HfO 2 to a triple-layered dielectric structure, the most significant difference in the surrounding of the CNT is the closely located interface between the HfO 2 and the TiO 2 layer. It is common knowledge that the interface between two different materials may carry defects or charge traps. An alternative explanation could be that as the top-layer of HfO 2 becomes thinner, its sur-face becomes rougher and hosts an increasing number of defects, e.g. oxygen vacancies. The defects may act as charge traps and cause the increased hysteresis. But here we would like to point out two opposing observations. First, surface defects are likely to interact with or be screened by adhered water molecules, which then would decrease the relative hysteresis gap in ambient conditions. We see the opposite trend, a slight decrease of the relative hysteresis gap in vacuum. Second, our AFM measurements show no quantitative difference in surface roughness between the samples with different layer thicknesses. Here should be added though that the AFM is working close to its limit of resolution, measuring roughesses on the order of 1 nm. While mobile charge traps also may be present within the dielectric, and could possibly be a major contributor to memory effects seen in the single layer dielectrics, it is reasonable to assume on the basis of these data that moving the lower interface of the upper HfO 2 layer closer to the CNT provides a layer of stationary charge traps at a well calibrated distance from the CNT. It is supported by the notion that a layer of stationary charge traps in the vicinity of the CNT will also screen the action from mobile charge carriers, thus creating a well defined device geometry with a narrow hysteresis gap distribution. We therefore conclude that the most probable dominating charge storage mechanism in the triple layer structure is due to stationary charge traps at the lower interface of the uppermost HfO 2 layer, which are filled and emptied by charge carriers in response to application of a negative or positive gate voltage.
In summary, we have investigated 94 SWCNT FETs with different gate insulators, giving us unprecedented statistics on the presence of hysteresis in their transfer characteristics. We find that by using a tree-layered gate dielectric consisting of HfO 2 -TiO 2 -HfO 2 , all SWCNT FETs display hysteresis with a narrow distribution of their relative hysteresis gaps, which narrows down further when the upper most layer is changed from 3 nm to 1 nm. The study shows that SWCNT FETs can be fabricated and operated in ambient conditions without any surface passivation, which points towards the dominant charge trapping mechanism being insensitive to H 2 O molecules on the surface. Such layered gate dielectric is of particular interest for memory applications, providing to our knowledge the first proven route to 100 % yield in single CNT-based memory elements. However, several challenges remain to be solved in order to make highly integrated CNT memory cells, such as positioning the CNTs with nm precision and providing each of them with a local, nanotube specific gate.

Methods
The samples were prepared by starting from a highly boron-doped Si wafer which acts as a backgate. The backgate was covered with an ALD layer of either Al 2 O 3 (nominal thickness: 20 nm), HfO 2 (20 nm), or HfO 2 -TiO 2 -HfO 2 (40-0.5-3 or 40-0.5-1 nm). All ALD depositions were done at Planar Systems Inc. (Espoo, Finland), using a Planar P400A ALD deposition tool. The idea motivating the triple-layer structure is to create, in a controlled way, charge traps in the close vicinity of the CNT FET [14]. The interface between two different ALD layers may serve that purpose. We also prepared reference samples with gate insulator of the more commonly used thermally grown SiO 2 (300 nm). On top of the gate insulator a matrix of alignment markers was deposited, using e-beam lithography and metallization of Pd with an adhesion layer of Ti. CNTs were then deposited in two different ways, depending on their origin. Our primary source was commercial SWCNTs produced by NanoCyl S.A. (Sambreville, BELGIUM), bought in the shape of black powder, which was suspended in a solvent by ultra-sonication. A few droplets of the nanotube suspension were then deposited onto the sample. We also prepared, as a reference, 11 samples with SWCNTs from the Hot Wire Generator reactor on to substrates with the HfO 2 -TiO 2 -HfO 2 (40-0.5-1 nm) triple-layer. The Hot Wire Generator reactor is based on the aerosol (floating catalyst) synthesis of CNTs. Iron particles and carbon monoxide were utilized as the catalyst and the carbon source, respectively [21]. Individual CNTs were filtered out from the bundled tubes in the gas phase as described in [22] and deposited onto the sample surface at room temperature using thermophoretic precipitator [23]. In both methods CNTs were left at random places on the surface. Their locations were then mapped in relation to the matrix of alignment markers, using an AFM. Finally, electrodes of Pd were deposited onto the ends of the CNTs, with the help of e-beam lithography and subsequent metallization.
All measurements in this study were carried out at room temperature in an electrically shielded room, either under ambient conditions or in a chamber under dry nitrogen gas flow, which reduced the relative humidity to below 1% (below the resolution of our humidity sensor). Two-terminal measurements were performed, with the substrate acting as a backgate. DC measurements were used with the applied voltage given by a home-built voltage distribution box, powered by batteries and computer controlled via a data acquisition card, while measuring the current response through the nanotube. I-V characteristics and conductance response to an applied backgate voltage was collected from all samples. The samples with linear I-V characteristics and its conductance not sensitive to an applied backgate voltage were considered to have metallic CNTs. The study includes in total 94 semiconducting SWCNTs, featuring a clear backgate dependence.
These comprise about 82 % of all the samples made, which is somewhat higher than the expected 67 % for randomly picked CNT chiralities. Surprisingly, eight of the eleven devices made with SWCNTs from the Hot Wire Generator reactor show clear metallic behavior. Of the three remaining semiconducting SWCNTs, one had a malfunctioning back-gate, leaving only two CNT FETs of this kind added to the study. As shown in Fig. 3, these two CNT FETs do not deviate notably in performance compared to the other 25 devices with the same gate dielectric.
An often problematic part in CNT sample processing is to achieve low contact resistance between electrode and nanotube [24]. As an upper limit measure of the contact resistances in our devices, we sampled the total two-terminal resistances of the metallic CNTs. These were found to be in the range of 14-160 kΩ, which is close to the theoretical minimum resistance for SWC-NTs of 1/2G 0 = h/4e 2 ≈ 6.45kΩ. Here G 0 is the quantum unit of conductance, e is the charge of the electron and h is Planck's constant.
The memory devices included in this study have so far been subjected to slow switching frequencies of up to 10 Hz, using typically gate voltages of ± 3 V for ALD gated samples and ± 10 V for CNT FETs with gate dielectric of SiO 2 . Some of the devices show charge stability with no change in ON or OFF state for several days, while others have a retention time of down to a few hours. Durability has been tested for some of the CNT memories, with no significant change in ON/OFF states after switching 10 4 times or more. We are currently studying these aspects, but would like to add they should not be compared to single device characteristics of state-of-the-art commercial memories before the gate configuration is changed from a backgate to a local gate for each CNT, which may significantly improve device characteristics. That work is also in progress.