Single spin universal Boolean logic

Recent advances in manipulating single electron spins in quantum dots have brought us close to the realization of classical logic gates based on representing binary bits in spin polarizations of single electrons. Here, we show that a linear array of three quantum dots, each containing a single spin polarized electron, and with nearest neighbor exchange coupling, acts as the universal NAND gate. The energy dissipated during switching this gate is the Landauer-Shannon limit of kTln(1/p) [T = ambient temperature and p = intrinsic gate error probability]. With present day technology, p = 1E-9 is achievable above 1 K temperature. Even with this small intrinsic error probability, the energy dissipated during switching the NAND gate is only ~ 21 kT, while today's nanoscale transistors dissipate about 40,000 - 50,000 kT when they switch.


Introduction
The primary threat to continued downscaling of electronic devices envisioned in Moore's law 1 is excessive energy dissipation that takes place when a device switches between logic levels. If electronic devices are shrunk relentlessly without concomitantly reducing energy dissipation, thermal management on a chip will ultimately fail resulting in chip meltdown. Conventional devices have a fundamental drawback in this regard since they typically encode digital information using charge (or voltage/current levels determined by charge). Charge is a scalar quantity that has only a magnitude. Therefore, binary logic bits 0 and 1 must be demarcated by a difference in the magnitude of the charge representing the bit.
Switching between bits would mandate changing this magnitude, which invariably involves current flow and associated power dissipation of I 2 R (I=current and R=resistance in the path of the current). There is no way to avoid this dissipation.
Spin, on the other hand, is a pseudo vector that has both a magnitude and a polarization. The polarization can be made bistable by placing the electron in a dc magnetic field, so that only two polarizationsparallel and anti-parallel to the field -are stable. They can encode the bits 0 and 1. Switching between them requires simply flipping the spin without physically moving the charge in space and causing a current flow. This can reduce energy dissipation significantly.
In this paper, we first show rigorously how a universal Boolean logic gate (the NAND gate) can be realized based on this idea. Although the basic idea was proposed many years ago 2 , this is the first rigorous quantum mechanical calculation establishing the gate's truth table. Next, we present an estimate of the energy dissipated during switching this gate. The energy dissipated is found to be the minimum allowed by the laws of thermodynamics, namely the Landauer-Shannon limit 3 .

A single spin Boolean NAND gate.
Consider a linear array of three single electron containing quantum dots shown in Fig. 1. The quantum mechanical wavefunctions of electrons in nearest neighbor dots overlap in space causing exchange coupling between them. A weak global magnetic field makes the spin polarization in each dot bistable, because the polarization can be either parallel or anti-parallel to the global field. These two stable polarizations encode the classical binary bits 1 and 0, respectively.
The two peripheral dots A and C host the two input bits and the central dot B hosts the output bit. Input data are provided by orienting the spins in A and C in the desired directions (parallel or anti-parallel to the global magnetic field) with local magnetic fields generated by local inductors, as in magnetic random access memory (MRAM) chips. These inductors are wrapped around the input dots and might be realized with carbon nanotubes. We will show that when the system is in the ground state, the output spin polarization in dot B always conforms to the NAND function of the input spins in dots A and according to the truth table of a NAND gate:  Fig. 1(e) for the sake of clarity.

Theory
If the charging energy (intradot Coulomb repulsion) within each dot is sufficiently strong, then at halffilling (1 electron per dot), then the Hubbard Hamiltonian representing the 3-spin array in Fig. 1 where the σ -s are Pauli spin matrices. We assume that the lowest orbital states in the quantum dots are occupied. If excitation to the higher orbital states is not accompanied by spin flip, then the higher states do not matter in the ensuing analysis, since logic bits are encoded in the spin and not the orbital quantum number. Even if the rate of transition between orbital states is moderately high 9 , the rate of spin flip is still very small 10 , indicating that most excitations are not accompanied by spin flips. Consequently, the excited states are not important in our context and we do not have to consider them. We adopt the convention that the direction of the local and the global magnetic fields is the z-direction. The last two terms in the above equation account for the Zeeman energies associated with these fields. The first two terms account for exchange interaction between nearest neighbors (the angular brackets denote summation over nearest neighbors). We will assume the isotropic case when ij where J is the exchange energy, which is non-zero if the wavefunctions in dots i and j overlap in space.
The spins in the quantum dots are polarized in either the +z or -z direction (because of the global and local magnetic fields), which we designate as "upspin" ( ) and "downspin" ( ) states, respectively. We will assume that the upspin state (aligned anti-parallel to the global magnetic field) encodes bit 0 and downspin state (parallel to the global field) encodes bit 1. where the φ m,n are the 3-electron basis states enumerated above.
In the above matrix, 2Z is the Zeeman splitting energy in any dot caused by the global magnetic field, while 2h A and 2h C are Zeeman splitting energies in the input dots due to the local magnetic fields that write input data. If the local magnetic field is in the same direction as the global field and writes bit 1, then the corresponding h is positive; otherwise, it is negative. The quantity J is always positive (to guarantee that the singlet state composed of two coupled electrons has lower energy than the triplet state, as it should be).
In the Appendix, we tabulate the 8 eigenenergies E n (n = 1....8) and the corresponding eigenstates In the Appendix, we also show that if we apply sufficiently strong local magnetic fields to orient the spins in input dots A and C to the desired directions (i.e. |h A |=|h C |=h >> J, Z), and allow the system to relax to the ground state, then the spin polarization in the output dot B will always represent the result of NAND Boolean logic operation on the input bits. In other words, the 3-dot system realizes a NAND gate whenever it is in the ground state. Ground state relaxation is the central idea in some types of artificial neural networks and similar ideas are found in other contexts 11 as well. Of course, applying local magnetic fields exclusively to specific quantum dots that host input bits is difficult and requires sophisticated shielding techniques and extreme spatial resolution. We visualize using spin polarized scanning tunneling microscope tips for this purpose, which can concentrate a magnetic field over a single quantum dot. A magnetic shield can be wrapped around each dot for further field containment. This is a difficult engineering challenge but not unachievable because of any fundamental physical laws.
Once the NAND gate is realized, we need only one other component to implement any arbitrary Boolean logic circuit. That element is a "spin wire" which will ferry spin signal unidirectionally from one gate to another. A spin wire consists of a linear array of quantum dots with clock pads between them [ Fig. 1(e)].
When the clock signal at a given pad is high, the potential barrier between the two flanking dots is lowered, and their resident electrons are exchange coupled. This renders their spins anti-parallel 12 .
Therefore, by sequentially clocking the barriers, we can replicate the spin bit in every other dot and transmit the spin signal along the wire unidirectionally 13 . A 3-phase clock is required for this purpose 13 .

Gate errors
It is the natural tendency of any physical system to relax to the ground state, which is the basis of the NAND operation. However, once a system relaxes to ground state, it need not stay there forever. If it gets out of the ground state, and it does because of noise and fluctuations 14 , it will produce wrong results and cause errors in computation. We will compute this error probability next.
Consider a system which is thermodynamically coupled to its environment that allows it to relax to the ground state. Once the system has attained equilibrium with the environment, the probability of finding it in any particular state is given by the Fermi-Dirac occupation probability. This probability is not unity for the ground state, implying that the system does not have to remain in the ground state in perpetuity.  We emphasize that T 1 is the spin relaxation time of a single electron in an isolated quantum dot that is uncoupled to any of its nearest neighbors. When relaxation to ground state takes place in the logic gates during computation, each electron is exchange coupled to its nearest neighbors. This relaxation is governed by the many-body relaxation of coupled spins. The single particle spin relaxation can be orders of magnitude slower than the many body spin relaxation. This is well known in the context of the transverse relaxation time T 2 16 . Therefore, the relaxation to ground state can occur in a time much shorter than T 1 . That means that the clock frequency is not limited by 1/T 1 , but can be much higher.
In ref. 13, we showed that the relaxation to ground state occurs when the clock signal is high and the nearest neighbors are coupled by exchange interaction. Therefore, the rate of relaxation to ground state is the many body rate 1/T 1 * which is much higher than the single particle rate 1/T 1 . When the clock signal is low, the system is in the standby state, and we would not like the spin to flip spontaneously during this time since that would cause an error. However, in the standby state, each electron is uncoupled to its neighbors and hence the spin flip rate is 1/T 1 << 1/T 1 * .
The rate 1/T 1 * is obviously the upper limit on the clock frequency, since otherwise the relaxation to ground state will not be complete before the clock signal changes. The extrinsic error probability will be then limited by p e = 1 -exp The intrinsic and extrinsic error probabilities are not related to each other and are independent quantities.
The net error probability that error correction schemes will have to contend with is the larger of p i and p e .
Modern error correction algorithms can handle net error probabilities as high as 3% 17 .

Energy dissipation during switching
The maximum energy dissipated during switching the NAND gate is the largest energy difference between any two of the four ground states corresponding to the four input combinations shown in Figs. 1(a) - Fig. 1(d). By considering all the four ground state energies (see Appendix), the largest energy difference between any two ground states is 2Z (corresponding to switching between the states in Figs. 1(a) and 1(b)), which we have just shown is kTln(1/p i ). Therefore, ideally, the maximum energy dissipated during switching is kTln(1/p i ). This is the well-known Landauer-Shannon limit 3 .
It is interesting to note that when we switch between some of the states, (e.g. between Fig. 1(b) and 1(c)), the energy dissipated is less than the Landauer-Shannon limit of kTln(1/p i ). This happens because of interactions between the spins (internal feedback) which make all 3 spins act in concert as a single entity.
A similar situation was addressed in ref. [18].
In the energy calculation, we purposely ignored the energy cost of generating the local magnetic fields and the energy dissipated in the clock pads. These costs can be made arbitrarily small, certainly much smaller than kTln(1/p i ), by adopting adiabatic schemes 19 .

Temperature of operation
The requirement J=Z=(1/2)kTln(1/p i ) will also determine the maximum temperature at which we can The local magnetic fields needed to write input bits in dots A and C need to be approximately 10 times larger than the global field (see Appendix). Therefore, the local field strengths need not exceed 0.4 Tesla, which should be within reach of magnetic random access memory technology 23 .
Finally, one concern is that using a material with giant g-factor may adversely affect the spin flip time.
But it will affect T 1 and T 1 * almost equally. Therefore, the extrinsic error probability p e = T 1 * /T 1 , will not change by much. If T 1 * goes down, then the maximum clock frequency 1/T 1 * will increase commensurately.

Conclusion
We have shown that a simple linear array of 3 spins in quantum dots, with nearest neighbor exchange coupling, realizes the universal classical Boolean NAND gate, if placed in a global dc magnetic field and allowed to relax to the thermodynamic ground state. Recent advances in single spin electronics, allowing control over single electrons [24][25][26] , has brought us close to the realization of such computing elements. The energy dissipated during switching between states is kTln(1/p i ). With p i as low as 10 -9 , this energy is ~21 kT which is much better than the 40,000 -50,000 kT dissipated in present day transistor based gates 27 . A serious drawback however is that the temperature of operation is ~ 1 K due to present constraints in quantum dot technology. At this temperature, the energy dissipated during switching is ~ 3×10 -22 Joules if p i = 10 -9 . This can extend Moore's law easily into the next few decades. We also point out that realization of these gates does not require phase coherence of spin, which is difficult to preserve over long times, even at low temperatures. This paradigm is completely classical unlike quantum computing; therefore, these gates are considerably easier to implement than quantum gates.

APPENDIX_________________________________________________________________
We tabulate below the 8 many-body eigenenergies (E n ) and the eigenstates ( n ψ ) of the 3-spin array for the four cases corresponding to the four input combinations shown in Figs. 1(a) -1(d).
Case I: h A = h C = h>0: This is the case when the input bits are [1 1] and the situation corresponds to Fig.   1(a) [the first entry in the truth table of the NAND gate]. The 8 eigenenergies E n and eigenstates n ψ are:  Note that the eigenenergies E n depend on Z, but the eigenstates n ψ do not. In Table A1, the eigenenergies are arranged in ascending order (i.e. the first entry is the ground state and the last entry is the highest excited state), provided h >> J and J > Z/2. The last inequality ensures that which guarantees that the first excited state is higher in energy than the ground state. We now address why we need h >> J.
Note that the ground state wavefunction is the entangled state 11 Fig. 1(a). Therefore, the desired ground state is the unentangled state In other words, the 3-spin configuration in Fig. 1(a) will become the ground state if we make h >> J. In that case, whenever we apply the inputs [1,1] to the input dots A and C and let the system relax thermodynamically to the ground state (by emitting phonons, etc.), it will reach the state in Fig. 1(a) where the output bit (in dot B) will be [0] and we will have realized the first entry in the truth table of the NAND gate.

Case II: h A = h C = -h<0:
This is the case when the input bits are [0 0] and the situation corresponds to Fig. 1(b). In this case, the eigenenergies and eigenstates are obtained by replacing the quantity h in Table   S1 with -h.  whereas the desired state shown in Fig. 1(b) Fig. 1(b), and we will have realized the second entry in the truth table of the NAND gate. All we need for this to happen is h >> J.
Case III: -h A = h C = h>0: This is the case when the input bits are [0 1] and the situation corresponds to Fig. 1(c). In this case, the eigenenergies and eigenstates are more complicated and given in Table A3.  Fig. 1(d), and we will have realized the fourth and final entry in the truth table of the NAND gate.
In conclusion, what we have shown here is that if we place a 3-spin array with nearest neighbor exchange coupling in a dc magnetic field, and align the spins in the two peripheral dots (designated as input ports) with sufficiently strong local magnetic field B local such that the Zeeman splitting in the inputs dots 2h = gμ B B B local is much larger than 2J, then the spin polarization in the output (central) dot will always conform to the NAND function of the two inputs, once the array relaxes to the thermodynamic ground state. This realizes a "single-spin-NAND-gate".
One final issue that needs to be resolved is the following. In order for the NAND gate to work correctly, we need that h >> J. How large should the ratio h/J be? Note from Table A1 that the ground state approaches the unentangled state ↓↑↓ if Therefore, in Case I, we need h/J ≥ 10 to make the ground state nearly indistinguishable from the unentangled state ↓↑↓ .
In Figs. A2, A3 and A4, we plot the equivalent quantities for Cases II, III and IV, respectively. Once again, we find that ensuring h/J ≥ 10 is sufficient. Therefore, in all cases, it is adequate to have the strengths of the local magnetic fields writing inputs bits no more than 10 times stronger than the global magnetic field. If the global magnetic flux density is 0.04 Tesla, it is sufficient to have the local magnetic flux density 0.4 Tesla.