New barrier layer design for the fabrication of gallium nitride-metal-insulator-semiconductor-high electron mobility transistor normally-off transistor

This paper reports on the fabrication of an enhancement-mode AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistor with a new barrier epi-layer design based on double Al0.2Ga0.8N barrier layers separated by a thin GaN layer. Normally-off transistors are achieved with good performances by using digital etching (DE) process for the gate recess. The gate insulator is deposited using two technics: plasma enhance chemical vapour deposition (sample A) and atomic layer deposition (sample B). Indeed, the two devices present a threshold voltage (V th) of +0.4 V and +0.9 V respectively with ΔV th about 0.1 V and 0.05 V extracted from the hysteresis gate capacitance measurement, a gate leakage current below 2 × 10−10 A mm−1, an I ON/I OFF about 108 and a breakdown voltage of V BR = 150 V and 200 V respectively with 1.5 µm thick buffer layer. All these results are indicating a good barrier surface quality after the gate recess. The DE mechanism is based on chemical dissolution of oxides formed during the first step of DE. Consequently, the process is relatively soft with very low induced physical damages at the barrier layer surface.


Introduction
Gallium nitride (GaN) is one of the best candidate for high frequency and high power applications [1,2] thanks  [25] to its outstanding material properties (high breakdown voltage, high electron velocity and good thermal conductivity) and advances in electrical modelling [3,4]. The standard AlGaN/GaN high electron mobility transistor (HEMT) device is a depletion-mode (D-mode) transistor. However, researchers are encouraged to develop enhancement-mode (E-mode) AlGaN/GaN HEMT due to its several applications in analog, digital [5] and automotive industry [6]: for example, it provides essential fail-safe operation and simple circuit architecture for power switch applications [7] as well as allowing simple design for RF and microwave circuits [8].
To have an E-mode device, several ways are used to shift the V th towards the positive value such as, fluorine implantation [9][10][11], introduction of additional layers on top of the barrier layer [12][13][14][15][16][17][18][19], fin-structure [20,21] and gate recess [22][23][24][25] (table 1). One of the most common methods for the last approach is the gate recess using plasma which induces some degradation at the surface of the barrier layer [26]. To overcome this problem, the gate recess by digital etching (DE) process is used to minimize the degradation at the barrier layer surface [27,28]. Self-limiting nature of the DE process allows an accurate control of the etching.
In this work, a new HEMT heterostructure (figure 1) based on a double AlGaN barrier layer is proposed to obtain E-mode devices. The goal of the top AlGaN barrier (etched by DE process) is to increase the charge density in the access region to reduce the serial resistance while keeping the charge density underneath the gate low enough to achieve a normally-off transistor. Thanks to the decorrelation in the optimization process between the internal part underneath the gate and the external part in the access region of the device, the Normally-off transistor is exhibiting good electrical performances.

Device fabrication
The HEMT epitaxial structure grown in CRHEA-France on silicon (111) substrate used in this study is shown in figure 1. The epi-structure starts with 1.5 µm GaN buffer layer followed by 5 nm Al 0.2 Ga 0.8 N layer, 2 nm GaN layer and finally 10 nm Al 0.2 Ga 0.8 N layer. At the end, the epi-structure is capped with 5 nm in situ SiN. The first 5 nm Al 0.2 Ga 0.8 N layer has been  defined after achieving a calibration design of experiment that ends up with an epi-structure which is totally depleted from free carriers.
A Schrödinger-Poisson simulation (figure 2) of the epitaxial structure has been performed to show the band gap engineering optimization process. This simulation takes only in account the four top layers of the heterostructure (AlGaN-GaN-AlGaN-GaN).
When the gate recess reaches the thin GaN layer (2 nm), the effective Schottky barrier height (SBH) of the gate electrode is about 1.3 eV taking advantage of the conduction band discontinuity (∆E c ) between GaN and AlGaN. The effective barrier height corresponds to the maximum band diagram energy that the electrons should overcome to go from the metal to the channel. The conduction band in the channel is then liftedup over the Fermi level, which leads to a low charge density in the channel. The device pinch-off voltage is then shifted towards the positive values. After removing the entire thin GaN layer, the V th will shift back towards the negative values (blue curve). In order to keep the E-mode behaviour of the device with the present epi-layer structure, etching must be stopped before removing the 2 nm GaN layer, otherwise the device will become again D-mode or at least less E-mode.
The HEMT fabrication process performed at LN2-Canada laboratory starts with Ti/Al/Ni/Au ohmic contacts deposition using E-beam evaporation followed by a rapid thermal annealing then the device isolation is performed by N + ion multiple implantations. Afterwards, a 50 nm SiO 2 layer is deposited by plasma enhance chemical vapour deposition (PECVD) and used as a physical mask for the DE process. This oxide layer and the in situ SiN are etched by SF 6 plasma in order to define the gate area.
The next step is the DE of the top 10 nm AlGaN barrier layer. This process is based on an oxidation of the AlGaN by soft O 2 plasma (RF power-100 W/Pressure-300 mT/2 min) followed by wet etching of the oxide layer using HCl:H 2 O (1:10) solution during 1 min [28].
Electrical measurements have been performed as well as atomic force microscopy (AFM) observations on transistor pattern with source-drain distance of 10 µm and 1.5 µm opening in SiO 2 for the gate recess. Figure 3 shows the current measured on this pattern at V DS = 10 V versus the DE iteration number. Using the AFM, we have extracted an etch rate of 0.5 nm per DE cycle.
On the plot shown in figure 3, we can observe two main regions. The first region (up to 20 cycles) corresponds to the etching of the top AlGaN barrier layer. In this region, the current decreases as the DE cycle number is increasing. In the second region (over 20 cycles); where the etching reaches the 2 nm GaN, the current is relatively stabilised. We stopped the DE after 22 cycles corresponding to 50% etching of the 2 nm GaN layer.
We can conclude that the 2 nm GaN layer inserted in the barrier layer is an important element in the epi-structure which is mandatory to: In other words, our barrier layer GaN/AlGaN is 6 nm thick, if we have this barrier layer composed only with 6 nm AlGaN, the pinch-off voltage will be negative because we will lose the benefit of these 2 nm GaN. • Monitor the recess etching to obtain a well-controlled process. Indeed, when the recess reaches the GaN layer, the drain-source current saturates, and we can stop our recessing. This is an advantage to get a stable, reproducible and robust process.
Therefore, the 2 nm GaN layer is mandatory in the epistructure and represents a big part of the novelty of this new band gap engineering approach to fabricate a normally-off GaN-HEMT device.
After the gate recess process, the sample is pretreated with a KOH solution, followed by a HCl solution [28]. The gate process is one of the most critical part of the HEMT fabrication process. We decided to use two different process for the gate oxide deposition. On the first sample (sample A), a thin 12 nm SiO 2 gate oxide layer is deposited by PECVD. On a second sample (sample B), a thin 12 nm Al 2 O 3 layer is deposited by atomic layer deposition. The HEMT heterostructure is the same on both samples. This step is followed by the gate metallization (Ti/Au/Ni) deposited by E-beam evaporation. Afterwards, a SiO 2 passivation (800 nm) layer is deposited by PECVD followed by a thick interconnexion metal stack Ti/Au/Ni for transistor measurement pad. Figure 4 shows a scanning electron mobility (SEM) image of a fabricated Emode device. Transmission line measurements reveal a contact resistance R c of 1.28 Ω mm and a sheet resistance R sh of 788 Ω mm. It is important to notice that no work has been done to optimize the ohmic contact resistance. The main goal of this paper is the demonstration of this new barrier layer engineering approach.

Measurements and results
The To shift the pinch-off voltage towards the positive values the aluminium content of the AlGaN at the bottom of the barrier layer can be reduced below 20% to decrease the electrons density underneath the gate electrode. At the same time, we should increase the Al content in the top AlGaN layer to reduce the serial resistance of the device.
In figure 5, we observe that the gate leakage current measured at V DS = 10 V is below 200 pA mm −1 for both devices. The off-state drain leakage current of approximately 1 nA mm −1 and 10 nA mm −1 gives an I ON /I OFF ratio around 2 × 10 8 and 0.17 × 10 8 for samples A and B respectively. The low ∆V th as well as low gate leakage currents measured on samples A and B indicate that there is no significant damage induced by the DE process to the barrier layer surface.
To further validation of this observation, C(V) measurements (figure 6) have been performed at 100 kHz on an oversized diode. A low hysteresis is observable on the C(V) measurements as well. We can state here that the DE minimizes damages induced by the gate recess despite the important number of DE cycles.
A breakdown voltage of 150 V and 200 V at V GS = 0 V has been measured on sample A and sample B respectively. An onstate resistance (R ON ) of 22 Ω mm and 16 Ω mm of sample A and sample B respectively are extracted from the DC I D (V DS ) characteristics (figure 7).

Conclusion
This paper introduces a new band gap engineering approach of the barrier layer of AlGaN/GaN HEMT heterostructure to fabricate E-mode devices. Thanks to DE process, these devices could be co-integrated with normally-on devices within advanced circuits. The obtained results validate this new approach and we have measured a V th over 0 V. The ∆V th of 0.1 V (sample A) and 0.05 V (sample B) and the low gate leakage current prove the low damage induced by the DE process despite the large number of etching cycles. The future work will consist in further decreasing the aluminum content in the bottom AlGaN barrier layer to reach V th over 1 V.