High-performance SiGe HBTs for next generation BiCMOS technology

This paper addresses fabrication aspects of SiGe heterojunction bipolar transistors which record high-speed performance. We previously reported fT values of 505 GHz, fMAX values of 720 GHz, and ring oscillator gate delays of 1.34 ps for these transistors. The impact of critical process steps on radio frequency performance is discussed. This includes millisecond annealing for enhanced dopant activation and optimization of the epitaxial growth process of the base layer. It is demonstrated that the use of a disilane precursor instead of silane can result in reduced base resistance and favorable device scalability.


Introduction
Today, SiGe heterojunction bipolar transistors (HBT) in BiCMOS technology environment are widely used for applications like automotive radar, high-speed wireless and optical data links, and high-precision analog circuits. While future 5 G communication standards at frequencies up to 40 GHz are likely to be addressed by advanced CMOS technologies, SiGe BiCMOS technologies are a strong contenders for the required high data rate wireless or fiber optic back-haul. Moreover, the advent of highly-integrated mm and sub-mm wave circuits could pave the way to widespread use of these bands for applications such as high-resolution sensors in robotics, imaging and sensing in medicine, industry, and science, or short-range data transmission. These applications take advantage of an ongoing increase of the radio-frequency (RF) performance of SiGe BiCMOS technologies. Recent advancements in technology, modeling, and mm-wave circuit applications of SiGe HBTs achieved in the European research project DOTSEVEN are reviewed in [1].
BiCMOS technologies with SiGe HBTs featuring transit frequencies f T up to 320 GHz and maximum oscillation frequencies f MAX up to 400 GHz have reached industrial production level today [2][3][4][5][6]. Recent research results revealed a significant potential for further enhancement of the RF performance. SiGe HBTs with peak f T values of 505 GHz and peak f MAX values of 720 GHz were demonstrated on the research level [7]. These devices represent the current state of the art for SiGe HBTs. The record HBTs were fabricated in a bipolar-only process flow. The integration of HBTs with a similar performance in industrial BiCMOS technology platforms is currently addressed in the European project TAR-ANTO launched in 2017. With this new HBT generation it becomes conceivable to extend fundamental operating frequencies of integrated silicon circuits up to 300 GHz which is out of reach with existing technologies. The available wide absolute band width at these frequencies will enable, e.g., wireless data-rates in the order of tens of gigabits per second. High-precision radar and imaging systems can take advantage of the corresponding reduction of the carrier wave length. First implementations of such systems in experimental SiGe HBT technologies are reviewed in [1].
This paper addresses advances in device fabrication technology and device scaling that facilitated the remarkable improvement of RF performance. The impact of device geometries, specific material characteristics, and process integration aspects on device performance is discussed in section 2 for three HBT generations. The characteristics of the record-performance HBT of [7] are compared to data for HBTs of IHP's 130 nm BiCMOS technologies SG13S [8] and SG13G2 [9]. Individual process improvements that led to the demonstration of HBTs with 700 GHz f MAX are discussed in section 3. Section 4 addresses the impact of using the higher order precursor gas disilane instead of silane for the epitaxial growth of the base layer stack. Consequences on scalability and device performance are discussed. Figures 1 and 2 show the cutoff frequencies f T and f MAX as function of the collector current for three HBT generations. The fabrication processes of all three HBT generations are based on the 130 nm BiCMOS technology SG13S of IHP [8] featuring non-selective epitaxial growth of the SiGe base and elevated extrinsic base regions. The devices SG13G2 [9,10] and DOT7 [7] represent the technology advancements that were achieved based on the results of the two subsequent European research projects DOTFIVE and DOTSEVEN, respectively.

Progress in RF performance
The demonstrated peak f T /f MAX values of 505 GHz/ 720 GHz for the DOT7 device are the highest values reported for SiGe HBTs until now. The achieved performance enhancement was made possible by scaling vertical and lateral transistor dimensions and a series of process innovations which helped to reduce non-scaling contributions to device parasitics such as base and emitter resistances. A major feature size for HBT scaling is the emitter width. The emitter widths of the three investigated HBT generations SG13S, SG13G2, and DOT7 are 170 nm, 120 nm, and 105 nm, respectively. These values are still far from the scaling limit indicating room for performance improvement by further device scaling. Figures 1 and 2 indicate that the roll-off of f T and f MAX is shifted to higher current densities for the advanced technology generations. This is due to an enhanced dopant concentration in the collector region which suppresses the basepush-out effect. As a consequence, peak values of f T and f MAX shift to higher current densities for the advanced technology generations. However, it can be seen also that the advanced technologies provide significantly higher values of f T and f MAX than previous generations for a given collector current density. The higher f T and f MAX values correspond to higher current gain and power gain for transistor operation at a given application frequency thus enhancing the design margin for circuit applications at this frequency. The reduction of breakdown voltages due to the more aggressive doping profiles of the advanced transistor generations was moderate. The emitter-collector breakdown voltages BV ECo are 1.7 V for the SG13S device and 1.6 V for the SG13G2 and DOT7 devices.
The high-speed performance of a technology for switching operation can be efficiently benchmarked by ring oscillator gate delays. Gate delays of current-mode-logic (CML) ring oscillators are plotted in figure 3 as a function of collector current density for the three technology generations. The oscillators consist of 31 stages and a 1:16 frequency divider. Currents per stage were adjusted to a single-ended voltage swing of 300 mV at a supply voltage of −2.5 V. Figure 3 indicates that the improved f T and f MAX values of the advanced HBT generations are associated with significantly reduced gate delay times. The minimum gate delay of 1.34 ps for the DOT7 device represents the shortest gate delay demonstrated for a SiGe HBT technology so far [7]. Shorter gate delays have not been reported for any other integrated circuit technology.

Process optimization leading to 700 GHz f MAX
In this section, we review the process developments that facilitated the improved RF performance of the DOT7 device with respect to the SG13G2 reference process. The introduced process modifications addressed the reduction of device parasitics by reducing lateral device dimensions as well as by improving the control of the doping profile and the conductivity of critical device regions. Further details of this process optimization and results for individual device parameters are given in [1,7].
A schematic cross section of the HBT is given in figure 4. Basic features common to all three HBT generations are: (i) elevated extrinsic base regions self-aligned to the emitter window resulting in low base resistance, (ii) the formation of the HBT in a single active area without shallow trench isolation (STI) between emitter and collector contacting regions resulting in low collector resistance and small collector-substrate junction areas, and (iii) the absence of epitaxially-buried subcollectors and deep trenches in order to limit process complexity. Low-resistive collector wells isolated by standard STI are formed by ion implantation and rapid thermal annealing at the beginning of the HBT process module. Critical lateral dimensions such as the width of the emitter window (w E ), the width of the collector window (w C ), the width of the emitter poly-silicon (w EP ) and the width of the base-emitter spacer (d Sp ) are indicated. Details of the fabrication process and depth profiles of the doping and germanium concentrations of the advanced transistor generation can be found in chapters 1.3.1 and 1.4 of [1], respectively. The fabrication process includes the following four epitaxial steps.
(1) After patterning the oxide layer that forms the isolation between collector and extrinsic base link the opened collector window (w C ) is filled by selective epitaxy of un-doped Si. Subsequently, masked ion implantation is used to form the selectively-implanted collector (SIC) in the inner transistor region. The realization of high f MAX values requires high cutoff frequencies f T together with low base resistance R B and low base-collector capacitance C BC as indicated by the relation High f T values are facilitated by steep vertical doping profiles with short transit times through the base and the baseemitter and base-collector junctions combined with short charging times of the base-emitter and base-collector capacitances. Short transit times were addressed by an optimized SiGe base profile with an increased peak Ge concentration of 32% after deposition and 28% after the full process and by reduced thicknesses of the low-doped base-emitter and base collector transitions. An enhanced arsenic concentration and a reduced thickness of the emitter helped to reduce the emitter resistance. Consequently, low base-emitter and base-collector charging times could be maintained despite of the enhanced capacitances due to reduced junction widths. The broadening of the doping profiles was minimized by reducing the spike temperature for the final rapid thermal process. All three technology generations take advantage of the suppressed diffusion of boron due to carbon doping. The SiGe:C layers are doped with about 10 20 cm −3 carbon.
A further process modification that helped to reduce the excess resistances of base, emitter, and collector was the introduction of a millisecond flash-annealing step combined with a low-temperature back-end-of-line process with nickel silicide. Heating the wafer surface to temperatures close to the melting point at a millisecond time scale results in strongly enhanced dopant activation in heavily doped device regions without noticeable diffusion. The thermal budget after ms-  annealing has to be minimized in order to avoid dopant deactivation. This is supported by the replacement of the CoSi 2 process by a NiSi process with lower thermal budget. An additional reduction of R B was achieved by optimizing the process for the selective epitaxial growth and by increasing the dopant concentration of the elevated external base regions.
Scaling of lateral device dimensions is essential for simultaneous realization of low R B and low C BC that is required for high f MAX values. Figures 5(a) and (b) show transmission electron microscopy cross sections of SG13G2 and DOT7 HBTs, respectively. Critical lateral dimensions such as w E , w C , and w EP were reduced for the DOT7 devices (see figure 5) by reducing the corresponding lithographic dimensions. However, the possibilities for scaling the emitter window by lithographic measures are limited by the resolution of the used 248 nm DUV scanner. Therefore, w E could be scaled only moderately from 120 to 105 nm. The width of base-emitter spacers was reduced for the DOT7 device by modifying the corresponding etching and deposition processes. In addition, the width of the silicide blocking spacers at the outside of the emitter poly was reduced for the DOT7 device. Moreover, the process for the SIC that is formed before base epitaxy in the collector region below the emitter window was changed from a resist mask in SG13G2 to a hard mask process in DOT7 allowing for an improved control of the width and the doping concentration of the SIC region.
The described measures for lateral device scaling resulted in a significant reduction of R B and of contributions to C BC due to device edges for the DOT7 HBT in comparison to the SG13G2 device [7]. In combination with the enhanced f T of the DOT7 device, this resulted in the strong increase of f MAX shown in figure 2.

Study of two precursor gases for base epitaxy
A crucial step of the HBT fabrication is the epitaxy of the base layer stack. At the beginning of this epitaxial process, the wafers are covered with an about 80 nm thick oxide layer except for small collector windows of width w C . These collector windows were filled with Si up to the level of the oxide surface by a preceding selective epitaxial process. The following epitaxy of the Si/SiGe:C/Si base layer stack is performed in a differential manner, i.e., single-crystalline layers are grown on Si areas whereas poly-crystalline layers are grown on oxide areas. We have investigated two processes options for the epitaxy of the base layer stack which use silane and disilane as Si precursor gases, respectively. The replacement of silane by the higher order precursor disalane results in significantly higher growth rates. As a consequence, lower deposition temperatures are applicable for the disilane process.
Next, the two processes are analyzed with respect to their potential for lowest base resistance and device scaling. Figure 6 shows scanning electron microscopy (SEM) images of HBTs after deposition of the base layer stack using silanebased and disilane-based epitaxy. Silane epitaxy ( figure 6(a)) results in crystalline growth on Si areas and poly-crystalline growth on oxide areas. The grain structure of the poly-crystalline layer causes a rough transition line between the polycrystalline and single-crystalline areas as indicated in figure 6(a). Disilane epitaxy results in crystalline growth on Si areas and amorphous growth on oxide areas due to the reduced temperature (T<550°C). The amorphous layer is crystallized in a subsequent annealing step. Figure 6(b) shows an SEM top view after annealing. The resulting poly-crystalline layer is smoother than in the case of silane epitaxy. Moreover, a sharp transition line is formed between the poly and single-crystalline areas. For ideal transistor operation, the emitter window has to be securely positioned inside the unperturbed crystalline Si area within the collector window. The bumpy border line of the crystalline area in the case of silane epitaxy restricts the usable active transistor area in this case. A sharp straight border of the crystalline area as indicated in figure 6(b) is advantageous for minimum overlap of the collector window (w C ) over the emitter window (w E ) and thus supports the reduction of the contribution of the device edges to the base-collector capacitance.
Both epitaxy variants were evaluated in process splits of the HBT fabrication. Device cross sections for the two cases are shown in figures 5(b) and (c). Figure 5(b) shows a flat and smooth SiGe base layer (bright area below emitter window) within the active transistor area for the silane-based epitaxy. In contrast, the SiGe layer is waved in the device with disilane-based epitaxy and the thickness of the SiGe layer is varying across the active transistor area. Further optimization of the disilane-based process is needed to overcome this disadvantage.
The HBT with best RF performance [7] reviewed in section 2 was fabricated with silane epitaxy of the base layer stack. The process with disilane epitaxy resulted in lower peak f T and f MAX values for the most scaled device. This is attributed to a not yet fully optimized process in the case of disilane epitaxy. Nevertheless, the present experiment indicates a potential advantage of the disilane-based process for the realization of lowest base resistance values as discussed below.
In the following, we analyze electrical results for HBTs with three different emitter window widths fabricated with silane and disilane epitaxy of the base layer stack. Measured device parameters are summarized in table 1. The highest f T is obtained in both process splits for the device with the intermediate emitter width of 0.14 μm. Peak f T values are about 15 GHz lower for the smallest emitter width of 0.105 μm. This is attributed to the relative increase of non-scaling contribution from the device edges to delay times and to C BC and C BE . The disilan-based devices show about 50 GHz lower peak f T values than the corresponding silane-based devices. This is attributed to imperfectly matched Ge and B profiles of the two base layers. The disilane-based devices exhibit a lower Ge concentration and a higher base doping resulting in a lower transconductance at collector currents corresponding to peak f T . Peak f MAX values are highest for the devices with minimum emitter widths of 0.105 μm due to the reduction of R B with decreasing w E . Note that the devices analyzed here show somewhat lower f MAX values than the record device discussed in section 2 due to a more relaxed device layout with slightly larger w C and w EP .
It is remarkable that the HBTs with disilane epitaxy show significantly higher f MAX than the devices with silane epitaxy despite of about 50 GHz lower f T values. The higher f MAX values of the disilane devices are mainly caused by lower values of R B and to a smaller extend by lower C BC (see table 1). The base resistance R B is about 3 Ω lower for the devices with disilane epitaxy for all three emitter geometries. This cannot be attributed to the 14% lower intrinsic base sheet resistance R sbi alone but also to a lower external base resistance R Bx in the case of disilane epitaxy. Contributions to R Bx that are relevant here include the contact resistance between silizide an external base poly-silicon, the sheet resistance of the external base poly-silicon layer, and the contact resistance between external base poly-silicon and the single-crystalline base region. The silane and disilane processes resulted in the  same low sheet resistance of the un-silizided external base poly-silicon layer R s (BP) (table 1). The lower external base resistance R Bx of the disilane process results most likely from a lower resistance between the internal base and the external base poly-silicon at the edge of the collector window due to favorable structural properties in this case.
In conclusion, the use of disilane instead of silane as precursor gas for the epitaxy of the base layer stack opens up attractive additional degrees of freedom for device optimization. This concerns the morphology of the base layer stack which is favorable for device scaling as well as the potential for reduction of the base resistance. However, further optimization of the disilane-based process is required for the realization of flat and homogeneous SiGe layers down to smallest collector windows.

Summary
The fabrication of a new generation of high-performance SiGe HBTs with peak f T /f MAX values of 505 GHz/720 GHz and CML ring oscillator gate delays of 1.34 ps has been reviewed. The integration of such HBTs in an RF BiCMOS technology platform will significantly enhance its capability for mm-wave and THz applications. A route to further enhancement of the RF performance of SiGe HBTs is scaling of vertical and lateral device dimensions. One of the crucial process steps that define the scaling capability of the technology is the epitaxial growth of the SiGe base layer stack. It has been demonstrated here that the use of a disilane precursor instead of silane can result in reduced base resistance and favorable device scalability.