Single carrier trapping and de-trapping in scaled silicon complementary metal-oxide-semiconductor field-effect transistors at low temperatures

The scaling of Silicon (Si) technology is approaching the physical limit, where various quantum effects such as direct tunnelling and quantum confinement are observed, even at room temperatures. We have measured standard complementary metal-oxide-semiconductor field-effect-transistors (CMOSFETs) with wide and short channels at low temperatures to observe single electron/hole characteristics due to local structural disturbances such as roughness and defects. In fact, we observed Coulomb blockades in sub-threshold regimes of both p-type and n-type Si CMOSFETs, showing the presence of quantum dots in the channels. The stability diagrams for the Coulomb blockade were explained by the potential minima due to poly-Si grains. We have also observed sharp current peaks at narrow bias windows at the edges of the Coulomb diamonds, showing resonant tunnelling of single carriers through charge traps.


Introduction
The Silicon (Si) industry is seeking a new disruptive application in quantum technologies by using the platform of the existing infrastructure to fabricate scaled complementarymetal-oxide-semiconductor field-effect-transistors (CMOS-FETs). According to the International Technology Roadmap for Semiconductors 2.0 (ITRS 2.0) [1,2], which was issued in 2015 to replace the previous ITRS, the single electron transistor (SET) is considered to be a strong candidate for RFmixers [1,3,4], which is an important part of the RF front end. SETs are based on sequential single electron tunnelling [5] through two tunnelling barriers and a quantum dot with a small self-capacitor [6,7]. By changing the bias condition, the single electron sequential tunnelling is either unblocked or blocked, and SETs are controlled between on and off states, accordingly [8].
In the early stage of the research, scientists used metal [6,9] or a III-V semiconductor [10,11] as materials to study the characteristics of SETs and single electron phenomena. From the manufacturing point of view, Silicon (Si) SETs have some advantages due to their compatibility with CMOS fabrication technology [12]. Si-based SETs have already been demonstrated [13][14][15]. However, we must design complicated device structures with quantum confinement using dedicated processes, such as nanowire-defined dots [16], top gates [17], and side gates [18], which increases the complexity of fabrication. Besides complicated structures, the feature size must be comparable to or smaller than the thermal de Broglie length of single electrons to maintain a larger charging energy than thermal energy [19]. For standard CMOSFETs, the fabrication processes are well established, and the minimum feature size of CMOSFETs were as small as 14 nm [20] in 2014, which is already smaller than the thermal de Broglie length of 17 nm for electrons in Si at 300 K. Therefore, we should observe various quantum mechanical effects in conventional CMOSFETs. For example, random telegraph noise based on single electron trapping is a serious issue to secure reliabilities [21][22][23][24]. The purpose of this work is to investigate and establish the relationship between scaled Si CMOSFETs and Si SETs. Previously, the SET characteristics of Si nanowire FinFETs on SOI were observed at room temperatures [25,26], and low temperatures [27][28][29]. But, the single electron phenomena in conventional CMOSFETs based on bulk Si at low temperatures has not been fully investigated.

Experiments
The MOSFETs were fabricated by using a standard 65 nm technology node. The wide channel width of 10 μmwas chosen to increase the chances of observing single carrier trapping and de-trapping phenomena. The channel length was 55 nm/75 nm for pMOSFET/nMOSFET, respectively. The gate electrode was made of doped poly-crystalline silicon (poly-Si). The gate dielectric material was SiON with the Equivalent Oxide Thickness (EOT), t ox , of 2.4 nm. The value of the current at each bias was obtained by averaging over 10 5 data points each with a duration of 2 μs.

Results
The drain current (I d ) on the gate bias (V g ) characteristics of the two MOSFETs were measured at 300 K and 5 K respectively, as shown in figure 1, at the drain bias (V d ) of m50 mV.
The threshold voltages were −0.45 V/0.47 V at 300 K and −0.60 V/0.62 V at 5 K, for pMOSFET/nMOSFET, respectively (figure 1). The on-currents were larger for both pMOSFET and nMOSFET at 5K, because of the increase in mobility [30] and the increase of the saturation velocity [31]. The sub-threshold slopes were 14.9 mV/decade for pMOS-FET and 5.7 mV/decade for nMOSFET at 5 K, while they were 82.4 mV/decade for pMOSFET and 80.3 mV/decade for nMOSFET at 300 K. The off-current was below our detection limit (∼1pA) at 5 K. In the sub-threshold regime at 5 K, the channel resistance of both pMOSFET and nMOSFET were larger than 25.8 kΩ, which was a necessary condition of observing single-electron effects in SETs.
In fact, we observed typical SET characteristics at 5 K, as shown in figure 2.
The dependences of the I d −V d characteristics upon changing the V g implies the presence of a quantum dot in the channel of both devices. In figure 2(a), at V g of −0.528 V, I d of the pMOSFET was blocked in the V d range between −2.5 mV and 2.5 mV, while I d was not blocked at V g of −0.515 V. The similar Coulomb blockade behaviour was also observed in nMOSFET (figure 2(b)).
We measured I d in more detail by changing both V g and V d to check the single carrier trapping and de-trapping characteristics, as shown in the two-dimensional (2D) contour plot of I d ( figure 3). Several Coulomb diamonds were found in pMOSFET while only one Coulomb diamond was found in nMOSFET. Different Coulomb diamonds, which corresponded to different hole/electron states in a quantum dot, are marked as H0, H1, H2, H3 in figure 3(a) and E0, E1 in figure 3(b). In figure 3(a), the size of Coulomb diamond shrinks as | | V g was increased. It means that the coupling capacitance of quantum dot was changed as we changed V g .  This is a marked difference from the standard characteristics predicted by the conventional mesoscopic model of metallic tunnelling junction [32], in which all coupling capacitance in equivalent circuit are fixed. In figure 3(b), only one diamond was observed in the current map of nMOSFET. nMOSFET showed similar behaviour to p-MOSFET. The Coulomb diamond was observed when V g is between 0.47 V and 0.51 V. Above 0.51 V where the coupling resistance becomes smaller than quantum resistance, no diamond was observed.
When V g was larger than 0.47 V, the Coulomb diamond started to be observed. The diamond was not observed at 0.51 V where the coupling resistance became smaller than quantum resistance.
By comparing pMOSFET with nMOSFET (figure 2), we found that I d in nMOSFET was almost three times larger than that in pMOSFET. This may be explained by the mobility difference between the electrons and holes. The single electron/hole tunnelling event was only observable in corresponding sub-threshold region in the figure 1.
We also found that current peaks at the edges of Coulomb diamond for both devices. At narrow bias windows, which are marked as Hole Traps (HT1 and HT2) in figure 3(a), and Electron Traps (ET1, ET2) in figure 3(b), the current exhibited sharp peaks. The sharp current peaks were found at the edge of the Coulomb diamond blockade regime in both figures 3(a) and (b).

Discussion
The standard mesoscopic model was used to estimate parameters for SETs [33], as shown in figure 4(a). The carrier concentration was around 10 10 ∼ -10 cm 12 2 in Si twodimensional electron gas [34], which corresponds to 10∼100 nm electron-electron distance. This is on the same magnitude as the thermal de Broglie length of electron in Si at 5 K, 133 nm, and much larger than the Bohr radius in Si, 5.2 nm. Under this condition, the electrons trapped in the quantum dot can be treated as non-interactive electrons [35].
At the sub-threshold regime, the channel current is dominated by a single hole/electron transistor current. Therefore, the carrier concentration can be approximately estimated: In this weakly inverted condition, the impact of poly-Si depletion layer is negligible. However, the inversion layer thickness caused by quantum confinement near the SiON/Si interface cannot be neglected. The inversion layer thickness, t inv , is ∼2 nm [34,36,37]. Therefore, the total capacitive effective  thickness is Si where e ox is the dielectric constant of SiO 2 and e Si is the dielectric constant of Si. The coupling capacitances of each hole state shown in figure 3(a) were different. As | | V g was increased, more holes occupied the quantum dot. The gate coupling capacitance (C g ), source coupling capacitance (C s ), and drain coupling capacitances (C d ) to the quantum dot also increased. This implies that the coupling capacitances were connected to the inversion layer capacitance [38]. If | | V g increased after depletion layer reached its maximum width, the channel would start to be inverted. Therefore, both inversion layer capacitance per unit area [39], C inv , and oxide capacitance per unit area, C ox , contributed to C g as shown in where S was the area of the quantum dot. We can extract C g from the periodicity of Coulomb oscillations related to each Coulomb diamond, ΔV g , The extracted capacitances of pMOSFET and nMOSFET are shown in tables 1 and 2, respectively. In H3, V g was about −0.56 V, which was quite close to the threshold voltage of pMOSFET. The carrier density in H3 was much higher than that in H0, H1 and H2. Therefore, C inv in H3 would be the largest compared with H0, H1 and H2. Since C inv was the largest, here we assume that the dominant contribution to C g would be C ox in H3, and neglect the contribution of C inv . We can estimate the size of the quantum dot from C g in H3, ( ) C H3 g , based on this approximation. If we assume the quantum dot is a circle, we can caculate the diameter, d, The inversion layer capacitance in table 1 was extracted by assuming the diameter of the quantum dot in pMOSFET was 38.5 nm. The charging energy in H0 was 7.5 meV for pMOSFET, much smaller than the value reported in single dopant transistor [26,28,40], which is roughly 30 meV. Therefore, it is unlikely that the quantum dots were made of impurities in the channel due to the large size of the quantum dot. It implies that the quantum dots in both pMOSFET and nMOSFET come from physical structures defined by the surface roughness or poly-Si grains [41]. Grain boundaries of poly-Si cause remote surface roughness at poly-Si/SiON interface, as shown in figure 4(b). The remote surface roughness at poly-Si/SiON interface results in local variations of equivalent oxide thickness [42,43]. This forms a dip of surface potential near the interface of grain boundary area, and single carriers would be confined near the peak region. The dimension of poly-Si grains can be around 50 nm [44], which is comparable with the size of the quantum dot that we estimated from pMOSFET. If poly-Si grains were responsible for this Coulomb blockade phenomenon, we should only be able to observe SET characteristics if the channel length is comparable with the size of poly-Si grains. Otherwise, the currents are superpositions of various channels through multiple connections of SETs.
The increase of drain and source coupling capacitance upon increasing | | V g (table 1) can be explained by the changes of tunnelling barrier height and the forming of an inversion layer. The barrier height was continuously reduced when we increased | | V g , and the capacitive coupling between source and drain also became stronger [45]. As a result, the Coulomb diamond shrinks significantly. The formation of inversion layer also contributed to the shrink of the Coulomb diamond. When | | V g was large enough to invert the channel, the inversion layer was initially formed around the source region [39]. When | | V g was increased and the channel was inverted further, inversion layer started to expand from source to drain.
Next, we discuss the current peaks observed at the edges of the Coulomb diamond region. In order to analyse the current peak in detail, we plotted the I d −V d characteristics and the current map near the noise region in figure 5.
The current peak was only observable at a very narrow window in bias condition. In figure 5(a), at V g of −0.561 V, a current peak is clearly observed if V d was at −4 mV. When V g was at −0.559 V and −0.574 V, the peak was not observed. The fact that current peaks were found at the edge of the Coulomb diamonds implies that the current peaks were related to charge traps. The window of bias condition to observe this current peak is much narrower than the bias condition to observe Coulomb diamonds. This sharp current peak implies that the energy level broadening must be small in the charge trap, and resonant tunnelling was responsible for this phenomena. We were able to observe similar phenomena in figure 5(b), showing similar characteristics in the nMOSFET. More investigation is needed to identify the nature of these current peaks.

Conclusion
We observed single carrier trapping and de-trapping phenomena by measuring standard short-channel MOSFETs at low temperatures. We observed single hole/electron tunnelling phenomena at sub-threshold regions in both standard p-type and n-type short-channel MOSFETs. The size of the Coulomb diamond was shrinking with decreasing gate bias in p-MOSFET. The quantum dot corresponding to the Coulomb diamond was considered to have originated from the potential minimum created by the poly-Si grains. We also observed current peaks at the edge of Coulomb diamond at certain bias conditions. The current peaks were considered to have originated from the charge traps, which will potentially link reliability issues in advanced MOSFETs. Therefore, the low temperature measurements will be useful to investigate the single carrier trapping and de-trapping process in MOSFETs, which will help in understanding the quantum effects and pave the way to establish the relationship between scaled Si CMOSFETs and Si SETs.