Engineering of the spin on dopant process on silicon on insulator substrate

We report on a systematic analysis of phosphorus diffusion in silicon on insulator thin film via spin-on-dopant process (SOD). This method is used to provide an impurity source for semiconductor junction fabrication. The dopant is first spread into the substrate via SOD and then diffused by a rapid thermal annealing process. The dopant concentration and electron mobility were characterized at room and low temperature by four-probe and Hall bar electrical measurements. Time-of-flight-secondary ion mass spectroscopy was performed to estimate the diffusion profile of phosphorus for different annealing treatments. We find that a high phosphorous concentration (greater than 1020 atoms cm−3) with a limited diffusion of other chemical species and allowing to tune the electrical properties via annealing at high temperature for short time. The ease of implementation of the process, the low cost of the technique, the possibility to dope selectively and the uniform doping manufactured with statistical process control show that the methodology applied is very promising as an alternative to the conventional doping methods for the implementation of optoelectronic devices.


Introduction
The functionality of semiconductors relies strongly on the impurities that can be added to the intrinsic materials to change their electrical, physical, and optical properties. Uniform doping to realize ultrashallow junctions at transistor-like device source and drain has been a key point of the effort toward device scaling [1][2][3]. In traditional semiconductor device fabrication, the doping is carried out using mainly three methods: ion implantation, in situ co-deposition, or doping furnaces. Ion implantation is an excellent process that allows high level of control on both the dose of implanted impurity atoms and the implantation depth [4][5][6]. However, the conventional ion implantation process, which relies on the bombardment of semiconductors with energetic ions, is incompatible with nanostructured materials, such as onedimensional (1D) nanowires. Furthermore, it induces severe crystal damage which requires also an annealing step to reconstruct the crystal and activate the implanted impurities. Very high temperature are usually needed, limiting its applicability to platforms that can substain high thermal budget processes. These aspects make ion implantation a delicate and costly process. In co-deposition techniques, such as chemical vapor deposition (CVD), the dopant is directly introduced in the growth chamber by a carrier gas [7][8][9][10]. This approach offers an excellent control of the dopant concentration and solubility, which can be tuned by changing the vapor pressure of the source and the temperature of the substrate during the thin films deposition. However, in CVD method the presence of toxic and explosive gases requires many safety precautions, making it an expensive and dangerous technique. Moreover, this approach lacks spatial control as it affects homogeneously the full wafer surface. In doping furnaces, doping is achieved by exposing the wafers to a flux of dopant atoms from the sublimation/evaporation of a solid/liquid source or from a gas source. Dopant diffusion into the substrate is promoted by heating the wafers for the time needed to achieve the desired doping profile. Typically, doping furnaces can be hosted only in large facilities and can accommodate a large quantity of substrates. However, due to the hazardous nature of the dopant sources, this step often requires a very long time in a controlled environment [11,12].
To overcome the difficulties of conventional technologies and their correlated costs, tremendous research efforts have been taken in recent years to develop new strategies for introducing dopants into semiconductor materials such as monolayer doping [13][14][15][16] or spin on dopant (SOD) [17][18][19][20][21][22][23]. In this work we applied a SOD treatment with rapid thermal annealing process (RTA) to drive-in the dopants from the SOD polymeric film into the silicon substrate, without modifing the surface energy, requiring covalent attachment methods, such in surface-initiated polymerization [2] and grafting of functionalized polymers [24,25]. The SOD film provides an impurity source for semiconductor junction fabrication, and due to the convenience and simplicity of use, it greatly reduces the reliance on the traditional facilities for doping diffusion. SOD based treatments have become increasingly popular due to their simple, uniform doping profile, high yields, and possibility to introduce both n-and p-type doping [26,27]. The advantage of SOD over the aforementioned methods relies in its low cost, simple control of the process and its adaptability to different platforms, achieving a uniformity of the coated film on large substrates. Moreover, it eliminates the need for dangerous gases and their related safety precautions, it is more environmentally friendly, and reduces manufacturing costs. Additionally, unlike CVD method and furnace-based doping approaches, the SOD process allows selective doping via lithographically patterned areas, similarly to ion implantation [28]. The possibility of diffusing the SOD only in specific areas is very interesting for new nanoelectronic applications: for instance, in the fin field effect transistor the channel has not to be doped, giving the gate higher ability to control threshold voltage, which is a very important property when the transistor is scaling down, while the source and drain regions can be doped locally by SOD process. Here, we have targeted high doping levels -even though perfectly localized-to address the needs of FinFET devices for plasmonic and quantum applications [29,30]. Clearly, such devices will not be the only perspective potentials of applications, but the necessity of having a high level of localized doping, makes them one of most challenging devices.
In this work we systematically investigate the diffusion of phosphorous from a SOD source in silicon on insulator (SOI) wafers, RTA treatments are performed using different temperatures and process times, leading to the optimization of the desired final doping concentration. By a systematic analysis of the electrical characterizations, the values of P diffusion electrically activated, the doping and mobility were extracted and compared with the chemical P diffusion obtained through time of flight secondary ion mass spectrometry (ToF-SIMS) analyses measurements, demonstrating a successful control of dopant diffusion on SOI susbtrates. At the end, a localized doped Si-based nanodevice is tested as validation of the SOD procedure.

Methods
The optimization of the SOD treatments was carried out using a (001) SOI substrate, featuring a 125 nm thick Si layer on a 1 μm buried oxide (BOX) (figure 1(a)). After a cleaning process (ultrasonic treatment with acetone, isopropanol, and N-methyl-2-pyrrolidone) the SOI wafers were spin-coated with the commercial SOD P508 (composition: 8% P and 5% SiO 2 ) for 30 s at speed of 3000 rpm ( figure 1(b)). This process was carried out in a temperature and humidity-controlled environment to prevent cloudiness of the SOD layer. To evaporate the volatile solvent contained in P508, the samples were baked on a hot plate at 55°C for 10 min and then at 120°C for 15 min (figure 1(c)). The two baking steps were necessary to avoid cracking of the SOD film. The diffusion of the dopant in silicon was performed by RTA. Different annealing temperatures and times were tested to study the behavior of the diffusion profile and the resulting doping level as reported in table 1. In each process the RTA system ramped up in 9 s to the annealing temperature, which was maintained for process times in the 10-90 s range. The samples were cooled down in a controlled way by flowing the N 2 in the chamber ( figure 1(d)). The remaining SOD layer was removed by rinsing in a HF solution (5% vol) for 1 min, followed by an oxygen plasma asher treatment for 30 min at 1000 W to remove any organic contamination. A final HF rinse (5% vol) for 30 s (figure 1(e)) is performed to remove any SOD residues. The reproducibility of the process was validated by processing three different samples batches. After the doping treatment by SOD and the cleaning of the samples, devices for four-probe measurements and Hall bar shaped devices were fabricated (figure 2). The four-probe devices fabrication includes just one step of optical lithography, where a positive resist is patterned before the metal deposition. The metallic contacts were obtained by electron beam evaporation of 7 nm of Ti, 50 nm of Au and 100 nm of Al followed by a lift-off process (figures 2(g), (h)). The Ti was used as a prime to increase the adhesion of Au to the Si substrate, Al allowed us to increase the final thickness of the metals to facilitate the bonding. The Hall bar shaped devices consist of a mesa, patterned by optical lithography and transferred to the substrate by dry etching (CF 4 plasma), (figure 2(b)). Specifically, the adhesion promoter TI PRIME was spin-coated at 3000 rpm for 5 s, then the positive resist AZ 5214E was spin-coated in two different steps at 750 rpm for 5 s and at 4000 rpm for 40 s. After the optical lithography, the samples were dipped for 15 s in dilute HF to remove the native oxide layer on the surface right before the contacts deposition. Finally, to obtain ohmic contacts we performed the same procedure reported for the four-probe devices. To improve the quality of the contacts, by lowering the contacts resistivity, the samples were annealed in a furnace at 300°C for 180 s [31]. Samples were characterized electrically according to the Van der Pauw method [32], and carrier density and Hall mobility were extracted from Hall effect measurements. This electrical characterization was carried out using a permanent magnet creating a 0.204 T magnetic field at room temperature, and an electromagnet which applied a magnetic field ranging from 0 to 1 T at 3 K with an accuracy of 3 mK. The temperature has been measured with a Cernox ® negative temperature coefficient RTD made of ceramic oxynitride. The phosphorous profile was obtained by ToF-SIMS analyses operating in negative mode and sputtering an area of 500×500 μm 2 using Cs + ions at 1 keV and an area of 50×50 μm 2 using Ga + ions at 25 keV. Phosphorous quantification was performed according to a calibration procedure that was widely discussed in a previous paper [33]. Finally, by a combination of electron beam lithography and reactive ion etching a Si-based nanodevice using the same SOI substrate before descripted is realized: a SiO 2 hard mask is realized and the SOD spincoated in selective areas. The I/V characterization at room temperatures has been carried out to confirm the localized doping optimized by SOD treatment.

Results
The doping concentration N D was obtained by measuring the resistivity ρ of each sample with the dual configuration four-point probe method [34]. The two resistances R A and R B associated with the corresponding contacts are reported in figure 3. From these characteristic resistances the sheet resistance R S and the electrical resistivity r can be obtained by: where x Si is the thickness of the conductive layer [35]. In this analysis, the top Si layer (x Si =125 nm) is considered completely and homogeneously doped, neglecting that P atoms have a limited penetration depth as detected by the ToF-SIMS analyses reported below. Since the contacts were positioned in the middle of the sample and not in the corners of a square sample, a correction factor of 2 (in the equation (1)) is reported in the numerator in the classical Van der Pauw configuration [36]. The model described by Thurber et al was used to find concentration using the measured resistivity [37]. According to this model it is possible to define a parameter x as the logarithm of the ratio between the measured resistivity r and the normalization value r = W 1 cm and the quantity P as the product between the electronic charge q, the measured resistivity r and the electrically active doping density N D : Then, solving equation (5) using the parameters reported in table 2 and the normalization factor P 0 equal to 1 V s cm −2 : the doping concentration N D is obtained from equations (4) and (5): The N D values should be considered as a lower bound of the doping concentration. In fact in the evaluation of the resistivity, we considered the whole thickness of the SOI, 125 nm in our case. Although the Tof-SIMS characterizations (shown below) confirm a gradient of the chemical diffusion of phosphorus, in this analysis we consider a uniform distribution of the electrically active phosphorus because it was not possible to perform four-probe measurements at the various depths levels. By increasing the annealing time and temperature it was possible to obtain a high level of doping in silicon. For an annealing time below 30 s a doping level of 10 19 atoms cm −3 can be achieved at an annealing temperature of at least 880°C, while on increasing the annealing time to 90 s, the same level can be obtained for annealing temperatures just at 860°C. The maximum reached dopant density measured by four-probe method is about 7.8×10 19 atoms cm −3 for 90 s annealing time at 915°C.
Considering the samples annealed in the range between 860°C and 915°C and characterized by four-probes measurements, the doping concentration is a linear function of the square root of the annealing time as reported in figure 4. This same behavior is predicted by the diffusion model assuming that (1) the Si thickness is few times larger than the diffusion length of the dopant, and (2) the SOD acts as an infinite source of dopant in contact with a semi-infinite medium [38].
erfc , x Dt 0 2 ( ) ( ) c 0 being the doping concentration at the SOD/silicon interface, and it is assumed to have a solubility limit of c 0 =3.5×10 20 atoms cm −3 for phosphorus [39]. , the activation energy of 3.88 eV has been obtained. This value is in agreement with the phosphorus activation energy obtained by others using a similar SOD product but other annealing treatments [40,41]. To characterize the chemical diffusion profile of phosphorous, some ToF-SIMS analyses have been carried out (G series in table 1). The chemical profiles for different species diffused by RTA with various annealing     properties as reported by the mobility values in table 3. A phosphorous signal is detected in first 15-30 nm with a relatively long tail extending towards the Si/BOX interface, confirming a gradient of the phosphorous chemical diffusion. In order to continue the characterization of the samples, Hall bar measurements were performed in order to obtain the doping concentration and the electron mobility. The Hall mobility is obtained from the ratio between the Hall coefficient of the material R H and the resistivity ρ. By exploiting the six-contact Hall bar geometry, an average value of the Hall coefficient R H can be obtained in order to limit the negative effects caused by the non-uniformities of the sample. The resistivity ρ, instead, is obtained from: where V is the longitudinal voltage (figure 2(f)), W and L are respectively the width of the conductive channel of the Hall bar and the length between the voltage probes. The measured data are reported in table 3. The doping concentrations are similar at 300 and 3 K, while the mobility values are higher at low temperature. The main factors that affect the mobility in an extrinsic semiconductor are impurity scattering, phonon scattering, and electron-electron scattering: the role of impurity scattering becomes more important as the doping density increases or when the temperature decreases [42]. According to [43], samples characterized by high doping levels are more difficult to measure and are not particularly affected by the variation of the temperature. The measured mobility values are in agreement with those of silicon samples doped with P using different techniques [44,45], confirming the validity of doping mechanism with fast and low-cost SOD process. Finally, it is shown the capability of doping selective area through a Si-based nanodevice. From an SOI with a device layer of 145 nm are fabricated four Si pads linked through a 200 nm wide channel as reported in figure 7. To selectively doped two of the four pads (respectively contacts 1 and 3) and to leave the inner nanometric intrinsic channel, a SiO 2 mask is created figure 8. After the SOD doping treatment at 880°C, an electrical catherization is performed between all contacts. The I-V curve reported in figure 7(a) shows an ohmic profile between the two SOD doped contacts (contacts 1 and 3), while no current is observed between the undoped ones (pad 2 and pad4), confirming the selective doping validation procedure.

Conclusions
In this work, we exploited the spin-on dopant process on SOI wafers. By tuning the RTA treatment parameters, we are able to diffuse the phosphorous into the silicon layer with different Table 3. Experimental value of the doping density level and the electron mobility of 3 samples from Hall bar measurements carried out at 300 K and at 3 K.   depth profiles. In contrast with the typical doping processes, the SOD diffusion is a low cost process and it does not damage the crystal structure. By electrical characterization at room and low temperatures, the activated phosphorous concentration, the carrier mobility, and P diffusivity have been measured. We show that by SOD treatment, a high level of n-type doping greater than 1×10 20 atoms cm −3 can be reached. The Tof-SIMS analyses reveal that the phosphorous profiles depends to the RTA time. The possibility of doping with high doses, in confined areas and at a low cost is of great interest for quantum devices, Fin-FET and similar devices.