Wafer-scale nanofabrication of sub-100 nm arrays by deep-UV displacement Talbot lithography

In this manuscript, we demonstrate the potential of replacing the standard bottom anti-reflective coating (BARC) with a polymethylglutarimide (PMGI) layer for wafer-scale nanofabrication by means of deep-UV displacement talbot lithography (DTL). PMGI is functioning as a developable non-UV sensitive bottom anti-reflective coating (DBARC). After introducing the fabrication process using a standard BARC-based coating and the novel PMGI-based one, the DTL nanopatterning capabilities for both coatings are compared by means of the fabrication of etched nanoholes in a dielectric layer and metal nanodots made by lift-off. Improvement of DTL capabilities are attributed to a reduction of process complexity by avoiding the use of O2 plasma etching of the BARC layer. We show the capacity of this approach to produce nanoholes or nanodots with diameters ranging from 95 to 200 nm at a wafer-scale using only one mask and a proper exposing dose. The minimum diameter of the nanoholes is reduced from 118 to 95 nm when using the PMGI-based coating instead of the BARC-based one. The possibilities opened by the PMGI-based coating are illustrated by the successful fabrication of an array of nanoholes with sub-100 nm diameter for GaAs nanowire growth on a 2″ GaAs wafer, a 2″ nanoimprint lithography (NIL) master stamp, and an array of Au nanodots made by lift-off on a 4″ silica wafer. Therefore, DTL possess the potential for wafer-scale manufacturing of nano-engineered materials.


Introduction
Nanofabrication of periodic arrays of nanostructures is crucial for the realization of devices controlled down to the nanoscale. Over the last decades there has been a dramatic increase in applications of nanotechnology in fields such as physics, Original content from this work may be used under the terms of the Creative Commons Attribution 4.0 licence. Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI. chemistry, biomedicine, and materials science. This leads to the requirement for nanopatterning of large-areas with high reproducibility and throughput at a low cost. There exist a wide variety of patterning techniques, but each one offers different advantages and disadvantages. Deep-ultraviolet immersion lithography, using a 193 nm excimer laser, capable of achieving a resolution of 14 nm, is widely applied in industry [1], and the development of extreme-UV sources will push the resolution further down [2]. However, the associated high costs limit their introduction into companies with a lower volume production and research organisations.
Electron-beam lithography is flexible and able to define features below 10 nm, though, its cost is prohibitive for waferscale nanofabrication [3]. Nanoimprint lithography (NIL), based on mechanical pattern transfer between stamp and substrate, is a promising technique for large-area nanopatterning [4][5][6], able to reach below 10 nm feature size [7]. However, its main disadvantages are the lifetime of the nanoimprint stamp, the need of a flat and/or very clean surface, the mass transfer during imprinting process and the limited control over residues thickness. Nanosphere lithography, which relies on the selfassembly of colloidal spheres, is not suitable to full-wafer nanopatterning yet due to poor pattern fidelity [8,9]. Laser interference lithography [10], based on the interference of two coherent laser beams, can produce periodic nanopatterns down to 20 nm. Although it is suitable for large-area nanopatterning with high-yield, maintaining the light source stability can be rather challenging.
Recently, Talbot lithography, based on the self-imaging effect called Talbot effect, has emerged as an alternative technique for nanopatterning [11][12][13]. When highly collimated monochromatic light passes through a periodic pattern (grating or array of holes), several diffraction orders are produced and interfere resulting in a self-image of the regular pattern. This self-image is periodically repeated along the axis perpendicular to the mask. The period of the self-image, called the Talbot distance, is given by [14]: Where λ is the wavelength of the illumination light and p is the pitch of the periodic pattern. Due to the complexity and spatial distribution of the interference pattern it is difficult to apply directly the Talbot effect for photolithography. However, by introducing a displacement of the substrate relative to the mask, along the perpendicular direction, it is possible to integrate the optical field and solve the above mentioned issues. Thus, resulting in the development of displacement Talbot lithography (DTL) [15]. DTL has been confirmed as an excellent technique for large area nanofabrication of periodic features at a low cost and insensitive to surface bowing [16,17]. Applications of DTL include metamaterials [18], dielectric and metal mask fabrication for selective area epitaxy, such as III-Ns nanotubes [19] and nanowires [20][21][22], nanowires made of bottom antireflective coating (BARC) [23], nanoimprint stamp fabrication [24], and neuronal network formation [25], and, by moving the substrate in parallel to the mask while exposing, complex features can be realized [26]. The minimum feature size that can be transfer to the substrate depends on the light source wavelength, on the type of feature and on the different etching steps. Whereas dots of 75 nm [24] and holes of 100 nm [14] can be transferred to the resist layers, it is much harder to achieve such small features in the substrate. Up to now, it has been reported a minimum diameter of 90 nm in top-down Si pillars [24] and of 250 nm in holes transferred to GaN [27].
The DUV lithography processes include the use of a BARC layer together with a DUV sensitive resist. The BARC layer minimizes reflection from the substrate, which can ruin the mask self-image. However, these processes need plasma etching to transfer the pattern from the resist down to the underlying substrate [28]. The widening of the nanoholes when transferring from the resist to the substrate can be attributed to lateral etching of the BARC layer. Therefore, a polymer stacking sequence that keeps the feature size during pattern transfer to the substrate is highly desirable.
To avoid the plasma etching of the BARC layer, significant efforts have been devoted to the research on developable BARCs (DBARCs) [29][30][31]. DBARCs are developersoluble-polymer based anti-reflective coatings. The majority of the DBARC polymers reported so far can be classified into photosensitive and non-photosensitive. However, DBARC can be influenced by components and process conditions [32]. Toukhy and co-workers [33] demonstrate a first generation of methacrylate based DBARCs with promising results.
In this manuscript we report for the first time the patterning of sub-100 nm holes in a dielectric mask. To do so, we replace the standard BARC layer by a polymethylglutarimide (PMGI) layer. PMGI is an alkaline soluble polymer derived from Polymethyl methacrylate that can work as a non-imageable DBARC with an isotropic dissolution rate in developer, resulting in a direct transfer of the nanopattern during the development step which in turn results in a reduction of the nanohole diameter. In addition, PMGI is a lift-off resist that produces an undercut, so, there is no need of an additional lift-off resist layer (LOR). Thus, also simplifying the lift-off process. After introducing the standard fabrication process using a BARC layer and the novel process employing a PMGI layer, the DTL nanopatterning capabilities for both processes are compared by means of the fabrication of etched nanoholes and metal nanodots made by lift-off. The pattern on the resist are subsequently transferred to a dielectric or metal mask by etching or lift-off, respectively. Therefore, the fabricated dielectric or metal mask can be applied to futher technological processes including top-down etching or nanowire growth. This process is successfully applied to fabricate an array of nanoholes with sub-100 nm diameter for GaAs nanowire growth, a NIL stamp fabrication, and the preparation of an array of lift-off Au nanodots on a silica wafer. Compared to other nanolithography techniques, this approach offers full-wafer scale fabrication of sub-100 nm nanohole arrays in dielectric masks at low cost.

Experimental
All studied samples were prepared on commercial (i) SiO 2 on Si (100), (ii) in-house deposited inductively coupled plasmachemical vapour deposition (ICP-CVD) SiN x on Si (100) and GaAs (111) B , or (iii) UV-grade 1 mm thick 4 ′′ fused silica wafers manufactured by SiegertWafer, and WaferTech. The SiNx layers were prepared in a MicroSys-200 manufactured by MicroSystems GmbH, Germany. Samples were exposed in our PhableR 100 DUV photolithography system manufactured by Eulitha AG, Switzerland. The system is equipped with a pulsed ArF excimer laser (λ = 193 nm). The laser pulse frequency can be tuned from 30 to 150 Hz and the single pulse energy from 0.5 to 5.0 mJ. The DTL system is installed in its own encasement and dedicated HEPA® filters are mounted for particle and amine concentration reduction. Samples were inspected using a SU8010 cold field emission-scanning electron microscope (FE-SEM), Hitachi, Japan, and a Leo 1560 Thermal FE-SEM, Zeiss, Germany. For the diameter calculations of the features the ImageJ® software and a contrastbased algorithm were employed to measure the areas and circularities of the features to subsequently calculate the diameter of the features. Reactive ion etching (RIE) processes were carried out in a table-top Sirus T2 Plus system from Trion Technology, Inc, US. Ozone cleaning was performed in a UV-ozone cleaner UVOH 150 from FHR Anlagenbau GmbH, Germany. Nanowire (NW) growth was performed in a 3 × 3 ′′ Close Coupled Showerhead Metal-Organic Vapour Phase Epitaxial (MOVPE) reactor from Aixtron GmbH, Germany. Regarding NIL, an EiTRE 6 NIL system, manufactured by Obducat AB, Sweden, was employed. The antisticking treatment of the NIL master stamps was carried out in a FIJI plasma enhanced atomic layer deposition system manufactured by Veeco Instruments Inc, USA.
We are going to compare two different coatings for DTL namely the BARC-based and the PMGI-based coatings. On one hand, the standard or BARC-based coating comprises a deep-UV (DUV) resist PAR1077S90 or PAR1085S90 (Sumitomo, Japan) and a BARC GenARC 266 (Brewer Science Inc, USA) layer [34]. On the other hand, the PMGI-based process includes the same deep-UV resists and a PMGI SF3S polymer (MicroChem Corp, USA) replacing the BARC layer.

Results and discussion
In order to do a fair comparison, both coatings will be employed in the fabrication of etched nanoholes in a dielectric layer and lift-off nanodots.

Etching process BARC vs. PMGI
The fabrication of arrays of nanoholes is technologically attractive for many different processes, such as the realization of masks for the selective growth of nanostructures such as III-V nanowires [5,6,[35][36][37], for the preparation of NIL stamps [24], and the fabrication of porous layers [27] to name a few.
The DTL exposures (figure 1(a)) were performed using a phase shift mask with a hexagonal array of nanoholes of 200 nm diameter with 500 nm pitch. The gap between mask and wafer was set to 80 µm, and the range of displacement was set to aproximately 3 Talbot lengths of ∼ 8 µm. Laser pulse energy was set to 1.5 mJ and frequency to 100 Hz and the accumulated dose was varied between 2.5 mJ cm −2 and 7.0 mJ cm −2 .
The substrates employed for the etching of nanoholes, independent of the coating used, were 2 ′′ Si(100) with a 100 nm SiO 2 dielectric layer. Figure 1 shows the schematic representation of the nanopatterning via etching for both BARC-and PMGI-based coatings.
For the preparation of the BARC-based coating (figures 1(a)-(e)), the BARC layer, spun at 2500 rpm for 45 s, was baked at 180 • C during 1 min resulting in a 64 nm thick layer. Then the DUV resist was spun on top at 2000 rpm during 45 s and baked at 90 • C during 1 min for a thickness of 115 nm. After the DTL exposure the wafer was baked at 100 • C for 50 s and developed in MF24A for 50 s ( figure 1(b)). Then, the pattern was transferred to the BARC layer via O 2 plasma etching (figure 1(c)) at room temperature (RT), 40 sccm O 2 , 150 mTorr, and 50 W of radio-frequency (RF) power, resulting in an etch rate of~54 nm min −1 . The pattern created on the BARC layer was transfer further into the dielectric layer (SiO 2 in this case) via reactive ion etching (RIE, figure 1(d)), in the above mentioned Sirus T2 system, with a mixture of 5 sccm CHF 3 and 5 sccm CF 4 , at RT, 50 mTorr, and 75 W of RF power, resulting in an etch rate of~18 nm min −1 . Finally, the wafer surface was cleaned from polymers and residues with O 2 plasma (figure 1(e)) at the conditions described for the etching of the BARC layer.
The PMGI-based coating (figures 1(f)-(i)) was prepared according to the following recipe. The wafers were spincoated with PMGI at 2500 rpm for 45 s, and baked at 200 • C for 10 min resulting in a 75 nm thick layer. Afterwards, the DUV resist was spun on top at 2000 rpm during 45 s and baked at 90 • C for 1 min resulting in a thickness of 115 nm. After the DTL exposure (figure 1(f)) the wafer was baked at 100 • C for 50 s and developed in MF24A for 50 s ( figure 1(g)), transferring the pattern directly into the PMGI layer. Then, the pattern created on the PMGI layer was transferred further into the dielectric layer (SiO 2 in this case) via reactive ion etching (RIE, figure 1(h)), in the above mentioned Sirus T2 system, with 10 sccm of CHF 3 , at RT, 20 mTorr, and 75 W of RF power, resulting in an etch rate of~18 nm min −1 . In a final step, the wafer surface was cleaned from polymers and residues with ozone (figure 1(i)) at 90 • C, a flow of O 2 of 500 sccm, and a wide band UV irradiation intensity for O 3 generation of 50 mW cm −2 . Figure 2 shows the nanoholes experimentally transferred to the SiO 2 dielectric layer following the process described in figure 1 for both coatings. The patterns were achieved for various accumulated doses in a positive resist with only one mask. The nanohole openings diameter increases from~118 to~256 nm for the BARC-based coating (figures 2(a)-(c)) and from~95 to~179 nm for the PMGIbased one (figures 2(f)-(h)). For accumulated doses below 2.5 and 3.0 mJ cm −2 for BARC and PMGI respectively, defects in the form of vacancies (missing holes) and or underdeveloped nanoholes start to occur. Those problems are related to an inhomogeneous DTL exposure (see SI figure S1 stacks.iop.org/Nano/31/295301/mmedia). On the other hand, for accumulated doses over 5.5 and 7.0 mJ cm −2 for BARC and PMGI respectively, additional features surrounding the nanoholes appear. Those features are the result of the second order diffraction pattern that occurs at high enough accumulated doses [14]. It is worth mentioning that the final nanohole size can be controlled not only by the accumulated dose (figure 2), but also by resists thickness optimization (see SI figure S2).
The minimum diameter of the nanoholes is 95 nm and 118 nm by using the PMGI-and the BARC-based coatings respectively, for the defect free exposure conditions (see SI figures S1 and S2). The main difference between the processes described for both coatings is that in case of the PMGI-coating the pattern is transferred to the PMGI layer during the development step ( figure 1(g)), thus, simplifying the process by avoiding the O 2 plasma etching, also known as de-scum, of the BARC layer. In addition, the O 2 plasma etching rate of DUV resist is higher than of BARC layer (see supporting info, SI, figure S3). The absence of selectivity during the de-scum step makes it not suitable for transferring the pattern into the layer beneath, affecting the total thickness of nanopatterned resists (after de-scum DUV resist is almost completely etched) and nanohole edge slope. Therefore, an obvious advantage of replacing the BARC layer by PMGI is the possibility of maintaining the size and shape of the nanoholes, and to create a proper slope for transferring the nanoholes into the underneath dielectric layer. It is worth mentioning that during the etching of the dielectric, the deposition of a CF x layer on top of the resist protects it against erosion during etching [38], which in turns helps keeping the nanohole edge slope, and the total thickness of the nanopatterned resists. Moreover, the recipe described to etch the nanoholes into the SiO 2 or SiN x dielectric layer creates a~78-82 • slope that maintains the nanohole size (see SI figure S4) created by using PMGI with respect to the ones obtained with BARC.
In the experiments described in this article, the BARC layer employed (GenARC 266) was insensitive to DUV radiation and insoluble in developer (MF24A), so it was needed the use of an O 2 plasma etching to transfer the nanopattern from the DUV resist to the BARC layer. The poor selectivity between the DUV resist and the BARC layer against the O 2 plasma ruins the resist profile making it not suitable for an appropriate nanopattern transference. On the contrary, when using the PMGI-based coating, as the PMGI polymer is soluble in MF24A developer, the O 2 plasma etching can be avoided and the abovementioned detrimental issue can be overcome.
We cannot claim that PMGI is better than BARC generally. For example, UV sensitive BARC, soluble in developer and optimized for 193 nm wavelength can be a challenge in order to give a better resolution.
Regarding the limitations of PMGI, the dissolution rate in the developer strongly depends on baking temperature (200 • C in this case) and on the development time. The dissolution of PMGI in MF24A is isotropic and undercut should be as deep as the PMGI thickness. However, the optimal PMGI thickness is also important due to its antireflective properties. Those are the main limit for the resolution due to the risk of pattern collapse.
Regarding DUV light absorption, PMGI has a relatively high extinction coefficient at 193 nm making it suitable for DTL [39]. In addition, the thickness of the dielectric layer, such as SiO 2 or SiN x , can be engineered to further reduce reflections from the substrate. Thus, achieving an even better resolution.
In addition, as DTL is a non-contact technique, the fabrication of nanoholes in a dielectric mask does not depend on the surface roughness of the dielectric layer. In contrast, as NIL is a contact technique, surface roughness plays a significant role in the transference of the pattern, which, in the worst case, can lead to serious damage on the wafer, such as cracks or fractures, due to wafer bowing.

Lift-off process BARC vs PMGI
Alternatively to the fabrication of nanoholes, metal nanodots can be deposited on the wafer surface by means of lift-off. Figure 3 summarizes the lift-off process for both the BARC-(figures 3(a)-(f)) and PMGI-(figures 3(g)-(j)) based coatings. However, the profile obtained in the BARC layer after the descum process (figure 3(c)) is not suitable for a reliable lift-off due to the lack of undercut profile. Thus, the addition of a liftoff resist (LOR) layer is essential.
The LOR layer was spin-coated on a 100 nm SiO 2 /Si wafer at 2500 rpm for 63 s and baked at 200 • C for 10 min resulting on a 70 nm thick LOR layer. After that, the process continued according to the description given in the previous section for the BARC-based coating. After development ( figure 3(b)) and O 2 plasma etching ( figure 3(c) In the case of the PMGI-based process, a suitable overhanging lift-off profile can be obtained right after the development step ( figure 3(h)). It is only necessary to control the development time for an optimised undercut profile; 60 s in figure 3(h). Then, metal was evaporated (figure 3(i)) and lift-off carried out as disscused for the BARC-based process ( figure 3(j)).
The use of a PMGI layer significantly reduces the complexity of the fabrication of metal nanodots. A suitable undercut profile can be achieved right after the development of the wafer. In this way, the O 2 plasma etching and its undesirables drawbacks (mentioned in section 3.1) can be avoided.

Application of PMGI-based process
After describing and comparing the BARC-and PMGI-based coatings, the PMGI-based coating is applied successfully to three different nanofabrication processes (figure 4).

Template for NW growth.
Arrays of Au-nanodots inside a nanohole in a dielectric layer conforms a route for pattern preservation in the growth of GaAs NWs via the vapourliquid-solid (VLS) growth mode [5,6,[35][36][37].
A 70 nm thick SiN x layer was deposited on a 2 ′′ GaAs (111) B wafer by means of ICP-CVD using a mixture of Ar/SiH 4 /N 2 (60/10.5/9.5 sccm) at 200 • C, 0.025 mbar and 1000 W ICP power and 3 W RF power, resulting in a deposition rate of 42 nm min −1 . Fabrication of nanoholes was performed following the process described in section 3.1 for PMGI-based coating. After completing the fabrication of nanoholes, Au nanodots were electrodeposited (figure 4(a)) using pulsed electrodeposition at a peak current density of 5 mA cm −2 (details can be found in SI section 5). Wurtzite-GaAs NWs were grown by means of MOVPE using arsine and trimethylgallium at a V/III ratio of 3.51, and susceptor set temperature of 540 • C for 30 min. Resulting in 2.8 µm long and 95 nm diameter wurtzite GaAs NWs ( figure 4(b)). We achieved a 100% yield and pattern preservation, over all scanned areas, due to Au particle locking by the presence of the SiN x mask. The use of a dielectric mask prevents parasitic growth, as well as facilitates the use of electrodeposited gold to reduce material consumption and to avoid Au residues on the nanohole edges that can contribute to parasitic NW growth.

3.3.2.
Fabrication of NIL master stamps. NIL master stamps for a two-step NIL process were fabricated on 2 ′′ 200 nm SiO 2 /Si wafers. Fabrication of nanoholes in SiO 2 followed the method described in section 3.1. The mask employed was a phase shift mask with a hexagonal array of nanoholes of 200 nm diameter with 600 nm pitch. The array of nanoholes was transferred to the SiO 2 layer via a CHF 3 -based reactive ion etching process using the Si/SiO 2 interface as an etch-stop. Figure 4(c) shows the SEM top-view and the cross-section of the array of nanoholes on the master stamp after the cleaning step. After applying an F-based anti-sticking treatment, the master stamp was replicated into an intermediate polymer stamp, using a soft GMN-PS90 polymer foil. The polymer stamp was prepared in an UV imprint process at room temperature in an Eitre 6 nanoimprinter using a modified version of simultaneous thermal and UV-process (STU) [40]. The polymer stamp (figure 4(d)), which consists of an array of 200 nm tall pillars with a diameter of 170 nm and a pitch of 600 nm, was made as a replica from the DTL-PMGI fabricated 2 ′′ master SiO 2/ Si stamp ( figure 4(c)). The replicas are defect free with an equal height of pillars over the entire wafer, which is critical for quality and stability of the NIL process on targeted substrates.

Lift-off Au nanodots.
Fabrication of arrays of Au nanodots is crucial for III-V VLS-NW growth [5,6,[35][36][37], for hard mask fabrication [27], and plasmonic arrays on insulating and transparent substrates. Fabrication of Au nanodots followed the method described in section 3.2. Resulting in a hexagonal array of 140 nm diameter Au nanodots (figure 4(e)) that completelly covers a 4" silica wafer (figure 4(f)). This result is difficult to obtain by any other nanolithography technique due to the combination of small size (140 nm), large area coverage (4"), and insulating substrate (silica).

Conclusions
In summary, PMGI can work as a non-imageable DBARC, resulting in a direct transfer of the nanopattern during the development step which in turn results in a reduction of the nanohole diameter. In addition, PMGI is a lift-off resist that produces an undercut, so, there is no need of an additional lift-off resist layer (LOR). Thus, also simplifying the lift-off process. Moreover, we demonstrate the huge potential of Displacement Talbot Lithography for wafer-scale nanofabrication for several applications as a fast, robust and scalable process.
In particular, we have demonstrated the successful substitution of BARC layer by PMGI polymer.
It is worth highlighting that thanks to this innovation we can fabricate nanoholes in a dielectric layer (SiO 2 and SiN x ) with a diameter below 100 nm. The use of a PMGI-based coating in combination with DTL allows a reduction of process complexity by avoiding the use of O 2 plasma etching; both for pattern transfer and for creation of a suitable undercut profile in one step together with resist development. This complexity reduction brings an additional benefit because of the low selectivity between DUV resist and BARC layer against O 2 -plasma etching which increases the nanohole size, affects the total thickness of the nanopatterned resists, and creates a nanohole edge slope not optimum for nanohole fabrication. In addition, with only one mask it is possible to select the final size of nanoholes or nanodots in a broad range (from 95 to 200 nm). Therefore, DTL is the perfect candidate for patterning of regular arrays of nanoholes at wafer-scale with a lower fabrication cost than other techniques. This process simplification is also of great importance to the fabrication of nanodots by means of lift-off.
Moreover, the possibilities opened by the PMGI-based coating are illustrated by the successful fabrication of an array of nanoholes with 95 nm diameter for GaAs nanowire growth on a 2 ′′ GaAs wafer, a 2 ′′ nanoimprint lithography (NIL) master stamp, and an array of Au nanodots made by lift-off on a 4 ′′ silica wafer. Therefore, DTL possess the potential for waferscale manufacturing of nano-engineered materials. This process can be extended up to 8 ′′ and 12 ′′ wafers. However, there are some practical limitations in the light source, quality of the mirror and of the collimation system, and the quality of the phase shift mask with the regular pattern.
This dynamic exposure process is based on the movement of the substrate perpendicular to the mask, in the 3D diffraction self-image of the regular mask. The yield is limited by the quality of the mask and the beam. The quality of the mask is defined in terms of pattern stitching, pattern size tolerances, homogenous phase shift distribution and the quality of the beam in terms of collimation, and intensity distribution. It is worth mentioning that resist and dielectric thickness variations can affect the homogeneity of the resulting nanopattern as well.