Study on electrical properties and structure optimization of side-gate nanoscale vacuum channel transistor

In this paper, a nanoscale vacuum channel transistor (NVCT) with a side-gate structure is fabricated by standard electron beam lithography. The states of the proposed NVCTs could be effectively modulated by side-gate bias, exhibiting a drive current (>400 nA), low work voltage (<20 V) and high on/off current ratio (>103). Moreover, we further optimize the shapes of the electrodes, demonstrating that the electric performance is closely related to the structure parameters. The side-gate NVCT offers an alternative method to fulfill the on-chip vacuum devices with high integration.


Introduction
Integrated circuits (IC) constitute the foundation of the information society, and early research on IC, e.g. signal amplification or modulation, was mostly based on vacuum tubes [1,2]. Vacuum tubes or vacuum electronics initiated the early development of electronics. Meanwhile, with the continuous advancement of technology, higher requirements for electronic devices have been put forward with low-cost and miniaturization. Vacuum electronic devices have gradually been replaced by silicon-based devices, due to their high-power consumption and difficulty for high integration [3].
However, it is known that the carrier mobility in Si-based solid-state devices is intrinsically affected by the lattice scattering or impurities. Limited by material properties, Si-based devices cannot meet the accelerating needs of high frequency or fast response, which gradually lose the pace of Moore's law [4,5]. In contrast, vacuum allows electrons to achieve ballistic transport without collisions or scattering, leading to faster carrier transport than in the solid-state devices [6,7]. Moreover, a sub-100 nm vacuum channel can be readily acquired by current semiconductor processing, which reveals the feasibility of vacuum nanoelectronics with high integration [8].
As a result, researchers have attempted to compress the traditional vacuum channel down to the nanoscale in order to obtain novel vacuum electron devices. Meyyappan et al in NASA first proposed a planner tip-to-tip nanoscale vacuum channel transistor (NVCT) [9], which is similar to a conventional field effect transistor (FET). The difference is that NVCT replaces the carrier transport channel from silicon or 2D materials to a sub-150 nm vacuum nanogap. However, an inevitable contradiction exists between the operating voltage and the thickness of the gate insulation layer. Reducing the thickness of the insulation layer can significantly reduce the operating voltage and improve gate control capacity, while the gate leakage current will increase accordingly that restricts the practical application. Therefore, researchers have come up with other novel structures with low-dimensional materials F-N theory (Some figures may appear in colour only in the online journal) Original content from this work may be used under the terms of the Creative Commons Attribution 3.0 licence. Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI. [10], e.g. Spindt-type vertical [11,12] and gate-all-round NVCTs [13,14], which greatly shorten the distance of the gate and the emitter, leading to lower working voltage, high drive current and even better radiation resistance. However, the preparation processes of the structures mentioned above are relatively complex, which cannot be effectively compatible with current semiconductor processing.
Here, we explore to introduce the concept of on-chip integration into NVCT, specifically, preparing the emitter, collector, and gate in the same plane. In this paper, a sidegate vacuum nanogap structure is proposed and fabricated by standard electron beam lithography (EBL). The vacuum nanogap between the emitter and collector is less than 100 nm. The states of the side-gate NVCT could be effectively modulated by gate voltage, exhibiting a drive current (>100 nA), low work voltage (<20 V) and high on/off current ratio (>10 3 ). Besides, the influences of electrode shape on electric properties were further investigated. The concept of side-gate NVCT offers a promising platform to fulfill on-chip vacuum devices with high integration.

Methods
The preparation flow of the side-gate NVCT is demonstrated on a silicon oxide wafer (n-type substrate with 300 nm thick oxide) by conventional semiconductor processing [15]. The silicon oxide wafer is first ultrasonically washed in acetone, ethanol and deionized water, respectively. Then the gold nanogaps are formed by standard EBL. After electron beam evaporation (60 nm Au and 5 nm Cr) and a subsequent liftoff process, the prepared device is annealed via 2 h in a tube furnace under hydrogen (70 sccm) and argon (40 sccm) atmosphere at the temperature of 400 °C. The post-annealing can effectively remove the residual PMMA photoresist on the surface and improve the strength of the gold nanoribbons at the same time. All the fabrication steps can be easily compatible with current semiconductor processing, illustrating the feasibility of side-gate NVCT with high integration. Figure 1 exhibit the structure of the proposed side-gate NVCT. The device consists of the emitter, the collector and the side-gate, where the entire core area occupies less than 5 µm × 5 µm. The nano vacuum channel is formed between the emitter and collector, in which electrons transport is controlled by applying a bias voltage to the side-gate. Figures 1(b) and (c) show the zoom-in SEM images of the NVCT. The nanogap between the emitter and collector is about 100 nm, and the angle of emitter/collector tips is about 60°. Figure 1(d) is the optical image of dark-field microscope for the nanogap, which can show the uniformity of the sample surfaces. It can be seen that the surface of the electrode prepared by EBL has no excess impurities with good uniformity.

Results and discussion
The electric properties measurement is carried out in a vacuum chamber (10 −4 Pa), as is shown in figure 2. A bias voltage is applied at the side-gate to modulate the electron emission from emitter to collector, and a positive voltage is applied at the collector with the emitter being ground. After bonding to a printed circuit board (PCB), the device is connected to a Keithley 2400 digital source measure unit which outputs DC voltages and records the emission current. In order to avoid vacuum breakdown and damage of the sharp emitters, a current limit of 1 µA was imposed during the testing process. The voltage step is kept as 0.1 V during the test to maintain stability and accuracy. Figure 3(a) shows the output characteristics and the gateleakage current for the side-gate NVCT with a tip angle of 60°. It is clearly observed that the NVCT could effectively modulate the side-gate. As the gate voltage increases from 0 V to 5.8 V, the emission current increases significantly, exhibiting a drive current (>100 nA), low work voltage (<20 V) and high on/off current ratio (>10 3 ). Similar to conventional FETs, the side-gate NVCT can be switched from off-state to on-state by the gate voltage. Without a bias applied at the side-gate, the barrier is too broad to field emission or F-N tunneling for low-energy electrons, in which the NVCT is in the off-state. As the gate voltage increases, the vacuum barrier is compressed gradually which enhances the tunneling probability accordingly. Thus, NVCT switches to the on-state and the emission current grows exponentially with the increasing Vc. Meanwhile, it is noted that the I-V curves also exhibit some fluctuations at high bias voltage (>15 V). Presumably,  the extremely high electric field intensity at the tip may lead to Joule heating that 'evaporates' part of the emitter tip, thus altering the electric field distribution around the emitter and affecting the emission stability.
The Fowler-Nordheim (F-N) theory is about the relationship between the electron emission density and the external electric field intensity, based on the tunneling theory in quantum mechanics [16]. In general, the traditional F-N theor etical formula can be simplified to: where a = 1.56×10 −6 αβ 2 φd 2 , b = 6.83×10 9 φ 3/2 βd , α is the emission area (m 2 ), β is the field enhancement factor, f is the work function of the emission material (eV), V is the emitter voltage (V) and d is the width of the nano-vacuum channel (m). Take the logarithmic transformation of equation (1) ln where equation (2) is the commonly used F-N fitting equation that determines whether the field emission process occurs [17,18]. Figure 5(b) illustrates the corresponding F-N curves obtained by fitting the emission current data. It is observed that the F-N curves show a consistent linearity, indicating that the transport process of electrons in the nanogap satisfies F-N tunneling instead of thermal activation. Also, the stability test is further presented with a fixed collector and gate voltage of 15 V and 5 V, respectively. A slow decline of emission cur rent can be observed for the overall test time (15 min). The emission current shows a fluctuant trend when the device was initiated, while becoming much more stable as the emission degrades. Moreover, we also note that the cone-type structure has a significant improvement on the field emission performance compared to the previously reported plane-type structure. The cone-type electrodes can enhance the electric field intensity of the emitter surface, thereby compressing the surface barrier and increasing the tunneling probability. As a result, we further modify the shapes of the electrode tips to verify that the electric properties of NVCT are closely related to the surface morphology. The SEM images of side-gate NVCT with different emitter/collector tip angles and the corresponding field emission performance are shown in figures 4(a)-(e). It is observed that although differences exist in the electrode morphologies, all the NVCTs show a relatively consistent emission current tendency. Generally, the emission current increases exponentially with the raising emitter-collector voltage, Vc, while the side-gate can effectively improve the emission performance of the device. Furthermore, we note   that the turn-on voltage decreases from 10 V to 5 V, with the growth of the emitter angle from 30° to 60°. It illustrates that optimizing the emitter angle can enhance the electric field intensity, subsequently reducing the tunneling probability of electrons at the emitter surface. On the other hand, the emission current of the NVCTs with an emitter angle of 45° and 30° are relatively stable compared to the device with a 60° tip angle. The 'sharper' emitter electrode may obtain a much higher local field intensity around the 60° tip. It is supposed that the high field intensity could more easily cause changes at the sharper tip, thus altering the electric field distribution and leading to current fluctuation. In this case, it suggests that the stability of the device cannot be 'sacrificed' to obtain superior electrical properties, e.g. high electric field intensity or low turn-on voltage. It is necessary to comprehensively consider various factors to achieve a balance between electrical properties and stability.
Besides this, the intercepted current of the side-gate is also monitored during the measurement, as is shown in figures 4(b), (d) and (f). It is observed that the side-gate structure inevitably generates a gate current or the so-called leakage current [19], which may influence the practical applications of NVCTs in the fields of radio frequency (RF) or high-speed logic devices [20]. The asymmetric structure of the side-gate may be the main causing factor for the high gate current. Referring to the design theory of the gate engineering [21], we suppose that the initial trajectories of emission electrons can be optimized by adjusting the structural parameters. For instance, with a second gate added on the opposite side and tied electrically to the other gate, it would balance out the electric fields so that the gate interception should decrease. Still, the experimental results show that the majority of electrons arrive at the collector as desired where only a small minority is intercepted by the side-gate.
Electric field intensity simulations for various emitter tip angles are further carried out with CST Particle Studio. Figures 5(a)-(c) exhibit the electric field distribution of different structures and the peak field intensity normalized by the value of the 30° emitter angle is shown in figure 5(d). The maximum local field was extracted from the simulation results for comparison, showing a local field enhancement of 30% as the angle increased to 60°. The simulation results verify that the modification of surface morphology can lead to effective current increase and turn-on voltage reduction. Importantly, the proposed device structure can be readily fabricated by the conventional semiconductor process, which may be viewed as an alternative approach for NVCT.
We further compare the electric performance of the previous reported NVCTs with various material types, whose operating voltage, operating current, on/off ratio and gate current are listed in table 1. Generally, the NVCT can be divided into two categories: planar and vertical types. For the planar structures, the emitters/collectors are fabricated in the plane of the wafer surface, with the back-or surrounding-gate modulating the emission current horizontally. On the other hand, the vertical NVCTs are performed in accordance with conventional field emission devices, where electrons are extracted out of the plane of the emitters. As far as we are concerned, the planar NVCTs usually provide more convenience for design and fabrication. Here, our side-gate NVCT introduces the concept of in-plain structure, specifically, preparing the emitter, collector, and gate on the same wafer surface, which offers more compatibility and freedom for future integration.
It is clearly observed that the field emitters of NVCTs are mainly based on silicon, metal and graphene, which can be realized with standard semiconductor processing. Furthermore, different from field emission devices that need high working voltages up to hundreds of volts, NVCTs can regularly function at 20 V or even less. In addition, the operating current also plays an important role in practical applications. In this regard, Si-and SiC-based NVCTs exhibit distinct advantages in the orders of operating current, while the SiC-based NVCT still performs unsatisfactorily in the on/off current ratio. Comprehensively considering all the electric parameters, our NVCTs can offer both comparable operating current and on/off ratio. However, a non-negligible shortage of side-gate NVCTs is the high gate current or the so-called leakage current. As discussed above, the asymmetric structure of the side-gate may be the main causing factor for the high gate current. Further optimizing the structural parameters, e.g. symmetric gate structure or emitter shapes, may balance out the electric fields, decreasing the gate interception. We hope that it could be presented in a future publication.

Conclusion
In summary, we investigate the potential of applying planar sidegate structure on vacuum nanoelectronic devices. The side-gate NVCT can be easily fabricated by standard EBL. The field emission measurement is carried out in a vacuum chamber (10 −4 Pa). It is noted that the gate structure can effectively decrease the operating voltage and improve the electron emission performance. In addition, the shapes of the electrode tips are also altered, demonstrating that the electric properties of NVCT are closely related to the structure parameters. The optimization of the emitter structure can enhance the local field intensity and the tunneling probability, while leading to morph ology changes with current fluctuations at the same time. Thus, it is necessary to comprehensively consider various factors to achieve a balance between electrical performance and stability. Overall, the side-gate NVCT can exhibit a drive cur rent (>400 nA), low work voltage (<20 V) and high on/off current ratio (>10 3 ), which opens a new avenue towards the future on-chip vacuum devices with high integration.