The 2018 GaN power electronics roadmap

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

Silicon-based insulated gate bipolar transistors (IGBTs) and superjunction MOSFETs are fundamental components of present day power electronic systems for the conversion, control and conditioning of electrical energy, from generation to the point of load. If silicon devices were to be replaced by a more efficient semiconductor such as GaN, compact converters with ultra-high density could be designed only because the breakdown strength and electron mobility in GaN are respectively 10× and 2-5× higher. These basic material properties translate into smaller devices leading to higher frequency of operation, lower switching losses, and reduction in the comp onent count and size of passives. This was demonstrated by over 100 hours testing by NREL of 2 kW GaN inverters designed by the Red Electrical Devils, winners of the Google Little Box Challenge in 2015. Compact modules translate directly into lower weight, volume and cost. Coupled with increasing concern and government commitment to global warming, there are now strong commercial and legal pressures to accelerate adoption of these advantages into production systems.
Applications are now emerging that have no other practical solution than GaN. Take for example the automotive industry: GaN is the semiconductor of choice for power converters throughout vehicle electronics apart from the final drive inverter. Even here, there is now a very strong push to create production devices capable of switching as much as 100 A at 900 V. The advent of mass adoption of electric vehicles will in turn accelerate two other major markets that depend on highly efficient high-density power converters. Charging electric cars will require intelligent switching in the local power distribution grid to manage local generation and storage of electrical power in order to balance the load presented to the distribution grid. Simultaneously, IT infrastructure to support autonomous driving will create another massive parallel requirement for efficient compact power conversion.
GaN has evolved to the point where the cost of the transistor itself is no longer considered as the key driver in system cost. The novel solutions that the technology facilitates, provide savings in both manufacturing and running costs. Focus will come to bear on manufacturing parts in volume that will finally demonstrate the predicted price learning curves and focus attention on those research avenues that provide the fastest route to manufacturing maturity.
First generation production devices are now available from a broad range of suppliers including Transphorm, EPC, Panasonic, Infineon, GaN Systems, Dialog and Navitas. Each currently represents a different combination of process and design technology but their existence, proven performance advantages over silicon devices; reliability and manufacturability are seeing them designed into emerging applications in potentially massive new market applications. Investment in the GaN supply industry by major global companies such as Google, BMW and Delta Electronics underline the importance of GaN devices to the automotive, information technology and power supply industries. It is the focus of research and development in the manufacturing value chain beyond the transistor in these new systems that will have a very strong effect in directing the next phase of the roadmap for GaN semiconductor device technology.
This work brings together a palette of advanced research into GaN process developments presented by global leaders in GaN process and device technology that will inform solutions to challenges driven by the specific needs of converter and system development. Emerging demands that will feed from this work are the need to achieve 900 V breakdown in applications for local 3 phase grid interface and high-speed charging for vehicles, bi-directional switching, low inductance high thermal efficiency packaging and the potential to include on-chip sensing and control.
We hope you enjoy this peek into an enticing perhaps all-GaN future! 16. 600 V E-mode GaN power transistor technology: achievements and challenges 36 17. Potential of GaN integrated cascode transistors 38 18. Converter topologies in GaN 40 19. Fast switching with GaN and dynamic on-resist ance from application view-point 42 References 44

Marleen Van Hove, Denis Marcon and Stefaan Decoutere
imec, Kapeldreef 75,3001 Leuven, Belgium Status. GaN is anticipated to be a next generation power semiconductor. With a higher breakdown strength, faster switching speed, higher thermal conductivity and lower onresistance (R on ), power devices based on this wide-bandgap semiconductor material can significantly outperform the traditional Si-based power chips. As such, GaN-based power devices will play a key role in the power conversion market within battery chargers, smartphones, computers, servers, automotive, lighting systems and photovoltaics.
In absence of viable low-cost GaN bulk substrates, GaN is grown on a variety of substrates, the most popular being sapphire, silicon carbide (SiC) and silicon (Si). Si substrates have become attractive for GaN growth because of their larger wafer diameter (200 mm and higher) though the large mismatch in lattice constant and coefficient of thermal expansion (CTE) imposes epitaxy challenges, especially for larger Si substrate sizes. Moreover, GaN devices are naturally normally-on or depletion mode (d-mode) devices, whereas, to replace commercially available Si power devices, the GaN devices should be normally-off or enhancement-mode (e-mode) devices. Furthermore, GaN devices should be fabricated by a low-cost, reproducible and reliable production process. While e-mode operation can be readily achieved by adding a p-doped GaN layer under the gate, hereby lifting the conduction band at equilibrium and resulting in electron depletion, the ability to manufacture GaN-on-Si power devices in existing 200 mm Si production facilities offers further cost competitiveness to the Si power technology.
Initially, the development of GaN-based technology focused on high voltage (200 V and 650 V) power-switching applications. The first commercial 200 V e-mode GaN devices, fabricated on 150 mm Si substrates, were released in 2010 and the first 650 V commercial devices followed in 2014 (figure 1, left). After first developing the technology on 100 mm [1,2], and later 150 mm wafer sizes using Au-free metallization schemes [3], imec has been pioneering 200 mm GaNon-Si technology with first GaN 200 V epitaxy [4] and devices in 2014 [5][6][7][8][9]. The imec 200 mm GaN-on-Si e-mode transistor and diode platform was recently extended and qualified for 650 V applications. Today, the focus is on the technology development for higher level of integration and for 1200 V applications using 200 mm CTE-matched polycrystalline AlN substrates.
Current and future challenges. Because of the much higher CTE of GaN compared to Si, the GaN in-film stress during epitaxial growth needs to be tuned compressive to compensate for the tensile stress during cool down. The use of 1.15 mm-thick 200 mm Si substrates is beneficial to reduce wafer warp during growth and hence avoiding wafer cracking. Without significant hardware changes and lowering the robot speed of some handling systems, the thicker and heavier GaN-on-Si wafers can be processed in the standard imec CMOS fab. The warp specification of 50 µm is sufficiently low to avoid chucking issues on electrostatic chucks. Prior to the fab introduction, the 200 mm GaN-on-Si wafers are tested for mechanical robustness, hereby reducing the wafer breakage during processing to less than 1%. After epitaxy, Ga and Al contamination on the wafer backside is unavoidable. Since Ga is a p-type dopant for Si, one of the major concerns of processing GaN wafers in a CMOS fab is Ga cross-contamination. The Ga and Al backside contamination after epitaxy is effectively removed by an inhouse developed HF/H 2 O 2 -based cleaning procedure, hereby reducing the contamination level of the wafer backside and bevel to below 10 11 at cm −2 . Moreover, imec's e-mode pGaN process flow contains (Al)GaN dry etch steps. A first step to dry etch the pGaN layer selectively to the AlGaN barrier layer, and a second to recess the AlGaN barrier in the ohmic contact areas. Since conventional F-containing cleaning recipes of the dry etch tools can form non-volatile GaF x species (i.e. GaF x is not volatile below 800 °C), a Cl 2 -based clean that forms volatile GaCl 3 at ~200 °C is used. This cleaning procedure effectively and reproducibly maintains the Ga contamination level in the dry etch tools well below the maximum allowed level.
Finally, since Au is a rapidly diffusing contaminant in Si that deteriorates the minority carrier lifetime, the GaN metallization schemes need to be Au-free. Because of the high bandgap and the absence of explicit doping of the epilayers, especially the development of Au-free ohmic contacts is challenging. By using a Si/Ti/Al/Ti/TiN ohmic metal scheme and decreasing the alloy temperature to 565 °C, the ohmic contact resistance could be lowered to 0.3 Ω · mm with excellent reproducibility and uniformity.
Advances in science and technology to meet challenges. Because the breakdown field of the Si substrate is ten times lower compared to GaN, the breakdown voltage of the power devices is dictated by the GaN buffer thickness. In figure 1 (right) the vertical buffer breakdown voltage (at 1 µA mm −2 leakage) is plotted versus the buffer thickness. Straightforward extension of the 3.2 µm-thick 200 V buffer (red) to 5.5 µm for 650 V applications (blue) was resulting in low wafer yield: the yield related to wafer breakage in the mechanical screening test was reduced from 90% for 200 V to 77% for 650 V. This issue was tackled by implementing Si substrates with high boron doping (0.01 Ω · cm resistivity), hereby increasing the mechanical wafer strength, and by developing a new buffer concept with reduced thickness (4.9 µm, green) that resulted in an equally high buffer breakdown voltage while maintaining the low buffer dispersion, and increasing the wafer yield for 200 V applications to 99% and to 97% for 650 V applications.
By optimization of the cleaning and dielectric deposition conditions, together with the field plate design, state-of-theart 650 V 36 mm gatewidth power devices with 2.1 V threshold voltage (at maximum transconductance), 13 Ω · mm R on and 8 A output current (figures 2(a) and (b)) were obtained on 200 mm wafer size and processed in a standard CMOS wafer fab. Moreover, the devices exhibit dynamic R on dispersion below 20% (10 µs on, 90 µs off) up to 650 V over the full temperature range from 25 °C to 150 °C (figure 2(c)).
For 1200 V power applications, imec is working on using polycrystalline AlN (poly-AlN) substrates that have a better CTE-match to GaN. In this approach, a thin crystalline Si layer is transferred to a 200 mm poly-AlN substrate. This new technology is promising to go beyond the current technology limitations, because it is possible to grow thicker, higher quality GaN buffers on 200 mm substrates with a standard thickness of 725 µm. Imec has already demonstrated the CMOS-compatibility of these substrates in terms of contamination and wafer handling [10]. Furthermore, first high quality transistors have been processed illustrating the high promise of this new approach.
Concluding remarks. GaN technology offers faster switching power devices with higher breakdown voltage and lower on-resistance than Si, making it an ideal material for advanced power electronic components. For cost competitiveness, GaN power devices are preferably fabricated on large diameter Si substrates in existing Si CMOS fabs. Due to the large mismatch in lattice constant and thermal expansion coefficient, the epitaxy of GaN on large diameter Si substrates is very challenging. Imec has demonstrated for the first time that is possible to manufacture 200 V and 650 V GaN-on-Si e-mode devices in a 200 mm CMOS fab. For 1200 V applications, it is proposed to transfer the technology to 200 mm Si-on-poly-AlN substrates, which is CTE-matched with GaN. This substrate technology allows for thicker GaN buffers, which is needed to reach 1200 V and beyond, and was also assessed to be CMOS-compatible in terms of contamination and tool handling.   Status. GaN and other III-N compound semiconductors have had an enormous impact on optoelectronics-with the widespread adoption of LEDs, lasers, and solar-blind photodetectors-as well as RF electronics for both consumer wireless infrastructure and military communications and sensing. The continuing advance of III-N electronics promises to bring this revolution also into the power electronics space. With power device concepts based both on extensions of conventional lateral FET designs, as well as concepts based on vertical transistor designs, GaN and related materials promise to dramatically enhance the performance, efficiency, and ubiquity of sophisticated power management and control functions. Advances in growth and substrate technologies for achieving high-quality material, along with improved device designs, promise to enable continued increases in device performance. In addition, novel processing techniques are also promising to provide significant performance, cost, and integration improvements. Among these processing-related advances, techniques that enable epitaxial lift-off and substrate transfer are especially attractive. Epitaxial lift-off has been demonstrated for optoelectronic applications (see e.g. [11,12]), and offers the potential for improved light extraction, a smaller device form factor, and ultimately more flexible displays as well as sensors for emerging applications such as wearables. In the power application space, epitaxial lift-off can enable substantial increases in thermal performance (through improved heat removal), electrical performance (through lower resistive losses and higher breakdown voltages), economics (through more efficient materials utilization, die size reduction, and substrate reclaim and reuse), and enhanced integrability with other electronics technologies. A range of epitaxial lift-off technologies for GaN and related materials have been demonstrated, including selective wet etching of ZnO layers [12], dry etching of epitaxial Nb 2 N layers by XeF 2 [13], mechanical exfoliation and separation using graphene or BN layers [14,15], and band gap selective photoelectrochemical etching based on wet-chemical etching of lower-band gap materials such as InGaN [11,[16][17][18]. In addition to the mechanism by which the lift-off occurs, epitaxial lift-off processes may be distinguished by whether they lift off a single device (figure 3(b)) or small circuit (e.g. [11,13]), or seek to lift off a larger film (figure 3(a)) either for subsequent processing into devices (e.g. [12,14,15]) or after fabrication of the devices is largely complete (e.g. [17,18]). Current and future challenges. Advances in power electronics are poised to radically alter the design and implementation of electronic products and systems; ultimately, sophisticated power electronics and circuit topologies for enhanced efficiency and power-control capability could become ubiquitous if the key technological and economic challenges can be solved. Realization of this vision is currently constrained by cost, device performance, and integration challenges-all of which can be addressed by epitaxial lift-off. Due to the wide diversity of potential applications there is unlikely to be a single optimal solution; instead, we can expect different approaches to benefit different application segments. For example, for modest voltage and current requirements for which lateral devices (e.g. MISHEMTs) provide sufficient performance and economic benefit, use of conventional lattice-mismatched substrates such as SiC, sapphire, or Si is appropriate; epitaxial lift-off can then be used to accomplish substrate transfer for improved thermal or breakdown performance (see e.g. [19]), as well as the potential for reusing high-cost substrates (e.g. SiC) [13]. For applications where high currents and materiallimited breakdown voltages are required, as well as applications where economics dictates a high areal current density, vertical device structures offer inherent advantages. However, these devices also place additional demands on material quality; while high dislocation densities are often tolerable in optoelectronic and lateral electronic nitride devices, these defects significantly compromise the performance of vertical devices. This can be addressed by homoepitaxial devices on (a) Figure 3. (a) Large-area (100 mm wafer) epitaxial lift-off of GaNbased epitaxial device layers achieved using band-gap selective photoelectrochemical wet etching of an InGaN [17]; (b) single-die release of a GaN-based device using dry etching of Nb 2 N with XeF 2 [13]. (a) [ bulk GaN substrates, but this in turn places more stringent demands on the epitaxial lift-off approach to avoid the generation of dislocations. The economic benefits of epitaxial lift-off from bulk GaN substrates are substantial, given their high cost and small diameter. In addition to substrate reuse, thermoelectric modelling indicates that direct bonding of lifted-off vertical FETs to a heatsink could enable die size reduction by more than 50% compared to devices on bulk GaN substrates [18]. Of the current techniques, only band gap selective photoelectrochemical etching with pseudomorphic InGaN release layers has been demonstrated to maintain fully coherent single-crystal material from the bulk substrate through the device epitaxial layers, and so may provide a unique solution to achieving epitaxial lift-off of vertical devices on bulk GaN substrates. Reuse of bulk GaN substrates after lift-off has recently been demonstrated with lift-off of GaN pn junctions (figure 4) demonstrating a pathway to improved economics; future efforts will be needed to fully realize the thermal and integration benefits.
Advances in science and technology to meet challenges. To address the challenges and fully realize the benefits of epitaxial lift-off as an enabling technology for high-performance, low-cost, ubiquitous power electronics, significant technological challenges must be overcome. For material-quality sensitive applications such as vertical devices, additional development of lattice-matched or pseudomorphic release layers is an important future direction. Current demonstrations have been based on the use of InGaN release layers [11,[16][17][18]; while this approach has been successfully demonstrated for both single-die release and lift-off of large areas (>100 mm wafer), the lateral etch rate is modest and the surface morphology of the N-face GaN is not yet easily controlled due to limited etch rate selectivity. Additionally, the use of pseudomorphic release layers such as InGaN have been reported to influence the mechanical behaviour of released structures [20]. Development of strain-control strategies or deposition of alternative release layer materials with basal plane lattices commensurate with the GaN devices are areas for future development and exploration. Another area that is largely unexplored to date is that of novel packaging and bonding strategies to leverage the unique features of devices fabricated using epitaxial lift-off. The thermal performance of ultra-thin devices has been projected [18], but experimental validation and-in par ticular-optimization for the unique characteristics of ultra-thin devices is an area for additional development. Heterogeneous integration of liftedoff devices with conventional electronics, and packaging of lifted-off devices for emerging applications such as flexible or ultra-thin form factors is another area where substantial additional innovation is needed. Finally, the reliability of lifted-off devices is an important topic, but one that has not yet been addressed due to the nascence of the technology.
Concluding remarks. Epitaxial lift-off is an emerging technology that is poised to be of significant benefit to the developing field of III-N based devices, and in particular to high-performance, cost-effective power electronics. The improvements in electrical and thermal performance, economic benefits derived from reduced die size and bulk GaN or SiC substrate reuse, and potential for enhanced heterogeneous integration with other electronics and packaging technologies makes epitaxial lift-off appear promising for advancing power electronics across a broad range of applications.  Status. The main objective in the LETI [21] power electronic roadmap is the miniaturization of power converters to increase the energy efficiency of the systems while reducing the cost. It is also important to improve reliability and ensure operation at higher temperatures (300 °C), with the markets of automotive (EV and HEV) and motor drives for industrial tools being targeted. To achieve these objectives for power convertors from a few watts to several hundred kW, it is essential to increase their operating frequency [22]. GaN-on-Si power devices are capable of responding to these requirements because GaN allows high frequency switching (several MHz) and a higher power density than silicon (10 times greater), although these solutions must be implemented at the system level in order to fully benefit from the materials properties. Furthermore, GaN on 200 mm Si enables CMOS compatible technology leading to lower cost and improved robustness of the processes. LETI has chosen to develop MOS Channel HEMT (MOSCHEMT) GaN architecture, fabricating 'normally-off' devices which give functionality similar to a classic silicon based MOS. To take full advantage of these devices, a route towards monolithic solutions for low and mid power applications and a route towards system in package are promoted at LETI, figure 5, with five main axes of work: epitaxy, devices, passives, co-integration, and system architectures. Here, we will focus on the device roadmap.
Current and future challenges. Adoption of GaN in the industry requires high performance, high reliability devices produced at low cost. For automotive applications, GaN transistors of 1200 V-50 A and 650 V-200 A are targeted. Current requirements are a R on S below 1 mohm · cm 2 , figure 6, with an R dyn of no more than 10% of the R on S, meaning low losses [23]. The epitaxy is expected to improve in several ways: firstly, a constant improvement in the buffer layers and active layers to decrease the dislocation density, even though this has not been proven to be essential for high quality HEMT performance, and a reduction in point defects which cause trapping; secondly, a vertical leakage current lower than 1 µA mm −2 at 150 °C, and thirdly improvements and optimisations in the design of the epi stack, such as integration of back barriers to improve confinement of the free carriers in the potential well. Of course, all this has to be implemented while maintaining a wafer bow <50 µm for a silicon wafer thickness of 1 mm maximum to enable the process in standard 200 mm tools [24].
The most developed structure to make normally-off GaN HEMTs is pGaN gate architecture. P-type GaN may have a potential work function of up to 7.5 eV which makes pGaN, in a sense, an outstanding gate metal in addition to the depolarization effect for depleting the channel beneath the gate. However, this design suffers from a compromise between the threshold voltage and the sheet resistance in the channel and so high positive threshold voltages are difficult to achieve. This is why at LETI we are developing an alternative strategy, the MOSCHEMT. This architecture is a hybrid monolithic device which essentially puts a MOS channel and a HEMT drift layer in series. At the heart of this technology is the MOS gate, which needs to be reliable and robust; a challenge that Si and SiC have already faced in the past.
Advances in science and technology to meet these challenges. The advances required to meet the challenges listed above can be described in five bullet points: Simulation: to design complex architectures, capture process influence and describe device behaviour, simulations such as TCAD [25] are of major importance. Currently, significant efforts are needed to ensure simulators properly recreate the physics of III-N materials and devices.
Device characterisation: the JEDEC standards are not sufficient to fully qualify GaN-based power devices due to restrictive criteria. Dynamic properties and aging effects, which show common patterns with dielectric aging, are key topics to be understood in order to bring GaN-on-Si products to industrial maturity in mass markets.
Device technology: as discussed above, constant improvements are required in the epitaxy, with in particular improved defect characterization and analysis of their impact on device performance. The understanding of the gate oxide trap passivation will also be a significant scientific and technological challenge. The whole technology has to be CMOS compatible, which brings an additional constraint to GaN power device design, and the potential of GaN on 300 mm Si has to be investigated.
Thermal dissipation: the reduction in size of power devices when using GaN raises the challenge of thermal dissipation. In order to benefit from the full potential of GaN technology, the power density will need to be increased, and so process and packaging will need to be optimised to improve thermal dissipation.
Switching frequency: to allow high frequency switching, cointegration is key. Transistors, flyback diodes, rectifiers [26] or drivers [27] are examples of active devices that can be monolithically integrated to reduce parasitic elements and reach high performance converters.
Concluding remarks. The use of GaN-on-Si as a substrate for high power transistors is becoming an increasingly common choice, as an affordable large area alternative to expensive bulk substrates. Although there are still significant challenges to be overcome in order to produce high quality devices on these substrates, GaN devices will take full advantage of both the remarkable properties of GaN, and of production in CMOS compatible fabrication plants to achieve high performance and low cost devices.
Furthermore, the development of high power integrated circuits on GaN on silicon wafers will further reduce costs and encourage the use of this technology. With all of these advances, it will surely not be long before GaN-on-Si devices become a huge market as the demand for highly energy efficient convertors becomes ever greater.   Status. Uptake of GaN devices for power applications requires that they can be manufactured in volume at comparable cost to Si components, and with validated device reliability. The key innovation that has made this possible is the ability to grow epitaxial device quality layers of GaN and AlGaN on 6″ or 8″ (1 1 1) Si wafers. Together with the development of Si CMOS compatible device process flows, this has allowed GaN power devices to be fabricated using existing Si fabrication lines with Si and GaN processing occurring in parallel. This section addresses the electrical and material design of the GaN-on-Si epitaxial platform that is now being used to realise HEMT devices for power applications.

Buffer design in GaN-on-Si power devices
GaN HEMTs were first successfully grown on Si in the 1990s, however the epitaxy did not have sufficient breakdown voltage for power applications. GaN-on-SiC RF devices used Fe doping to suppress short-channel drain leakage and increase drain breakdown, representing the first realization that the nominally insulating GaN layer underneath the 2DEG channel is actually electrically active and needs just as much design and optimisation as the upper barrier and channel region. However, Fe doping was found to deliver insufficient breakdown voltage when applied to high voltage power devices. Eventually, it was found that a combination of a complex strain relief buffer together with carbon doping to control breakdown could achieve sufficient voltage handling [28]. Unfortunately, there continued to be bulk trapping related issues collectively known as dynamic R ON dispersion or current collapse, and their solution has only recently been demonstrated commercially. The reasons for the wide variation in dynamic R ON performance achieved for apparently identical carbon doped epitaxies are only now becoming understood.
Current and future challenges. Key issues in epitaxial growth of GaN-on-Si are the lattice and thermal expansion coefficient mismatches which make strain management critical. As a result, large numbers of defects (>10 10 cm −2 ) are generated, and cracking of the GaN layers can occur on cooling from the growth temperatures (≈1000 °C) [29]. The epitaxial layer structure which has been adopted to solve these issues is shown in figure 7. A nucleation layer of AlN is universally used to initiate growth and avoid the Ga/Si eutectic that causes 'melt-back'. This is followed by a strain relief stack, where two successful approaches have been found based on either a step-graded AlGaN layer [30], or a superlattice of AlN/GaN [31]. The detailed stack design is normally proprietary. These buffers are used to induce compressive strain during growth which counteracts the tensile strain introduced on cooling, preventing cracking and yielding a flat wafer. To aid growth uniformity, thick Si substrates (1 mm) tend to be adopted, which also helps to reduce the wafer breakage during processing which has been observed for standard thickness wafers (675 µm). Total epi-layer thickness as large as 8 µm can be achieved, but the challenges of wafer bow and stress become more difficult to overcome. Typical dislocation densities at the surface of the stack, i.e. at the 2DEG, are ≈10 9 cm −2 .
Due to the incorporation of impurities and point defects, as-grown GaN is typically n-type and it has been found that it is essential to add deep level dopants to suppress leakage. The dopant of choice is carbon [28] with a density well above 10 18 cm −3 delivering excellent isolation and breakdown voltage. Carbon primarily incorporates substitutionally on the nitrogen site [32]. This pins the Fermi level about 0.9 eV above the valence band making the GaN:C p-type, with electrical transport being via low mobility holes rather than electrons. It is found that the carbon doping must be spaced away from the active 2DEG to reduce trapping effects [33]. A key issue with carbon doping is current collapse (dynamic R ON ) [34]. Charge trapping occurs in the epitaxial bulk during off-state operation when there is high drain bias. When the device is switched on, trapped negative charge reduces the electron density in the active channel and increases the on-resistance. Some current commercial devices show as much as a factor of two increase following off-state bias.
Advances in science and technology to meet challenges. Suppression of current collapse is key for technology uptake. The p-type nature of GaN:C means that there is a p-n junction between the 2DEG channel and the bulk of the epitaxy, meaning that the bulk can be electrically floating. Suppression requires that this floating buffer is grounded to the active 2DEG channel preventing it from providing a back bias, and hence, counter-intuitively, a vertical leakage path is essential. Figure 8 shows an electrical network representation of the buffer, and simulations to show the impact of different leakage paths [35]. It is found that there is a trade-off between vertical leakage and current-collapse, with careful process control of leakage paths being absolutely required. Current state-of-the-art power devices are able to achieve less than 10% change in R ON in the 25 °C-150 °C temperature range by careful leakage control [36]. Recently it has been shown that changing the stoichiometry of the Si 3 N 4 surface passivation can change the bulk vertical leakage and control the dynamic R ON [37]. Further work is still required to achieve a guaranteed simultaneous optimisation of leakage and current collapse.
Many power switching topologies require the series connection of devices. Current technologies would require a hybrid packaging approach to prevent an undesirable Si substrate bias being applied to the upper transistor in a halfbridge configuration. New approaches to allow transistor electrical isolation are therefore required before full integration is feasible. One approach being investigated is the use of buried oxide layers with 200 V isolation being achieved by imec.
Operating at voltages much above 650 V will require the growth of thicker epitaxy, and that requires a solution to reducing stress. Although single crystal GaN or AlN would be the ideal substrates, cost and wafer size make this unlikely to have any impact. One possible approach is the use of thermal expansion matched substrates as an alternative to Si wafers. For example, polycrystalline AlN wafers have been successfully used as a growth substrate, achieving 18 µm thick epitaxial layers.
Concluding remarks. GaN-on-Si based power transistors are already achieving impressive performance and reliability based on the remarkable ability to grow strain-engineered, electrically-optimised, high-quality epitaxy on low cost 6″ or 8″ Si wafers. Buffer-related trapping leading to dynamic R ON has been a serious issue, requiring a delicate balance between leakage and performance for its suppression. This is only now being achieved by commercial suppliers. Going significantly beyond the current 650 V market segment to much higher voltages will require major changes and innovation in the substrates and epitaxy to allow thicker epitaxial layers to be grown yet still retaining control of wafer bow.

Acknowledgments
This work was funded by the UK EPSRC PowerGaN project K0114471/1.   Status. GaN based devices are promising for many power applications such as switching functions and inverters that can save a significant amount of energy. The performance and efficiency of these GaN power devices greatly rely on the epitaxial growth of GaN and related alloys. High quality GaN epitaxial growth can be achieved by using native freestanding GaN substrates. However, the downside of epitaxial GaN-on-GaN is it is expensive and only small-diameter GaN substrates. This in turn impede the mass production of GaN power devices at an affordable cost for commercial applications. To overcome this, the heteroepitaxial growth of GaN is carried out on foreign substrates such as silicon carbide (SiC), sapphire and silicon (Si). From commercial aspects, the heteroepitaxial growth of GaN-on-Si is attractive because of the large-size scalability of inexpensive Si substrates. Nevertheless, the areas of concern are the large differences in the physical properties between wide bandgap GaN and Si substrate that often results in poor crystal quality leading to high dislocation density, pits and cracks for GaN-on-Si. Therefore, appropriate epitaxial growth of GaN-on-Si and subsequent fabrication processes are absolutely necessary for power device applications. For example, several switching applications require lateral GaN-on-Si high-electron-mobility transistors (HEMTs) with high breakdown voltage (BV) [38]. To realize these GaN-on-Si lateral devices, we have used the metalorganic chemical vapor deposition (MOCVD) grown thick-AlN initial layer and GaN/AlN strained layer superlattice (SLS) structures. The AlGaN/GaN HEMTs grown on 8-inch silicon by using similar epitaxial growth technique delivered a high BV of 1.6 kV. For expanding the applications to electric and hybrid vehicles, high performance GaN power devices are required to drive high-power motors, power modules such as DC-DC converter and inverters. Typically, in these applications high-voltage GaN-on-Si vertical devices with reduced chip area are preferred. To facilitate the fabrication process of such devices, we have successfully grown thick GaN-on-Si vertical structures by using conductive buffer layers comprising of thin-AlN initial layer and SLS. The recent advances in the hetero epitaxial GaN-on-Si are encouraging for the growth of GaN power electronics on larger diameter Si substrates.

Challenges in growth for GaN power electronics
Current and future challenges. Despite their merits, GaNon-Si power devices have also associated technical challenges which need attention. Of these, the most important issue is the growth of a high-quality and thick GaN-on-Si. The large differences in lattice constants and thermal expansion coefficient between GaN and Si are responsible for the difficulties in the growth of high-quality and thick GaN-on-Si. The inset of figure 9 shows the cross-sectional structure of AlGaN/GaN HEMT on Si using metalorganic chemical vapour deposition (MOCVD). High temperature growth of GaN-on-Si could likely result in melt-back etching of Si substrate caused by Ga atoms [39]. As a result, deep pits, dislocations and cracks could arise, which in turn would deteriorate the device performance like an increase in buffer leakage, and reduced breakdown [40]. Therefore, the growth of high-temperature-grown AlN nucleation layer (NL) is indispensable to avoid both the melt-back etching and deep pits. Recent studies have revealed the influence of AlN NL on the vertical breakdown characteristics for GaN-on-Si and the AlN NL with better surface morphology and lower O impurity were preferred to grow highly resistive buffers [41]. Figure 9 illustrates the typical relationship between wafer bowing and total epitaxial thickness for the AlGaN/GaN HEMT on 4-inch Si. From this correlation, it could be understood that the use of GaN/AlN SLS is effective in controlling the bowing [42]. Subsequently, the growth of SLS is essential to control the wafer bowing for GaN-on-Si. Additionally, thick epi layers grown by using SLS multipairs supressed the vertical leakage and showed a vertical breakdown field of 2.3 MV cm −1 [43]. A high lateral BV Off of 1.4 kV was also demonstrated for AlGaN/GaN HEMT on Si grown with the above recommendations [44]. The recent systematic investigations and the promising results as discussed earlier would provide substantial understanding for the growth dynamics of epitaxial GaN typically on 8-inch Si substrates. Indeed, our AlGaN/GaN HEMT on 8-inch Si has shown a three-terminal off-state breakdown voltage 1650 V for the gate-drain distance of 50 µm. The availability of modern MOCVD reactors with multi-wafer capability and evaluation tools suggest promising features for GaN-on-Si lateral power devices.  [42].

Advances in science and technology to meet chal-
lenges. GaN-on-GaN vertical devices are expected to play a vital role in future high-power conversion applications as it can reduce the overall chip area. However, GaN substrates have disadvantages such as limited wafer size and being expensive. Therefore, the realization of GaN-on-Si vertical devices is the upcoming challenge owing to growth and fabrication difficulties. Unlike the lateral AlGaN/GaN devices, a deeper understanding on the growth and fabrication of GaN-on-Si vertical devices is required for potential power device applications. Some researchers have demonstrated GaN-on-Si vertical p-n diodes fabricated by wafer bonding and substrate removal technology [45]. This technique could complicate the fabrication process and eventually lead to increase in cost. Others showed GaN p-n diodes by using a quasi-vertical structure [46]. Irrespective of these methods, a detailed study is required for the growth of GaN-on-Si vertical structures that should complement the fabrication as well.
To realize such a GaN-on-Si vertical device, (i) the doping density (N d -N a ) in the drift region must be controlled and (ii) the buffer layer should be conductive. Figure 10 represents the net N d -N a in the drift region as a function of SiH 4 flow rate for a GaN-on-Si grown with two SLS thicknesses. As shown, the N d -N a could be controlled for GaN-on-Si by increasing the SLS multipairs, which is due to the reduction of dislocation density. The conductive buffer layers including the AlGaN/ AlN layers and SLS are indispensable for realizing GaN-on-Si vertical devices. Therefore, a Si-doped AlN NL as thin as 3 nm was initially deposited followed by the deposition of Sidoped AlGaN and SLS. This novel fully vertical GaN-on-Si p-n diode comprises of doped buffer layers and not involve substrate removal technology. This GaN-on-Si p-n diode has ohmic contacts on the p-GaN layer and a backside of n + -Si substrate that showed a turn-on voltage of 3.4 V and a breakdown voltage of 288 V for the 1.5 µm-thick n − -GaN drift layer [47]. The BV can be further improved by increasing the buffer thickness and/or by using field plate structures. These improvements in the MOCVD growth of GaN-on-Si vertical structures suggest their potential role in power electronics in near future.
Concluding remarks. GaN-on-Si power devices are emerging to play a dominant role in the next-generation power electronics. Significant improvements in the hetero epitaxial growth and device fabrication are indispensable for the commercialization of these power devices. For the epitaxial growth of GaN-on-Si lateral devices, we have utilized the high temperature AlN NL to prevent the melt back etching of Ga into Si. It was also found that the growth of SLS is essential to control the wafer bowing for GaN-on-Si. In addition, the growth of SLS multipairs effectively enhanced the breakdown volt age of GaN-on-Si HEMTs. On the other hand, fully-vertical GaNon-Si p-n diodes were demonstrated by using conductive buffer layers. We have used AlN NL as thin as 3 nm and SLS multipairs, both highly doped in order to realize fully-vertical GaN-on-Si p-n diodes. These advancements in the MOCVD growth of GaN-on-Si and device fabrication processes will lead to the high-performance power electronics.

Acknowledgment
The authors would like to thank the Super Cluster Program of the Japan Science and Technology Agency.  Status. Central to improving the efficiency of power electronics is the availability of low-cost, efficient and reliable power switching devices. GaN-based devices are exciting candidates for next-generation power electronics. Currently, both lateral and vertical structures are considered for GaN power devices. Vertical GaN power devices have attracted significant attention recently, due to the capability of achieving high breakdown voltage (BV) and current levels without enlarging the chip size, the superior reliability gained by moving the peak electric field away from the surface into bulk devices, and the easier thermal management than lateral devices [48].

Vertical GaN power devices
Since 2010, the field of vertical GaN power devices has grown exponentially and seen numerous demonstrations of vertical diodes and transistors (figure 11). A 3.7 kV vertical GaN pn diode [49] and a 1.1 kV vertical GaN Schottky barrier diode (SBD) [50] have recently showed near-theoretical power figure of merit. Trench metal-insulator-semiconductor barrier Schottky diodes [51] (figure 12(a)) and junction barrier Schottky diodes [52] (figure 12(b)) have also been proposed to combine the good forward characteristics of SBDs (e.g. low turn-on voltage) and reverse characteristics of pn diodes (e.g. low leakage current and high BV).
Several structures have been proposed for vertical GaN transistors, with the highest BV close to 2 kV. Current aperture vertical electron transistor (CAVET) combines the high conductivity of a two-dimensional electron gas (2DEG) channel at the AlGaN/GaN heterojunction and the improved field distribution of a vertical structure [53] (figure 12(c)). The CAVET is intrinsically normally-on, but a trench semi-polar gate could allow for normally-off operation [54] (figure 12(d)). Vertical GaN trench MOSFETs have no 2DEG channels, but do not need the regrowth of AlGaN/GaN structures and are intrinsically normally-off [55] (figure 12(e)). Recently, vertical fin MOSFETs have been demonstrated to achieve normally-off operation without the need for p-type GaN materials or epitaxial regrowth [56] (figure 12(f)).
While most vertical devices utilize expensive GaN substrates, it is also feasible to make vertical GaN devices on low-cost Si substrates. Quasi-and fully-vertical GaN-on-Si vertical diodes have been demonstrated with a BV over 500 V and excellent high-temperature performance [46]. These devices can enable 100-fold lower substrate and epitaxial cost than GaN-on-GaN vertical devices.
Current and future challenges. In spite of the great progress, the full potential of vertical GaN SBDs and transistors has not been exploited yet. The BV demonstrated in these devices, with no avalanche capability reported, is still much lower than the avalanche BV in vertical GaN pn diodes. The lack of avalanche capability would greatly compromise the device robustness when operating in inductive switching environments. Although the nature of avalanche breakdown is still not fully understood in GaN devices, a key factor is believed to be good edge termination technologies and a way to remove holes from the structure. In SiC power devices, successful edge termination technologies, such as junction termination extension and field rings, was enabled by selective p-type doping. However, in GaN devices, the current selective area doping or selective area epitaxial regrowth technologies cannot yield material of sufficiently high quality to enable defect-free patterned lateral pn diodes. In particular, p-type implantation and activation in GaN is far from mature. With complicated activation annealing schemes, the activation ratio for acceptors is typically below 5%, resulting in very low concentration and mobility for the activated free holes [52].
There remain some open questions on the selection of carrier channels in vertical GaN transistors to improve the device forward characteristics. The ideal channel for these devices would have normally-off configuration with high carrier mobility and without the need for epitaxial re-growth. Further work is needed for all the three channels reported so far, 2DEG channel [53], MOS inversion layer [55] and bulk fin channel [56].
The commercialization of vertical GaN power devices has been hindered by the high cost of bulk GaN substrates. The mainstream GaN substrates are 2-inch, while 4-and 6-inch GaN substrates are available very recently in small volumes. The wafer cost (per area) for 2-inch GaN-on-GaN is $60-$100/cm 2 , still much higher than the cost for 4-inch SiC (~$8/cm 2 ) and 8-inch GaN-on-Si (~$1/cm 2 ). The fundamental challenge is how to achieve the material quality associated with free-standing GaN substrates, while allowing the devices to be transferred to alternate substrates and have the GaN substrates re-used to reduce cost.
Advances in science and technology to meet challenges. Different technological solutions can be envisioned to address the challenges in making patterned lateral pn junctions for edge termination structures. For example, compared to p-type ion implantation, n-type ion implantation (e.g. Si, N, etc) and activation is much easier. Lightly-doped p-GaN edge terminations has been then demonstrated by implanting donors to compensate highly-doped p-GaN layers in vertical GaN pn diodes [49]. Patterned pn junctions have also been reported by n-type ion implantation into epitaxially grown p-GaN regions [52]. Besides selective ion implantation, patterned pn junctions can be also made by selective p-GaN regrowth to fill n-GaN trenches. The initial feasibility of this approach has been demonstrated in CAVET [53], although much more work is needed to study the regrown interface quality and passivate parasitic leakage currents.
In parallel, different electrical, mechanical and chemical techniques are under development to enable devices to be lifted off from native GaN substrates and transferred to low-cost substrates. Successful layer transfer technology, combined with patterned interconnections on the supporting substrate and re-use of GaN substrates, should greatly reduce the cost and pave the way to commercialize high-performance vertical GaN power devices.
Another approach that can fundamentally circumvent the cost issue of vertical GaN devices is to fabricate them on Si substrates, which could allow for almost 100-fold lower wafer and epitaxial cost as well as 8-inch fabrication. Recently, GaN-on-Si vertical pn diodes with blocking capability of 500-600 V have been demonstrated [46]. Fully-vertical GaNon-Si power devices have also been demonstrated by different technologies, such as layer transfer, conductive buffer layer, and selective removal of the substrate and buffer layer. To improve the performance of these devices, advances in epitaxial growth technology are needed to enable thicker GaN layers with very low background carrier concentration (<10 16 cm −3 ) on Si substrate.
Concluding remarks. Vertical GaN devices are key to achieve the high currents (>100 A) and voltages (>600 V) required by many power applications, such as electric vehicles and renewable energy processing. Record performance near the theoretical Baliga figure of merit has been demonstrated in vertical GaN pn diodes, although more work is needed in vertical Schottky barrier diodes and transistors. Exciting research opportunities exist in the field, especially in making patterned pn junctions, recycling GaN substrates and developing vertical GaN devices on Si substrates.  Status. GaN-based insulated gate field-effect transistors with an insulating gate dielectric provide many desirable properties such as suppressed gate leakage and large gate voltage swing [57]. These devices are typically in the form of metalinsulator-semiconductor HEMT (MIS-HEMT) or MIS-FET with the insulating dielectric on a heterojunction (e.g. AlGaN/ GaN) channel or a GaN channel, respectively, as illustrated in figures 13(a) and (b). The MIS-HEMT was first studied for RF/microwave power amplifier applications [58], and then intensively investigated as a promising power switching device. The MIS-gate transistors are especially attractive to high-frequency power switching applications because they can better tolerate gate voltage over-shoot that often occurs in circuits with high slew rate.

GaN insulated gate field-effect transistors
As is the case of Si-and SiC-based MOSFETs, the gate dielectric in GaN insulated gate FETs is required to deliver a dielectric/III-nitride interface with low trap density, high reliability and long lifetime under various stresses (e.g. electrical, thermal, humidity, etc). GaN MIS-HEMTs typically exhibit depletion-mode (D-mode) operation with a large negative threshold voltage (V th ) because of the presence of highdensity positive polarization charges in the barrier layer (e.g. AlGaN). The D-mode MIS-HEMT, with its gate (input) terminal seldom forward biased during circuit operation, typically exhibits less adverse effects from the gate dielectric. This is mainly due to the presence of the barrier layer that decouples the 2DEG channel from the interface/border traps in the dielectric as long as the 'spill-over' of electrons toward the dielectric does not occur, leading to small V th hysteresis. Very good gate reliability [59] has been obtained in D-mode MIS-HEMTs featuring a thin gate dielectric layer (SiO 2 , Si 3 N 4 or high-κ dielectrics) under relatively small forward gate bias.
Enhancement-mode (E-mode) MIS-HEMTs and MIS-FETs with a positive V th are highly desirable from the circuit application point of view for their simpler gate control circuitry and fail-safe operation. To fully turn on the channel current, however, large positive forward gate needs to be applied. This is when the gate dielectric is under the most demanding operational conditions (e.g. high electric field, charge injection to the dielectric and carriers leaking through the dielectric). V th -instability (both static and dynamic) at different temperatures and bias stress conditions, and its impact on dynamic on-resistance (R ON ), needs to be systematically studied and clearly understood [60,61]. The time-dependent dielectric breakdown (TDDB) is the ultimate hurdle to overcome before commercialization of E-mode GaN-based MIS-HEMTs and MIS-FETs.
Current and future challenges. Trap states at the di electric/ III-nitride interface and inside the dielectric present the biggest challenges to GaN MIS-HEMTs and MIS-FETs [62]. With a wide bandgap in GaN, a large energy window is available to accommodate interface and bulk trap states at shallow and deep energy levels with short and long emission time constant τ it . The dynamic charging/discharging processes of these traps could lead to V TH instability during a switching operation, and consequently affect circuit and system stability.
Unlike Si on which highly uniform and highly reliable thermal oxide can be prepared using high-temperature (800 °C-1200 °C) furnaces, GaN surface becomes unstable when the ambient temperature exceeds 800 °C. In addition, the Ga-O bonds at an oxide/III-nitride interface fundamentally induce high-density gap states, except in a few very specific crystalline oxide configurations, according to a first-principles calculation study [63]. Thus, removing the detrimental Ga-O bonds at the GaN surface is a critical step for obtaining low interface trap density (D it ). If oxide-based gate dielectric is to be used for their high dielectric constant and large bandgap, a non-oxide (e.g. nitride-based) interfacial layer would be highly desirable.
Although there are many reports on E-mode GaN MIS-HEMTs and MIS-FETs in research literature, the commercialization of these devices has been hindered by concerns over the gate dielectric reliability. The commonly used gate di electric (SiN, SiO 2 and Al 2 O 3 ) is deposited by PECVD or ALD (atomic layer deposition) at relatively low temperature (at 300 °C-400 °C). While the low temperature helps maintain GaN surface morphology, it is also the main reason for high-density defects in the dielectric, making it difficult for these devices to pass reliability tests and qualifications.
High-temperature annealing only shows a moderate effect on enhancing the dielectric reliability. Thus, it is of critical importance to develop high-temperature gate dielectric films (e.g.~ 800 °C or above) with lower defect density and longer TDDB lifetime. The biggest challenge to high-temperature dielectric on GaN is the degradation (via decomposition or chemical reaction) of GaN surface at high temperatures. A possible solution could feature a low-temperature interface protection layer and high-temperature gate dielectric.
Advances in science and technology to meet challenges. The first D-mode GaN MIS-HEMT was demonstrated using PECVD-SiO 2 as the gate dielectric [58]. With MOCVD-grown in-situ SiN x as the gate dielectric, low D it and excellent gate reliability are obtained [59]. At 10 years, for a 100 ppm failure rate, a V gs_max of ~3.1 V is extracted, which is well above the operating V gs for a D-mode MIS-HEMT (V gs_max = 0 V).
The first E-mode GaN MIS-HEMT was demonstrated using PECVD-SiN x deposited on fluorine-implanted AlGaN/ GaN heterojunction [64]. Low-damage and well-controlled dry and digital etching techniques are being developed to obtain positive threshold voltage. E-mode partially recessed MIS-HEMTs and fully MIS-FETs have both been developed with low on-resistance, high saturation current, small V th hysteresis and low dynamic on-resistance. In particular, in situ removal of native oxide and consequent nitridation by lowpower plasma (as illustrated in figure 13(c)) prior to dielectric deposition [65] are important techniques for producing highquality dielectric/GaN interface by passivating the dangling bonds while introducing minimum gap states.
To achieve high gate dielectric reliability under large positive gate bias required for E-mode insulated gate FETs, SiN x deposited by LPCVD (low-pressure chemical vapor deposition) has emerged as a compelling candidate as it possesses several important benefits including large conduction band offset with GaN (ΔE c ~ 2.3 eV), relatively high dielectric constant (κ ~ 7) and especially the long TDDB lifetime as a result of the low defect density achieved at high deposition temper ature (e.g. 780 °C). Implementing the LPCVD-SiN x gate di electric in recessed-gate E-mode MIS-HEMTs and MIS-FETs has been more challenging since an etched GaN surface suffers more severe degradation than an as-grown GaN surface at high temperatures. An effective approach to suppress such a degradation while maintaining low D it (10 11 -10 12 cm −2 eV −1 ) has been developed using a lowtemper ature PECVD-SiN x thin film as an interfacial protection layer [66], as depicted in figure 14. For a 10-year lifetime, the maximum gate bias is determined to be 11 V at a failure rate of 63.2% and 9.1 V at a failure rate of 0.01%.
Concluding remarks. There is strong demand for GaN insulated gate field-effect transistors with both depletion-and enhancement-mode operations, as the insulated gate provides strong immunity to control voltage spikes and could be driven with circuits very similar to those used for the mainstream Si and SiC power MOSFETs. The most critical need of a GaN insulated gate FET technology is a gate dielectric technique that simultaneously delivers low interface/bulk trap density and robust reliability under stringent electrical and thermal stresses. The E-mode GaN MIS-HEMTs and MIS-FETs are especially challenging as they operate under large positive gate bias and the recessed-etched GaN demands better protections during high temperature processes associated with highquality dielectric deposition. Combining low-temperature interfacial layer with high-temperature gate dielectric could be a promising pathway toward reliable and stable GaN insulated gate FETs. Status. Reliability is essential for the application of GaN power devices to critical electronic systems, for high-voltage energy conversion, control of electrical engines, automotive electronics [67]. GaN is a robust material, capable of withstanding extremely high electric field and temperature; in order to fully exploit its potential, deep levels effects and failure mechanisms induced by high voltage and high temperature stress must be known in detail.
Several technological options are available for the fabrication of GaN power high electron mobility transistors (HEMTs): Schottky-gate normally-off transistors, which have the simplest structure, are prone to higher leakage current with respect to their insulated-gate counterpart; nevertheless they can reach breakdown voltages higher than 1100 V and can achieve normally-off operation in conjunction with a Si MOS driver in cascode configuration [68]. Normally-off devices can be achieved using p-type AlGaN or GaN with high acceptor doping on top of the AlGaN [69]. Recessedgate metal-insulator-semiconductor devices (MISHEMT) enable operation at positive gate bias without measurable gate current I G [70]. Normally-off operation can be achieved by decreasing the thickness of the AlGaN layer under the gate in a recessed structure.
The different structures can be affected by specific failure mechanisms. When biased in off-state at high reverse bias, Schottky-gate, normally-on HEMT were subject to a significant and progressive increase of gate leakage current (several orders of magnitude), correlated with the onset of leakage current paths which can be detected by electroluminescence (EL) [71]. Further analysis revealed that this catastrophic increase of I G was time dependent, that time to failure depended on the electric field, followed a Weibull distribution, and decreased slightly with temperature (activation energy = 0.12 eV). I G increase was attribute to the formation of a conductive percolation path across defects [72]. This concept of GaN as a 'lossy dielectric' was a major breakthrough for GaN reliability: it allowed the extrapolation of device lifetime using standard time-dependent dielectric breakdown (TDDB) tests, and promoted the study of other GaN time-dependent failure mechanisms, described in the following.
Current and future challenges. Time dependent breakdown effects in Schottky gate devices were due to different physical mechanisms either related to device design or materials quality: (i) in normally-on power Schottky HEMTs with double field-plate, TDDB was found to be due to the failure of the insulating SiN layer between the two-dimensional electron gas (2DEG) and the first field-plate edge. Increased robustness was achieved by changing the substrate conductivity in order to move the 2DEG edge towards the drain [68]; (ii) in AlGaN/GaN power Schottky diodes, breakdown involved first the dielectric at the diode edge and then the AlGaN; as a consequence, lifetime improves by adopting either a thicker plasma-enhanced atomic layer deposition (PEALD) SiN edge-termination dielectric (from 15 nm to 25 nm) or a more robust one (25 nm in situ SiN) [72]; (iii) drain-source off-state catastrophic breakdown of n-on Schottky gate HEMTs, may occur as a consequence of hole trapping and accumulation at the source edge of the gate: trapped positive charge shifts threshold voltage towards negative values and turns on the device while a high drain voltage is applied, thus resulting in device burn-out [73]. P-gate devices (either with an ohmic or a Schottky metal contact on top of the p-layer) are currently the most popular choice for n-off devices. A critical mechanism for p-gate HEMTs is the TDDB consequent to the application of a positive gate bias ( figure 15, left). In the case of a rectifying contact on p, positive bias leads to increased electric field, potentially leading to breakdown. Time to failure decreases at increasing gate leakage current and consequently at higher temperature (E a = 0.5 eV); times to failure are Weibull-distributed. Higher Mg doping in the p-layer reduces leakage current and therefore improves lifetime (figure 15, right). A possible explanation consists in the accumulation of positive charge at the interface with the AlGaN, proportional to leakage current which, at its turn, enhances gate current and promotes further degradation. A second hypothesis implies the formation of a percolation path, consequent to defects formation due to hot carriers (collected by the gate). In this case also, times to failure are Weibull-distributed; a 20-year lifetime at V GS = +7.2 V was demonstrated for a 200 V n-off technology [69].
The vertical drain-substrate stack also sustains a high electric field and is prone to time-dependent breakdown: a 200 V n-off technology was submitted to tests at V D-substrate in excess of 700 V and failed due to vertical burnout in approximately 2 × 10 4 s ( figure 16(a)). As shown in figure 16(b), higher leakage current and temperature correspond to a shorter lifetime, with a decrease which is thermally activated with a 0.25 eV activation energy. The maximum applicable volt age for a lifetime of 20 years with 1% failure rate is about 560 V at RT, considerably higher than the operating voltage [75].
The GaN MISHEMT represents an ideal structure for normally-off power GaN electron devices since the dielectric layer reduces significantly the gate leakage; unfortunately the MIS structure introduces new reliability problems, related with the stability of device threshold voltage. Large positive V th shifts (positive bias temperature instabilities) have been observed under forward gate bias conditions and attributed to accumulation of electrons at the dielectric/III-N interface where a second electron channel forms in the so-called 'spill-over' conditions [76]. According to [76], the density of interface states of any dielectric is currently high enough to completely deplete the 2DEG channel with a typical electron density in the order of 10 13 cm −2 . Improvements therefore require either a reduction of interface states or an increase of the voltage required to induce the 'spill-over'.
Negative voltage shift (NBTI), observed when negative volt age is applied to the gate is usually less severe, and becomes relevant only at high temperature (activation energy 0.37 eV, see [70] and reference therein). According to [70], NBTI is due to detrapping of states at the SiN/AlGaN interface; authors in [77] have formulated a unified model for positive bias temper ature instability (PBTI) and NBTI, which implies electron trapping/detrapping in pre-existing oxide traps that form a defect band very close to the GaN/ insulator interface. NBTI can reduce the threshold volt age of n-off devices, thus thinning the safety margin in off-state. Conversely, NBTI does not represent a critical problem for n-on devices: under cascode operation, the on/off state is controlled by the Si MOSFET; moreover, due to the leakage current of the Si MOSFET, the HEMT is always in slight semi-on state, and this limits the electric field across the SiN/AlGaN stack.
Advances in science and technology to meet challenges. Schottky-gate and MISHEMT n-on devices for cascode configuration and p-gate n-off devices are gaining maturity; time-dependent breakdown effects can be evaluated using standard, well-established testing methods; methods for long-term thermal stability assessment still have to be developed and consolidated into standards. Some issues remain, concerning gate leakage, hot electron degradation, instantaneous breakdown. Since the electric field plays a key role in the reported degradations and failures, it is important  Time to failure dependence on the initial leakage for three drain bias levels applied during the constant voltage stress [75]. © 2017 IEEE. Reprinted, with permission from [9]. to develop solutions in order to reduce its impact on the reliability issues. The regions/interfaces where the electric field reaches its maximum value often represent the weakest point of the device due to several effects: (i) the inverse piezo electric effect could bring to a catastrophic failure due to the lattice damage; (ii) hot electrons gain energy thanks to the high electric field in the pinch-off region; (iii) it has been shown that the p-gate failures are related to the electric field peak along the gate edge. Both preventing the building up of high electric field and growing high quality materials that can withstand the electrical stress are ways to improve the reliability of the devices. The quality of the passivation layer has been shown to be crucial to improve both the lifetime and the robustness, and the optimization of the materials quality is needed.
Also, the process is important and could be improved, since the etching treatment could damage the passivation layer at the gate edge, exactly where the electric field peaks in a forward gate bias condition.
Concerning n-off MISHEMTs, stabilization of threshold voltage remains an open issue, which requires in-depth physical characterization of surface and interface properties and of dielectric materials.
Since one of the targets is to increase the operating voltage over 1000 V, it is important to focus on the drain-to-substrate stack. In order to reduce the vertical leakage, the transition layers must be optimized and engineered, avoiding the defects to behave like conductive paths between the silicon substrate and the drain. It is worth noticing that these paths are the starting point which leads to the formation of the conductive percolation path leading to a TDDB behavior. Nevertheless, electric field peaks within the structure can also lead to reliability issues; smoothing the electric field at the heterointerfaces will results in a higher breakdown voltage of the vertical stack. In particular, it has been shown that this type of failure occurs within the silicon (substrate), which is the material with the lower breakdown field. A possible solution that increases considerably the breakdown voltage of the vertical stack consists in the removal of the silicon substrate removal, which, however, involves some processing complications.
Concluding remarks. This chapter has reviewed the reliability of n-on and n-off GaN power HEMTs, with particular emphasis on time-dependent breakdown mechanisms and NBTI/PBTI effects. The results described here have been obtained by means of on-wafer short-term (<100 h) tests. Knowledge on the long-term reliability of these devices is being developed only recently, thanks also to cooperative projects such as POWERBASE and InRel-Npower, which promise to achieve full maturity for GaN power technologies in the 650-1200 V range.

Acknowledgments
The work has been partially supported by Office of Naval Research project ONR N000141410647 'GaN HEMT reliability physics: from failure mechanisms to testing methods, test structures and acceleration laws', under the supervision of Dr Paul Maki. This project has received funding from the Electronic Component Systems for European Leadership Joint Undertaking under grant agreement POWERBASE No. 662133. This Joint Undertaking received support from the European Union's Horizon 2020 research and innovation programme and Austria, Belgium, Germany, Italy, Netherlands, Norway, Slovakia, Spain, United Kingdom. This article reflects only the authors' view and the JU is not responsible for any use that may be made of the information it contains. This research work was partly supported by H2020 Project INREL-NPOWER, project ID: 720527. Work partially supported by the Italian Ministry of Foreign Affairs and International Cooperation, 'Direzione Generale per la Promozione del Sistema Paese', through the Italy-Japan bilateral project 'MAGYGAN' between the University of Padova and Nagoya University (Professor Hiroshi Amano).

Xu Li, Dilini Hemakumara and Iain Thayne
James Watt Nanofabrication Centre, University of Glasgow, Glasgow, United Kingdom Status. To significantly impact the marketplace of energy efficient power switching, GaN-based transistors must be produced in high volumes at low cost. Adopting siliconbased substrates and silicon-like manufacturing approaches enables production using legacy 150 mm and 200 mm wafer facilities driving cost efficiencies. Standard silicon manufacturing approaches rely heavily on plasma processing for etching semiconductors and deposition of dielectrics and metals. These procedures need to be migrated to GaN-based mat erials and optimised to minimise process induced damage of the semiconductor layers. These can present as reductions in channel carrier concentration and mobility and therefore increased on-resistance, as well as hysteretic effects due to the formation of charge trapping states which can influence dynamic response.
As shown in figure 17(a), there are three areas where plasma processing as part of device manufacture can have a significant effect.
1-in the source-drain regions, controlled etching into the semiconductor to the same relative position compared to the device channel offers a generic solution as described in [78] irrespective of the thickness of the AlGaN barrier layer of the device. 2-in the gate-drain region, effective passivation of the semiconductor surface is vital to minimise leakage current and current collapse. A variety of dielectrics are being actively used and demonstrated encouraging performance [79,80] with further work required to fully understand the interaction between the dielectric and the semiconductor. 3-in the gate stack, a dielectric introduced between the gate metal and the semiconductor (figure 17(b)) can suppress gate leakage current. Subjecting the semiconductor to a fluorine plasma (figure 17(c)) has been shown to be effective in shifting positive the device threshold voltage [81], important for normally-off device operation. There can be issues with long term reliability of this approach however. An alternate is to perform a gate recess etch prior to gate dielectric and metal deposition ( figure 17(d))controlling the etch depth to control threshold voltage requires the use of low damage plasma based atomic layer etching approaches, such as those described in [82]. Wafer scale and wafer to wafer uniformity of these etching approaches still need to be confirmed.
Current and future challenges. Plasma processing in the source-drain region.
As reported in [77,83], plasma etching of the semiconductor layers in the source-drain region before contact metal deposition results in reduced contact resistance (0.18 Ohm mm was obtained in [83] using 'patterned' Cl 2 -based plasma etching), and reduced thermal budget (contact resistance of 0.5 Ohm mm was achieved in [78] at a contact anneal temper ature of 550 °C using a SiCl 4 -based chemistry). Driving down the thermal budget to below 500 °C opens up new opportunities for 'gate first' approaches to device realisation which may be important in improving the stability of the gate/semiconductor interface.
Plasma processing in the gate-drain region. As described in [79], passivation of the gate-drain region using low pressure chemical vapour deposition (LPCVD) of SiN x with optimal conditions had a strong effect on both current collapse and leakage currents. This is a high temperature (850 °C) process. A key property of the LPCVD-SiN x films in this study was the stress. Recently, the use of stress control in room temperature deposited inductively coupled plasma-CVD (ICP-CVD) SiN x films for surface passivation was also shown to reduce significantly leakage currents [80], therefore a key challenge at this time is to understand the underlying physical mechanisms that govern the leakage current and current collapse phenomena.
Plasma processing in the gate stack. As mentioned above, the incorporation of a gate dielectric is important to reducing the gate leakage current in GaN transistors and allows for a larger gate voltage swing, which is particularly important for normally-off devices. As reported in [84], controlling the properties of the GaN surface, in this case by removing a SiN capping layer deposited as the final stage of the wafer growth using an SF 6 plasma etch immediately prior to atomic layer deposition of an Al 2 O 3 , resulted in a 4× reduction in hysteresis to 60 mV for GaN MOS-capacitors. This work also reported the impact of the introduction of TiN into the gate stack, which resulted in a 35% increase in accumulation capacitance. Understanding of the origin of these effects will be vital to further device optimisation.
Advances in science and technology to meet challenges. Understanding the role and impact of plasma-based processing will be vital to further optimising and improving the efficiency of GaN power device operation in terms of static and dynamic on-resistance, current collapse, leakage currents and threshold voltage control. Control of the semiconductor surface, both mechanically and chemically, is a key. This can best be addressed by understanding and correlating the properties of the semiconductor surface and its interface with dielectrics and/or metals with transistor performance. Combining plasma processing equipment so that an etched wafer can be transferred directly into a dielectric or metal deposition tool is an important technological advance. This 'clustered' approach to wafer processing is relatively standard in the mainstream silicon industry-research needs to be undertaken to validate such approaches for GaN-based materials and devices for power electronics applications. A cluster tool such as that shown in figure 18 is already proving highly insightful in this regard. In addition to combined process chambers, the cluster tool shown in figure 18 also has an in situ scanning Auger capability. Clustered plasma process and metrology engines are going to be the key to unlocking the full potential of plasma processing for GaN power electronics.
Concluding remarks. Plasma processing is a vital element in the manufacture of GaN power electronics as, based on its use in the mainstream silicon industry, only plasma processing offers reproducible wafer scale and wafer to wafer etching and dielectric and metal deposition. Arguably, the GaN surface is one of the most process sensitive in the electronics industry, so its control at a chemical level is key to fully optimising device performance. Having a profound and fundamental understanding of the impact of plasma processing on the GaN surface is therefore an imperative to ultimate GaN power device realisation.

Acknowledgments
This work was undertaken as part of the UK Engineering and Physical Sciences Research Council 'PowerGaN' project (EP/K014471/1), 'Silicon Compatible GaN Power Electronics, PowerGaN'; and with support from Oxford Instruments Plasma Technology Ltd.

School of Engineering, University of Liverpool, United Kingdom
Status. The growth of ultrathin dielectric layers into GaNbased devices incorporating metal-insulator-semiconductor (MIS) structures has been extensively investigated as a method of minimising gate leakage currents, which are lost through the gate by electron tunnelling, leading to poorer power efficiency and electrical noise. For normally-off, enhancement mode devices, low off-currents are necessary to reduce the static power consumption and ensure fail-safe operation. The incorporation of various oxide or nitride dielectric materials into GaN-based heterostructures has been explored previously using a range of conversion (e.g. oxidation or wet chemical methods) and chemical (e.g. CVD or ALD) or physical vapour (e.g. sputtering or evaporation) growth processes. Regardless of the dielectric or fabrication process used, the discontinuity (see figure 19) at the resulting insulator-semiconductor interface gives rise to electrically active interface trap states. These can influence device performance, by acting as remote impurity scattering centres that can either lower the carrier mobility (µ) [85] or influence the threshold voltage (V th ) [86]. The insulator itself may also contain deleterious intrinsic charge traps. Furthermore, the insulator will have valence band and conduction band offsets with respect to the III-nitride (e.g. GaN, AlGaN, InAlN etc.) which will influence the carrier confinement properties in the semiconductor [87]. Despite these issues, both depletion-mode and enhancement-mode insulated-gate GaNbased transistors have been realised through the development of surface pre-treatments; dielectric film deposition processes; and post-deposition heat treatments [88].
Current and future challenges. The integration of insulted gate dielectric with III-N semiconductors continues to represent a significant hurdle to be overcome before E-mode MIS transistors can reach maturity. The dynamic charging of deep traps at the dielectric-semiconductor interface is associated with V th instability and long term reliability of the material system under electrical stress is uncertain. To begin to address some of these issues, gate dielectrics have been explored in the fabrication of E-mode MIS GaN-based devices. Two of the approaches explored to date include: (1) fluorine-doping which is used to passivate or neutralise positive charges at the semiconductor surface or in the dielectric itself; or (2) by recessing the gate by selectively etching the barrier layer in the region under the gate electrode. One example of F-doping via, CF 4 -plasma treatment in the gate region of an AlGaN/GaN high-electron-mobility transistor (HEMT) [89]. Exposure to the plasma implants F − ions into the AlGaN barrier and underlying GaN-channel. After application of an ALD Al 2 O 3 gate-dielectric, the F-doped semiconductor acts as a source of fluorine that diffuses into an Al 2 O 3 dielectric compensating its intrinsic positive charge. It was reported that the V th increases with gate dielectric thickness, exceeding 3.5 V for gate di electrics 25 nm thick. Using in situ fluorine-doping during ALD Al 2 O 3 deposition, we reported the control of V th in enhancement-mode AlGaN/GaN MIS-HFETS [90]. When compared to the undoped dielectric, the F-doping caused positive threshold voltage shift (see figure 20) and a reduction of positive fixed charge in the gate oxide.
A dielectric is exploited in recessed gate MIS-HEMT, to suppress gate leakage current and increase the on-state gate swing. However, in the case of E-mode MIS-HEMTs, V th hysteresis can be caused by large positive gate voltages due to 2DEG entering the deep trap states at the oxide/III-nitride interface. A demonstration of how this effect can be mitigated is through the application of an Al 2 O 3 /AlN gate stack insulator [91]. The insertion of a 2 nm thin plasma enhanced ALD AlN interfacial passivation layer yielded a device with a V th of +1.5 V, a current density of 420 mA mm −1 and an OFF-state breakdown of 600 V with low drain leakage of 1.7 µA mm −1 .
The preceding discussion has focused on n-type (2DEG) channel MIS E-mode devices, however the realisation of p-type (2DHG) devices has received less attention to date. A significant advance, in this respect, has been the demonstration of complementary metal-oxide-semiconductor (CMOS) GaN field-effect-transistor technology [92]. This landmark achievement is considered in more detail elsewhere in this roadmap. In the context of the dielectric employed, an MOCVD AlN/SiN dielectric stack was exploited as the gate oxide for both NMOS (µ e -300 cm 2 V −1 s −1 ) and PMOS (µ h -20 cm 2 V −1 s −1 ) transistors. The devices were used to demonstrate a functional inverter integrated circuit.
Significant advances have been made in the integration of gate dielectrics into III-N transistors, with the main purpose of minimising leakage currents in normally-off devices. A variety of dielectric materials have been assessed, using different deposition processes, but the main focused has been on SiO 2 , SiN x and Al 2 O 3 . The continuing challenges for E-mode MIS devices are: (1) the minimisation of charge trap densities at the insulator/semiconductor interface across the range of barrier and channel III-nitride materials; (2) minimisation of the effect charging-discharging of trap states which gives rise to V th instability; (3) minimisation of the influence of bulk and border traps within the insulator di electric itself which may impair the long term gate reliability and performance; (4) the development of processes and mat erials matched to the thermal budget of the device manufacture and the longer term in-field operating environment; (5) lastly addressing issues (1)-(4) in the context of PMOS E-mode devices [93,94].
Advances in science and technology to meet challenges. The challenges of processing dielectrics for E-mode GaN MIS-based device technology are comparable to those encountered over the last two decades in the field of silicon CMOS. Fundamentally, the processing of dielectrics requires atomic-scale control over the preparation of the semiconductor surface, followed by assembly of the insulator with sub-nanometre precision over non-planar substrates comprising of a mixture of materials. The strategies for preparing III-nitride semiconductor (e.g. GaN, AlGaN, AlInN etc) surfaces for subsequent dielectric deposition will continue further development for both NMOS and PMOS technologies. Where these are combined on the same wafer for nitride-based circuits will add process complexity. The solution to this problem will have to involve removal or conversion of any unwanted native contamination at the semiconductor surface. Ideally the semiconductor surface would be atomically planar after preparation. Various wet and dry (e.g. thermal and plasma) processes have been explored to passivate and protect the semiconductor. It seems likely that future strategies may rely more on capping the semiconductor wafer in situ at the end the III-nitride growth process to mitigate the problems associated with post-growth environmental exposure. Obvious candidates for this would be AlN-or SiN-based materials, but could include others. Alternatively, advanced strategies for the dielectric deposition process (e.g. ALD MOCVD PECVD, LPCVD or some physical vapour deposition method), would involve an in situ preparation step. As an example, one prospect might be the introduction of an atomic layer etching (ALE) step to remove unwanted native oxide/contamination. ALE could be applied to remove disordered gallium oxide/aluminium oxide residue, prior to the ALD of a 'dielectric-quality' ALD layer. To realise this, further research would be required to develop ALE chemistries for the group-III oxides and nitrides.
In addition to surface pre-treatments, there is clearly scope for the development of improved dielectrics. Alternatives to the existing candidates, future developments might target multilayer dielectric stacks to target the overall gate capacitance, whilst enhancing resistance to gate-leakage. Multilayer gate stack might also be exploited to engineer band alignments to both the underlying semiconductor and the gate contact material. Current research has identified the use of fluorine-or hydrogen-'doping' in Al 2 O 3 or SiN x , as a method of 'defect engineering' to neutralise or passivate traps in dielectric materials. There is clear scope for basic materials research to take this defect engineering further to enhance the electrical properties of gate dielectrics.
Concluding remarks. The incorporation of MIS structures within E-mode GaN transistors offers a range of device design freedoms to realise monolithic GaN power IC, with reduced parasitic inductance and more efficient power switching at high frequencies. It is foreseeable that the development of gate dielectrics will be tuned to meet three overarching challenges. Firstly, at the materials level, the dielectric stack will mitigate the effects of detrimental traps or defects within the dielectric and at the nitride semiconductor-dielectric interface, with negligible gate-leakage and maximum resistance to high-voltage electrical breakdown. Secondly, at the manufacturing stage, processing technologies will be required incorporate the dielectric into increasingly complex device architectures within the bounds of thermal budget. Thirdly, the development of dielectrics will be driven by the operational issues of life-time and reliability in the extreme environ ments experienced by GaN-based device technology.
The power GaN progression. With GaN already established as a leading material for LED/opto applications and for RF amplifiers, this wide band-gap material emerged as an interesting academic option for discrete power devices around the turn of the century. Today, discrete GaN power devices have been qualified to JEDEC standards from 80 to 650 V, using technology that has advanced from complex, costly and slow 'cascoded d-mode' implementations in highly-inductive through-hole packaging, to true single-die, e-mode devices in SMT formats [94]. However, significant system factors still exist which restrict practical switching speeds, negate the performance advantages of GaN and, as a result, have slowed market adoption.
The answer to this problem is derived from the lateral structure of GaN itself. A two-dimensional electron gas with AlGaN/GaN heterojunction gives very high mobility in the channel and drain drift region, so resistance is much reduced compared to both Si and SiC. Circa 2009, early GaN power IC technology was published from university research [95]. The ability to integrate multiple power switches on a single chip is a big advantage for GaN power ICs. Isolating substrates began with sapphire and silicon carbide, though it was clear that an ability to grow GaN onto Si substrates enabled a cost structure and an ability to use existing large-diameter wafer fabs that would be a big cost and capacity advantage. Since Si is conductive, this introduces an additional challenge, of handling the substrate potential, and the way that it interacts with the power device.
Current and future challenges-the GaN power IC. All-GaN ™ is the industry's first GaN power IC Process Design Kit (PDK), and allows the monolithic integration of 650 V GaN IC circuits (drive, logic) with GaN FETs [96]. This proprietary PDK is remarkable given the restricted device-level tool-set, e.g. no p-channel devices are available. This monolithic integration is impractical using vertical GaN, d-mode GaN or SiC technologies.
For high-frequency operation, the most critical achievement has been the monolithic integration of GaN driver and GaN FET. In discrete implementations, the exposed GaN gate is vulnerable to noise and potentially damaging voltage spikes. Even when the GaN FET is included in a co-packaged, multi-chip module, the impedance between Si driver output and GaN FET gate leads to losses and potentially unstable operation. Only a monolithic solution delivers the required speed, efficiency and robustness [97]. From the driver integration, we can then consider 'higher-order' functions of the power IC such as inclusion of logic, start-up protection, dV/dt control, dV/dt robustness, and ESD to create full-function GaN power ICs. Another major step is the combination of two FETs plus all associated drive, level-shift, bootstrap charging, and protection features (e.g. shoot-through prevention, UVLO, etc.) into a complete half-bridge power IC. Now, PWM ICs need simply to generate two, low current, groundreferenced digital signals and the half-bridge GaN power IC completes this ubiquitous building block (see figure 21).
Since the 1990s, when Si-based junction-isolation (JI) level-shifting techniques were introduced, power designers have searched for higher-efficiency and higher-frequency methods. Hybrid level-shifter techniques, e.g. capacitive-or inductive-coupling, have been introduced but the disparate semiconductor technologies used, plus complex assembly techniques meant large and expensive modules. The 650 V GaN power IC enables the true, next-generation, monolithicintegration approach and results in a level-shifter which has 10 × lower loss than Si and 3 × lower than the best-in-class hybrids.

Advances in science and technology to meet challenges.
Real-world applications. GaN is a low-loss, fast-switching material and enables a range of new high-frequency topologies to move from academic to commercial applications. Commercial devices now have blocking voltage ranging from 40 V to 1200 V. Generational improvements are driving R DS(ON) and device capacitances lower, but still far from a theoretical limit. For high voltage devices, R DS(ON) scales approximately as (L GD ) 2 . Drain-drift length is still 5× larger than the limit for 650 V devices, which means a 10× improvement in transistor area for a specific resistance value is possible and can be expected over the next 10 years.
The easy-to-use GaN power IC building block now becomes the core enabler for high frequency, soft-switching topologies such as active clamp flyback (ACF), critical conduction mode (CrCM) and totem-pole power factor correction (PFC) and LLC DC-DC circuits to enter mainstream markets [98][99][100]. Expect more system-enhancing and application specific features to be added to the power ICs, which will improve timing control, fault detection and feedback, and light-load loss reduction.
In parallel, new magnetic materials are being developed and released to production with high-efficiency operation up to 5 MHz. Multi-MHz DSP controllers are available for higher power applications and new high-frequency, costeffective ASICs are being introduced to enable adoption in price-sensitive markets such as smartphone and laptop chargers. Soft-switching circuits in the 5-10 MHz range frequency with simultaneous increase in efficiency deliver cost-effective, increased power density [101].
Practical examples of soft-switching topologies today are shown below in figure 22. Note that the mechanical construction/assembly techniques used are industry-standard, and readily-available at low cost. The 65 W solution operates at ~400 kHz, while the 150 W circuit operates at 1 MHz.
The same GaN power ICs may be applied in high-power, multi-kW applications, with one example being a 3.2 kW, 1 MHz, AC-48 V converter prototype with 65 W/in 3 power density [102]. Here, the single devices are paralleled to achieve lower R DS(ON) and interleaving techniques are used for the Totem-Pole PFC and LLC sections.

Concluding remarks.
Major accomplishments, major opportunities. The last 20 years have seen GaN's progression from RF to power discrete and now to the first generation of AllGaN power ICs. This has enabled advanced, soft-switching topologies to enter the commercial marketplace. Next-generation monolithic integration (e.g. advanced I/O features, over-current and over-temperature protection) will enable even higher levels of efficiency, power density and reduced system cost. Today, we see the simultaneous 'perfect storm' of new devices, new topologies, new magnetics and integration lead to major steps in efficiency, density and system cost-reductions. The power revolution of the late 1970s [103] will finally repeat today, 40 years later.   Status. Amongst many semiconductors, silicon carbide (SiC), gallium nitride (GaN) and diamond can offer significant system level benefits and have the potential to meet the anticipated power densities by 2025 [104]. GaN offers similar performance benefits to SiC, but with a greater potential for cost-reduction as well as higher frequency. A price advantage over SiC is also possible because GaN power devices can be grown on substrates that are larger and less expensive than SiC. Since the first report of high density two-dimensional (2D) electron gas in 1991 [105] and high electron mobility transistors in 1993 [106], GaN has gained traction and now discrete GaN transistors are emerging as commercial products. Their performance is however limited to about 1/5 of their potential capability by slower external silicon gate driver circuits required to control them. Si circuits have a limited operating temperature range and inherently efficient GaN devices are forced to slow down, leading to failure and severe derating of efficiency. The dual (Si & GaN) technology approach impacts cost deleteriously. By monolithically integrating control circuits with power devices on a single GaN technology platform the efficiency can be greatly increased, and cost reduced. Moreover, because of the difficulty in obtaining p-channel devices, integrated circuits (ICs) thus far demonstrated are made of n-channel devices.

Potential of polarisation super junction technology in gallium nitride
Current and future challenges. In GaN-on-Si technology, the breakdown voltage is primarily determined by the GaN buffer and therefore thick buffer and transition layers are necessary to sustain high voltage, which make the wafers more susceptible to bowing and crack generation. The inherent tensile stress due to mismatch in lattice constants and coefficients of thermal expansion in such structures can also compromise the reliability of devices. Lack of avalanche capability or non-destructive breakdown behaviour necessitates over-rating the device breakdown voltage for a given application. Moreover, there is a significant level of defects in layers and understanding of these defects and their relationship with device reliability is necessary. The conventional GaN technology uses metal field plates. However, the distribution of the electric field is not uniform, which impacts breakdown voltage along with rendering such devices to be sensitive to current collapse during high voltage switching. The field distribution is also highly sensitive to changes in charges accumulated in the insulators sandwiched between the semiconductor surface and the field plates. Realizing such high voltage devices also requires sophisticated processing capability for formation of precise field modulating plates. An alternative solution for manufacturing low-cost high-voltage GaN power switching devices, which can overcome some of the above-mentioned challenges is the polarisation super junction (PSJ) technology, which is described in the next section. This technology is also a highly promising candidate for the fully GaN based power ICs.
Advances in science and technology to meet challenges. In 2006, a polarisation junction (PJ) concept was proposed based on the charge compensation of positive and negative polarisation charges at heterointerfaces of a GaN/ AlGaN/GaN structure [107]. This was followed by the successful demonstration of GaN double heterostructures, grown along the (0 0 0 1) crystal axis, where high density positive and negative polarisation charges coexist at the AlGaN(0 0 0 1 )/GaN(0 0 0 1) interface with accumulated 2D electron gas (2DEG) and 2D hole gas (2DHG) accumulated at the GaN(0 0 0 1 )/AlGaN(0 0 0 1) interface respectively, as shown in figure 23 (left) and figure 23 (middle) which has since enabled a polarisation super junction (PSJ) technology [108]. Like the superjunction in Si, PSJ enables linear scaling of breakdown voltage with increase in thickness or length of the drift region and with performances beyond that of 1-D 4-H silicon carbide limit, as shown in figure 23 (right). Over the past few years, high performance diodes, transistors as well bidirectional switches have been demonstrated [109,110]. Enhancement-mode PSJ-HEMTs have also been reported with most recent results of large (4 × 6 mm 2 ) and small devices made on sapphire substrates showing with breakdown volt ages beyond 3 kV [111]. Moreover, due to the effective lateral charge balance and field distribution, these devices fabricated on a sapphire substrate show no current collapse. One of the key attributes of the PSJ technology is that it is viable to make both NMOS as well as PMOS circuits, and CMOS inverter operation of a monolithic Pand N-channel MOSFETs has been demonstrated on this platform [112]. This technology also paves way for bidirectional switches with integrated diodes. This device is well suited for a variety of applications and for solid state circuit breaker because, PSJ offers the possibility of realising much lower saturation currents than conventional HFETs [108], while maintaining ultra-low on-state resistance. Thus, PSJ technology can pave the way for high power density monolithic integration of various devices for a variety of applications, as shown in figure 24.
Most recently, the PSJ concept has been extended to vertical GaN technologies and is termed as vertical PSJ (VIPSJ) with predicted benefits of 2 orders of magnitude reduction in specific on-state resistance in comparison to SiC at 1 kV rating [113].
Concluding remarks. There are several scientific, technological and manufacturing challenges that need to be addressed before GaN power semiconductor devices can be considered mainstream. It is also becoming apparent that a transition from the general scheme of manufacturing power conversion circuits using discrete devices to that of a fully integrated power system-on-chip is anticipated to be a prerequisite to fully harness the high-frequency power switching benefits of GaN. To conclude, GaN PSJ technology will be instrumental in shaping a viable and a new era of an integrated power electronics for ultra-high-power density converters.  Proposed PSJ platform for monolithic power integrated circuits. Please note that the substrate is not specified. However, thin sapphire is the most cost-effective option because of the use of uniform thickness of 1 µm u-GaN buffer layers to serve for both low as well as high voltage devices and provide full electrical isolation (critical requirement for monolithic integration).

National Institute of AIST, Japan
Status. Si-based lateral power devices have been widely utilized in high-frequency and low-power converters for ratings of up to several hundred watts [114]. On the other hand, GaNbased heterojunction field-effect transistors (HFETs) utilizing polarization-induced 2D electron gas (2DEG) are emerging components for such high-frequency converters. GaN-based discrete devices up to 650 V rating are commercially available now. The development of GaN growth technology on conductive Si substrates has largely contributed to the improvement in the device performance and decrease in cost [43]. As a next step, towards achieving high intrinsic switching capability of GaN devices, monolithic integration of GaN-based converter circuits will be necessary. Area-specific on-resistances of GaN-HFETs are already two orders of magnitude smaller than those of Si-based lateral power devices. Owing to this significant footprint reduction, high output powers of up to several kilowatts can be expected in GaN-based monolithic converters. In this article, two technological challenges are addressed: the 'crosstalk effect' and 'heat dissipation' in nextgeneration ultra-high-frequency monolithic power integrated circuits (ICs). These issues are quantitatively discussed using simple analytical models. Current and future challenges. As an example of GaN power ICs, if an integrated half-bridge circuit on a conductive Si substrate as shown in figure 25 is assumed with the following parameters: voltage rating of the GaN devices are 600 V, input voltage V IN is 400 V, 2DEG density N s has a conventional value of 10 13 cm −2 , and dielectric constant ε of the GaN-based epilayer is 9.0 ε 0 .
Firstly, the 'crosstalk effect' is discussed. In discrete GaN devices, the substrate potential is shorted with the source electrode. The conductive Si substrate acts as a back-side field plate contributing to the suppression of current collapse. However, in an IC, it induces a significant increase in the onresistance of the high-side transistor [115]. This is because the 2DEG of the high-side transistor interacts with the substrate potential through the GaN epilayer capacitance C epi . During the on-state of the high-side transistor, the input voltage V IN is directly applied to C epi , inducing a 2DEG density reduction ΔN s : where q is the electron charge, A is the GaN device area, and t epi is the GaN-based epilayer thickness grown over silicon substrate. If we consider a 2DEG density reduction of 10% (i.e. 10% on-resistance increase), the calculated t epi is 20 µm.
In comparison with a GaN-based epilayer in conventional discrete devices (3-5 µm), power IC applications require an epilayer which is thicker by five times. Next, the issue of 'heat dissipation' challenges are discussed under hard switching condition. When the gate drive speed is sufficiently high, power loss of the hard-switching circuit (figure 25) reaches the minimum value. Under the minimum loss condition, the heat density HD of the GaN chip can be expressed as where Q oss is the output charge of each GaN transistor and f is the the output pulse-width modulation frequency. Equation (2) implies that a charge Q oss is supplied from the voltage source V IN during every switching period, and the energy is consumed as joule heat in the GaN chip. Figure 26 shows the heat density calculated using equation (2). Although high-frequency operation is expected in hard-switched GaN monolithic converters, the estimated heat density is unacceptably high. For example, it is 6.4 kW cm −2 at 10 MHz.
Advances in science and technology to meet challenges. The substrate material for the growth of GaN-based layers is a key element of power ICs. Because conductive Si substrates induce the crosstalk effect, novel platform substrates are required for next-generation ICs, especially for high-voltage  and high-frequency applications. GaN-on-silicon-on-insulator (SOI) technologies are a promising solution which can enable CMOS compatibility in the GaN device fabrication process [116,117]. The contribution of the back-side field plate effect is also obtained through substrate contact from the front side [117]. However, a several-µm-thick SiO 2 buried layer will be required to sustain 600 V or more. The thermal conductivity of SiO 2 is two orders of magnitude smaller than that of Si. Therefore, heat dissipation from integrated GaN devices on an SOI substrate will be big challenge. Furthermore, GaN power device technologies on insulator sapphire substrates are equally promising candidates [92,118] because they yield high-quality GaN crystals. However, on such insulator substrates, current collapse must be eliminated without the support of the back-side field plate effect. Effective lateral electric field management strategies will be necessary, such as polarization superjunction technology [118].
In addition, other emerging candidates must be considered. Because the thermal conductivity of SiC is three times higher than that of Si, GaN technologies on highly resistive SiC substrates have been widely used in RF applications and are also emerging candidates in power converter applications. Finally, GaN-on-diamond technology might be the ultimate solution to the heat dissipation issue because diamond has the highest thermal conductivity [119][120][121].
Concluding remarks. In next-generation GaN-based power ICs, device isolation technologies are a key challenge, especially in high-voltage applications. GaN-on-SOI and GaNon-sapphire technologies are promising candidates from this perspective. In addition, thermal management is a key issue. Area-specific on-resistance has been a major benchmark parameter of GaN-HFETs. In addition, the minimization of area-specific 'thermal-resistance' will be a key strategy in GaN-based IC development. Therefore, GaN device technologies utilizing high-thermal-conductivity substrates such as SiC and diamond are also emerging as platform substrates for GaN power ICs. However, on any platform, potential advantages in performance and cost should be considered from the system level viewpoint.

HRL Laboratories, Malibu, CA, United States of America
Status. GaN power transistors have demonstrated unprecedented switching speed [122]. At high switching speed, parasitic inductance in the power loop as well as in the drive loop causes large voltage overshoot [123]. In current practice, the GaN switch is often intentionally slowed down to avoid catastrophic failure and additional power consumption induced by the voltage overshoot [124]. To take full advantage of the high-speed GaN switch, one need to eliminate the parasitic inductance by monolithically integrating power switches and their gate drivers. The gate driver typically uses a Totem-Pole topology with a pair of complementary N-type and P-type transistors. The complementary transistors eliminate static power consumption. GaN CMOS technology is needed to realize monolithic GaN power IC integrating high-voltage GaN transistors with low-voltage N-and P-type GaN transistors on the same chip.
The monolithic GaN power IC, as shown in figure 27, minimizes interconnect parasitic between power switches and gate drives. Reduction of interconnect parasitic enables efficient power switching at high frequencies. At high frequencies, the size of passive components can be drastically reduced. Reduction of interconnect parasitic also enables active control of switching trajectory with minimal time delay. Active control of switching trajectory mitigates device stress and improves the reliability. The monolithic GaN power IC enables modular architecture where a number of power switching unit cells, e.g. half bridge, can be stacked in parallel and in series to scale the current and voltage handling capability. The monolithic GaN power IC enables cost reduction by cutting the assembly and packaging cost, as well as by using the modular architecture consisting of standardized switching unit cells.
Current and future challenges. N-type GaN high-and lowvoltage transistors are readily available. Difficulty in making P-type GaN transistor and integrating it with the N-type transistor has been the major obstacle for realizing the GaN CMOS technology. There have been a few early studies on P-type GaN transistors [125][126][127][128], an attempt to integrate Pand N-type Schottky gate GaN transistors [129], and lately a demonstration of a working GaN CMOS IC inverter [92]. The GaN CMOS demonstration was achieved through selective area regrowth of P-type GaN transistor structure on a wafer with N-type GaN transistor epitaxy structure. Significant improvement of the GaN CMOS technology is needed to meet the performance requirement of the monolithic power IC. Specifically, there are two major challenges to be addressed. One challenge is the low output current, or high on-resistance, of the P-type transistor. The other challenge is the off-state leakage current of the P-type transistor when integrated with the N-type transistor. The low output current results from poor hole mobility, low mobile hole concentration, and poor ohmic contacts. The off-state leakage is attributed to impurity contamination at the regrowth interface.
Advances in science and technology to meet challenges. Figure 28 shows device structure, IV curves, and on-resistance component breakdown of a P-type GaN transistor reported in [92]. Inefficient P-type doping is the primary challenge responsible for the low current and the high on-resistance. Mg, with an activation energy as high as 0.2 eV in GaN, is used as the acceptor. High dopant activation energy leads to low concentration of mobile holes even at high doping level, therefore high contact resistance and high access resistance. Advance in P-type doping technique, e.g. polarization-assisted doping [130], has the potential of overcoming the doping challenge. Low hole mobility is another important factor responsible for the high on-resistance. Low hole mobility is caused by severe impurity scattering, interface scattering under the gate insulator, and large hole effective mass. In addition to enhancing doping efficiency, improvement of insulator-semiconductor interface is important for achieving better hole mobility and lower channel resistance. Strain engineering may increase the population of light holes, thereby improving the hole mobility. In addition to improving hole density and mobility, reducing or eliminating the spacings between gate and source/drain electrodes can effectively improve the on-resistance. Improvement of epitaxy regrowth process is needed to eliminate the off-state leakage current shown in figure 28. P-type transistors fabricated on P-type only wafers did not show this off-state leakage. The off-state leakage is attributed to Si contamination commonly observed at the regrowth interface. The source of the Si contamination can be volatile organic silicon compound in the air ambient. A regrowth process avoiding such contamination is needed to integrate highperformance P-and N-type transistors.
Comprehensive study of gate dielectric in P-type transistors is also needed to ensure stable threshold voltage, and facilitate scaling to smaller gate lengths.
Concluding remarks. Monolithic power IC based on the GaN CMOS technology is essential for realizing and maximizing the performance/cost potential of GaN power electronics. Early work on GaN N/P-type transistors and GaN CMOS technology has proved that the GaN CMOS is a fact, not a fiction. Improvement of P-type doping and selective area regrowth is important for realizing high-performance GaN CMOS technology for monolithic power IC applications.  [92]. 5X reduction of on-resistance is achievable at low risk with optimized device design/process.

University of Sheffield, United Kingdom
Status. P-type devices are required for integration of CMOS gate drivers and power devices to enable high frequency, high efficiency convertor systems on a chip in GaN. A D-mode p-channel HFET in GaN, utilising a low density (1 × 10 11 cm 2 ) polarization induced two dimensional hole gas (2DHG) as carrier was first demonstrated by Zimmermann et al in 2004 [126]. It is more difficult to realise a normallyoff (E-mode) operation, with negative threshold voltage V th , since the 2DHG under the gate has to be depleted at zero gate bias. A recessed gate [131], and/or reduction of polarization charge via adjustment of the mole fractions [132] have been amongst techniques explored for E-mode operation, following logically from similar progression in n-type devices in GaN. However, these techniques are not easily transferrable, primarily because unlike a 2DEG in GaN, achieving a high density 2DHG is a challenge, and reported mobility of holes in a 2DHG, ranges no more than 6-43 cm 2 V s −1 at room temperature [126,132].
Current and future challenges. The main challenge for a p-type MOSHFET in GaN is achieving a high threshold voltage |V th | to prevent false turn-on in PMIC applications, while maintaining a high |I ON | and |I ON /I OFF | ratio. Achieving a |V th | of |−2.0| V is not feasible by etching alone, as it requires the thicknesses of the oxide and GaN channel layer to be reduced to undesirably small values (∼ 5 nm) [133]. On the other hand, achieving an E-mode operation by reducing the polarization charge via a reduction in the Al mole fraction leads to reduction in the density of both 2DHG and 2DEG, not only reducing the |I ON | in p-type devices but also deteriorating the performance of n-type devices on the same platform. Figures 29(a) and (b) depict the on-current |I ON | and on-off current ratio |I ON /I OFF | with threshold voltage |V th | of experimental p-channel HFETs reported in [92,127,131,132,134], highlighting the degradation of |I ON | as the device turns from D-mode to E-mode while |I ON /I OFF | ratios improve with increasingly negative |V th |. Except for the work of Chu [92] and Li et al [127], which do not include an underlying 2DEG beneath the 2DHG, the activities can be summarised into two main barrier-layer platforms, ternary AlGaN and quaternary InAlGaN, both of which possess an inherent polarisation superjunction [135] that is eminently useful for management of the peak electric field distribution and reliability of GaN power devices. The best performing E-mode p-type device by gate recess so far, reported by Hahn et al [132], resulted in an on-current |I ON | of ∼ 9 mA mm −1 at a V th of −1.3 V and an on/off current ratio of ∼ 10 7 . In quaternary barriers, increasing the Al mole fraction leads to an increase in negative polarization charge, higher bandgap, and a smaller lattice constant, while increasing the In mole fraction has the opposite effect. Hence, by adjusting both Al and In mole fractions simultaneously, it is possible to tune the polarization and the bandgap of the barrier layer, independently, to some extent.
Advances in science and technology to meet challenges. A higher |I ON | requires a high density of 2DHG, nevertheless, for an overall lower parasitic resistance, as well as high on/off current ratio, requires a localised depletion of the 2DHG under the gate, so as to not affect the access regions. This can be achieved via an AlGaN cap between the oxide and GaN channel layers [136], where the barrier separating the 2DHG from the 2DEG can be either AlGaN or InAlGaN. As shown previously, for the device in figure 30(a), the additional polarisation charge introduced by the AlGaN cap not only depletes the 2DHG under the gate, but also minimises the trade-off between |I ON | and |V th | [133]. However, this approach demands a selective epitaxial regrowth of the AlGaN cap layer. Figure 30(b) shows an alternate heterostructure, where in addition to the recessed gate, the 2DEG is biased via an additional base contact [134], thus acting as a secondary gate for the 2DHG. By applying a positive bias to the base contact V B , the density of 2DHG can be reduced locally, without affecting other devices on the platform. In both the device structures (figures 30(a) and (b)), a 2DEG lying parallel beneath the 2DHG separated  by an AlGaN/InAlGaN barrier contributes an additional parasitic capacitance which can be offset by increasing the barrier thickness.
Advancements in the growth of gate oxide are necessary to control and lower the impact of trap states at the oxide/AlGaN cap and oxide/GaN interfaces while at the same time lower the gate leakage current, for a reliable and replicable operation of these devices. The MOCVD growth of Mg doped p-GaN layer currently suffers from, large activation energy (120-200 meV) of Mg dopants and memory effect [137], which leads to poor hole density in p-GaN and a broader doping profile. Moreover, during the epitaxial growth at high temperature, Mg ions can diffuse into the GaN layer underneath, thus contributing to the leakage current and affecting the minimum channel thickness that can be achieved in manufacture. Therefore, novel doping techniques are required to obtain p-GaN layers with high hole density and sharper doping profile.
Other possibilities to boost the performance of p-type devices in GaN include, improving the hole mobility by tailoring the valence band structure in GaN, for example by the application of stress to lower the effective mass of holes or introduction of positive ions directly in the gate oxide to deplete the hole gas underneath.
Concluding remarks. P-type devices in GaN are necessary in the long run to harness the full potential that GaN technology has to offer in achieving high efficiency power conversion. Despite the poor mobility of holes and challenges associated with Mg dopant, techniques to circumvent or limit their impact exist, although still in their infancy. More work is required for demonstrating their reliable operation and manufacturability at low cost.

Oliver Häberlen
Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach, Austria Status. Since the first confirmation of a 2DEG at the AlGaN/ GaN interface in 1992 and the first availability of GaN-on-SiC radio frequency power transistors in 1998, nitride semiconductor hetero structure electron devices now constitute a hundred million dollar market for RF power. As regards power conversion applications, GaN-on-Si high voltage power transistors have been in development stage for the past decade with initial focus on depletion mode devices, due to the inherent nature of the 2DEG. However, most power electronic applications demand for enhancement mode devices. The first high voltage solution released to market in 2015 by Trans-Phorm [138] is based on a cascode configuration of a low voltage Si-MOSFET in series connection with a high voltage GaN MIS-HEMT to solve that issue. Following the progress of enhancement mode devices based on a p doped GaN gate module for low voltage GaN power transistors from EPC [139], we now see the first fully industrial qualified 600 V true enhancement mode (E-mode) GaN power transistors on the market from Panasonic and Infineon [140,141]. These E-mode GaN power transistors are based on a fully recessed gate module with subsequent regrowth of a second AlGaN barrier with pGaN (see figure 31) on top for an excellent control of the threshold voltage independent of the drift layer carrier density [142]. pGaN is also used at the drain region as drain extension which improves the dynamic on state resistance to well below 10% even at high temperatures of 150 °C and at a full rated drain voltage of 600 V down with delay times as short as few hundreds of ns from blocking mode to settled on state resistance measurement. At the same time, this drain sided pGaN region (see figure 31) also improves the robustness of the device to the required levels for hard switching applications [140]. The devices are offered in surface mount device packages allowing for designs with low loop inductances including top side cooled variants for enabling 3 kW converters without need for paralleled devices (see figure 31).
Recently, it has been demonstrated that the gate module even allows for a >10 µs short circuit robustness at full bus voltage of 400 V when driven properly [143]. The technology has been implemented in a volume silicon power fab with a very high degree of equipment sharing with standard silicon processes to achieve economy of scale.
When comparing Infineon's CoolGaN ™ technology to the state-of-the-art silicon super junction devices (Si SJ) as well as other wide band gap technologies on the market (see table 1), we see that all WBG technologies offer roughly the same order of magnitude improvement in output charge Q OSS and reverse recovery charge Q RR per R DSON . However, only E-mode GaN offers at the same time one order of magnitude of gate charge Q G improvement which makes it the perfect device for high frequency resonant switching. Resonant converters with 3 kW power level operating at 350 kHz without sacrificing peak efficiency of 98.4% demonstrate high density of 170 W/in 3 [144]. For hard switching applications the relevant figure-ofmerit is the energy stored in the output capacitance (E oss ) and here recent developments in Si SJ devices have raised the bar significantly so that as of today only E-mode GaN can outperform Si. In combination with the lack of reverse recovery charge that enables the use of GaN devices in half bridge configurations new and simpler topologies like full bridge totem pole are possible.
Current and future challenges. One of the biggest challenges to release power GaN devices to the market has for sure been their reliability. The hetero epitaxial growth of the GaN buffer on silicon wafers unavoidably leads to lattice misfit dislocations and other growth defects. At the same time, present lateral GaN devices differ from the established silicon power devices in many aspects as they are based on hetero junctions, differences in spontaneous polarizations and bulk/surface donors to generate the 2DEG instead of p and n dopings. The qualification of those devices therefore cannot solely rely on established silicon procedures (e.g. according to JEDEC Solid State Technology Association, former Joint Electron Device Engineering Council) but must take into consideration the new possible failure modes and physics together with the corre sponding lifetime models and application profiles to determine appropriate qualification tests and durations. It is also essential to derive appropriate screening tests based on intrinsic and extrinsic lifetime models to achieve the needed low field failure rates of 1 fit or less. Passing all those qualification procedures still does not guarantee stable long term behaviour in the application. Long term testing of the devices under real application conditions with no fails is a first necessary step, but only application testing with accelerated conditions (e.g. higher temperatures, bus voltages, peak currents) and testing to failure allows extraction of life time models and hence failure rates in real life [145]. As a joint effort by the major semiconductor companies involved in GaN, a working group for the standardization of GaN qualification under the framework of JEDEC has been recently established to address many of the before mentioned aspects [146].
Advances in science and technology to meet challenges. For further advancing the reliability of GaN devices it is important to further deepen the understanding of defects and their relation to device behaviour and device reliability. This comprises e.g. the understanding of point defects including their electronic structure mainly in the various parts of the AlN/AlGaN/ GaN buffer, channel and barrier layers and how those defects are influenced by the growth conditions of the mat erial and the selection of possible advanced substrates. In order to possibly achieve future enhancement mode devices based on MIS gate structures with low leakage currents and a wide range of threshold voltages and gate drive voltages a big step in understanding on how to reduce the interface defect density of gate dielectrics on top of GaN and how to improve channel mobility is needed.
An important mid to long term challenge for GaN technology to enable broader market penetration is approaching cost parity per same R DSON compared to silicon devices like CoolMOS ™ . This will be driven on the one hand side by reducing the cost per die area through increasing economy of scale and increased yield with rising volume and the introduction of 200 mm wafer diameter for GaN-on-Si during the next few years as well as the step to 300 mm within the next decade. On the other hand, we will see further die shrinks through better exploration of the material limits e.g. by increased material quality allowing for shorter drift regions through higher electric fields as well as advanced drift region engineering (improved field plates, graded 2DEG density, etc.) allowing for higher carrier densities without compromising reliability.
Concluding remarks. After GaN-on-SiC RF power devices reached a multi hundred million dollar market volume, and after a decade of intense research and development of GaNon-Si power technology, fully industrial qualified 600 V true enhancement mode GaN power devices are finally entering the market. Qualification procedures and screening methods have been established according to the needs of the new material system and taking into consideration typical industrial application profiles targeting field failure rates below 1 fit. The new devices offer customers the degree of freedom to either boost the power conversion efficiency to unprecedented levels of 99% and beyond or to significantly increase the power density of their converters without compromising the efficiency.

Kean Boon Lee, Sheng Jiang and Peter Houston
Department of Electronic and Electrical Engineering, University of Sheffield, Mappin Street, Sheffield, S1 3JD, United Kingdom Status. AlGaN/GaN high electron mobility transistors (HEMTs) are poised to replace Si MOSFETs for high frequency power switching applications up to 600 V. Enhancement mode (E-mode) operation with a positive threshold volt age (V TH ) ⩾ 3 V is desirable for circuitry protection and safety purposes but GaN HEMTs are naturally depletion mode (D-mode) devices. Cascode devices with low voltage E-mode Si MOSFETs and high voltage D-mode GaN HEMTs offer an excellent solution to the E-mode operation issue using existing gate drivers. In addition, the cascode structure can lead to improved switching speed and reduced switching losses compared to an equivalent discrete transistor [147]. Here, we discuss the challenges faced by cascode devices as well as the potential of integrated cascode structures to achieve high switching frequency.
Current and future challenges. Despite the promising performance of commercial 600 V hybrid GaN plus Si cascode transistors [148], several issues hinder their switching performance. Firstly, additional package connections in the hybrid cascode lead to increased parasitic inductances which can cause excessive ringing and limit the operating frequency [149]. This presents major challenges to packaging design. In addition, the intrinsic capacitance mismatch between the Si and GaN transistors and the body diode in the Si MOSFET can result in additional switching losses when the Si device is driven into avalanche mode during turn-off [150].
Monolithically integration of E-mode and D-mode GaN devices in the cascode configuration, on the other hand, will mitigate the parasitic inductances and the 'slower' Si device issues in the hybrid GaN plus Si cascode devices. However, V TH of the reported E-mode GaN devices using various techniques such as fluorine (F) treatment on the barrier under the gate [151], GaN MOSFETs [152] and p-AlGaN gate [153] remains low, typically less than 2 V. This presents an issue for gate driving as un-intended turn-on may occur with a voltage ringing effect as a result of CdV/dt coupling from the drain to the gate.
Advances in science and technology to meet challenges. The switching losses in a field effect transistor are partly determined by the current through the resistive loss-generating channel during the charging/discharging processes [154] and hence depend on the speed of charging and discharging the Miller capacitance (Miller effect) at high voltages. The latter depends on the load current-to-gate drive current ratio. On the other hand, the discharging of the charge stored in the output capacitance of the cascode device is not limited by the gate drive current during turn-on as shown in figure 32(a). During turn-off, the cascode connection utilises the load current to charge the output capacitance and a faster turn-off time can be achieved for the same gate drive capability. The GaNbased integrated cascode transistor is an excellent candidate to exploit these switching advantages without the additional parasitic inductance. In our recent work using F treatment technology to achieve E-mode in the integrated cascode GaN transistor (V TH = +2 V) ( figure 33), we demonstrated a reduction in turn-on and turn-off energy losses of 21% and 35%, respectively in comparison to a discrete GaN E-mode transistor under 200 V hard switching conditions [155]. The immediate challenge is to achieve a reliable E-mode technology with V TH greater than +2 V.
Matching of intrinsic capacitances between E-mode and D-mode devices in the cascode connection is critical to control the off-state operating voltage of the E-mode device. For hybrid cascodes, adding an external capacitor in parallel with drain-source of E-mode Si MOSFETs has been proposed to provide this matching and prevent the Si device running into avalanche [150], but at the expense of additional package inductances. For GaN integrated cascode transistors, different field plate structures in E-mode and D-mode devices can be employed to achieve capacitance matching. In addition, with the lack of a body diode in the low voltage GaN E-mode device, the integrated cascode devices have the option to trade the off-state operating voltage of the E-mode part for a faster switching speed, without the avalanche loss.

Qingyun Huang, Ruiyang Yu and Alex Huang
Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, United States of America Status. The commercialization of 600 V GaN power devices, including the cascode-based FETs and the enhancement mode FETs, has enabled large scale R&D effort in academia and industry [156] to evaluate the impact on converter design and performance. Compared with the best 600 V Si superjunction (SJ) MOSFET, the input figure of merit (R on · C iss ) of 600 V GaN FET has been improved by about 20 times, the output figure of merit (R on · C oss ) has been improved by about five times while the reverse recovery figure of merit (R on · Q rr ) has been improved by more than 40 times [156]. These revolutionary improvements make GaN devices ideal for high efficiency and high density power supply design, especially for applications where the DC link voltage is around 400 V. Many converter topologies exist that can take advantages of the improved device performance by directly replacing Si SJ MOSFETs with GaN FETs, operating at the same switching frequency or at an increased frequency. Example topologies include the active-clamped flyback converter for universal AC/DC adapter which can use GaN devices in the primary side [157]; the soft-switched isolated DC/DC converters, such as LLC resonant converter, phase-shift-fullbridge (PSFB), dual-active-bridge (DAB), etc, which use the GaN devices in the primary side or both sides [158]. Many designs explore the ability to push the switching frequency to much higher value than the Si-based ones, achieving ultrahigh efficiency and density. Some topologies are rarely used in the past, limited by the severe reverse recovery issue such as large Q rr and high recovery di/dt in the Si SJ MOSFET. However, by using the GaN devices where the reverse recovery Q rr is pretty much zero due to the absence of any minority carrier injection, some of these topologies become feasible and have demonstrated extraordinary performance. Examples include the 99% efficient totem-pole PFC, full-bridge (FB) photovoltaic (PV) inverter and the 98.8% efficient hardswitching isolated full-bridge converter [102,[159][160][161]. In addition to the circuits, improved modulations also make the same topologies perform even better. The continuous conduction mode (CCM) totem-pole power factor corrector (PFC) and FB PV inverter work with hard switching and constant frequency, typically only in the range of 50-100 kHz. However, the triangular cur rent mode (TCM) totem-pole PFC and FB PV inverter can work with soft switching and variable frequency in the range of 100 kHz-3 MHz [102,159,161]. With these GaN-based topologies, the efficiency and the power density are significantly improved compared with the Si-based solutions.
Current and future challenges. The main challenges for the GaN based converter topologies are: 1. The optimization of the switching frequency: the switching frequency determines the frequency related loss and the size of the passive components. The optimization of the switching frequency is an important research topic. 2. Selection between hard switching and soft switching: constant frequency hard switching modulation has low control complexity and high reliability, while the size of the passive components is large. Variable frequency soft switching techniques can reduce the size of the passive components due to the high frequency. However, the control complexity is significantly increased due to the variable frequency operation. The selection between hard switching and soft switching is a challenge. 3. The reduction of the differential mode (DM) filter size for soft-switched topologies: soft-switched topologies, such as the TCM totem-pole PFC and the TCM inverter, have large input current ripples. It is still challenging to dramatically reduce the DM filter size even the frequency is high. 4. New converter topologies in GaN: to take full advantage of the GaN device, developing new topologies and new power delivery architecture is a needed new challenge Advances in science and technology to meet challenges. The progresses in addressing and investigating the previously mentioned challenges are: 1. The optimization of the switching frequency: the optimization of the switching frequency depends on the requirements of the application. For applications focusing on the high efficiency, lower frequency is preferred. For the applications requiring high density, such as the Google Little Box challenge, higher frequency is preferred. 2. Selection between hard switching and soft switching: due to the elimination of the turn on loss, the zerovoltage-switching (ZVS) converters can realize high switching frequency. Thus, the size of all the passive components, especially the EMI filters, can be reduced. In addition, the slower dv/dt of the ZVS converters also reduce the EMI noises. The soft-switched converters have demonstrated ultra-high density, over 145 W/ inch 3 , on the totem-pole PFC and FB PV inverter [102,159,161]. 3. The reduction of the DM filter size for soft-switched topologies: multiphase interleaved soft-switched topologies can solve this challenge [162]. The interleaving technologies significantly reduce the current ripples. The DM filter size is optimized, too. 4. New converter topologies in GaN: the upcoming GaN-based AC switch could enable a number of new high-performance topologies. The resonant converter with GaN AC switch not only realizes high efficiency, but also achieves the wide input and wide output voltage conversion [163]. A new single stage solution, the isolated AC/DC DAB converter with GaN AC switches on the primary side, can be used for on-board charger and battery system with significantly improving the system efficiency [164].
Concluding remarks. The GaN-based converters have demonstrated extraordinary performance. As shown in table 2, the power density and the efficiency have been improved significantly based on these benchmark GaN converters. With the innovation and the optimization of the converter topologies in GaN, the density and efficiency will be further improved.
Even though the cost of the devices is increased, the high density and efficiency will reduce the system cost in the future.

Thomas Heckel, Stefan Zeltner, Bernd Eckardt and Martin März
Fraunhofer Institute for Integrated Systems and Device Technology, IISB, Germany Status. GaN semiconductors have gained popularity in GHz applications, while power electronic applications are still in the early stages of development. The focus of this section is the application of GaN devices for power electronics with device breakdown voltages from 400 V up to 900 V. Applications of GaN transistors include uni-and bidirectional DC/DC and AC/DC converters, inverters for high-speed motor drives as well as inductive heating and wireless power transmission (figure 34). High system efficiencies and power densities are the main requirements for these applications. This is enabled by low conduction and low switching losses from a semiconductor point of view. GaN transistors allow both aspects. Low conduction losses are achieved by GaN transistors with low area-related on-resistance compared to silicon (Si) and silicon carbide (SiC) counterparts. Low switching losses are achieved by fast switching between the on-and off state. GaN transistors show a purely capacitive behaviour due to their unipolar device characteristic, while Si-and SiC-MOSFETs lack from reverse recovery charge due to intrinsic bipolar body diodes [165]. Regarding the switching speed of the drain-sourcevoltage, 5-20 V ns −1 is considered as 'fast' for Si devices. Slew rates are typically limited to the range of 1-16 V ns −1 in motor drive applications [166]. In contrast, optimized SiC and GaN circuits allow up to 200 V ns −1 and 500 V ns −1 , respectively [167,168]. The possibility of ultra-fast switching exceeds the boundary conditions of most applications. However, operating two 600 V transistors in half-bridge configuration for e.g. hard-switching bidirectional DC/DC converters, Si-MOSFETs are not suitable due to their bipolar body diode. SiC-MOSFETs with orders of magnitude lower reverse recovery charge are suitable, but higher system efficiency can be achieved with unipolar GaN-transistors.
Current and future challenges. The main challenges for GaN transistors in power electronic applications are: 1. Normally-off characteristic: system developers require normally-off devices because of safety reasons, while the realization of normally-off device characteristics is still a main research topic (section 8). 2. Dynamic on-resistance: some GaN transistors show dynamic on-resistance. After turn-on, their on-resistance r ds,on is higher than the static value R ds,on,typ and decays over time until it reaches the static value R ds,on,typ . The main reason is a physical phenomenon called 'trapping' due to high electric-field strengths in the off-state, when the blocking voltage is applied (drain-source-voltage is e.g. 400 V) [169,170]. Figure 35 shows a comparison of three devices from different manufacturers. GaN #1 shows the highest dynamic on-resistance with a ratio of r ds,on (t 1 )/R ds,on,typ = 4.3 while it decreases to 2.5 after 300 µs. For example, the turn on time of a DC/DC converter operating at a moderate switching frequency of 100 kHz and a duty cycle of 50% is only 5 µs. This results in an effective on-resistance of 4.2 · R ds,on,typ for the system design and therefore in higher losses and lower efficiency. The influence of this issue becomes even worse when the switching frequency is increased. 3. Reverse conduction capability: in half-bridge configuration, reverse conduction capability is required for negative drain currents. Though there is no intrinsic body-diode in GaN transistors, current can flow from source to drain. However, the source-drain-voltage drop v sd increases with decreasing gate-source-voltage v gs . This is valid for all commercially GaN transistors known to the authors. For example, for some GaN transistors, the forward voltage drop v sd is 8 V or higher, when the gate is kept in the off state with v gs = −5 V. 4. Parasitics, packaging, controllability and EMI: in general, the influence of parasitic inductances and capacitances is the same as with Si and SiC circuits. This situation worsens for GaN transistors due to tighter gate voltage margins compared to Si and SiC devices which can lead to device destruction and phase leg short circuits. In general, fast switching semiconductors enable higher power densities, but require additional filters for electromagnetic interference (EMI), also. 5. Reliability issues and countermeasures are discussed in section 8.
Advances in science and technology to meet challenges. The progresses in addressing and investigating the challenges from the preceding subsection are: 1. Normally-off characteristic: this challenge must be solved at the level of the device technology. Alternatively, a cascode circuit with normally-off behaviour can be realized by using a normally-on high-voltage GaN transistor and a normally-off low-voltage Si transistor. However, recent studies have shown that the switching speed of cascodes is barely adjustable without additional components inside the cascode [171]. The necessity of an additional Si transistor for the cascode is another disadvantage of the cascode compared to normally-off GaN transistors. All commercial GaN transistors at the time of this study show normally-off behaviour by intrinsic normally-off characteristic or cascode configuration. 2. Dynamic on-resistance: as can be seen in figure 35, the GaN transistor #3 shows no dynamic on-resistance for the full time scale. The manufacturer applies an additional p-GaN-layer to provide the injection of holes from the drain and dynamic on-resistance can be prevented successfully [172]. However, other manufacturers still face the challenge of the dynamic on-resistance which is also indicated by significantly increased scientific activities regarding this topic.
3. Reverse conduction capability: the high forward voltage drop in reverse conduction mode of GaN transistors can be avoided by using synchronous rectification. This means to turn the GaN transistor on shortly after the current has commutated to the transistor in reverse direction. In contrast to a diode, the transistor has to be turned off before the complementary transistor of the half-bridge turns on. Otherwise, phase leg short circuits may occur which lead to immediate destruction of both switches. In this case, special protection circuits are necessary. Additionally, the adaption of the dead-time between the half-bridge switching actions helps to increase the efficiency even more. 4. Parasitics, packaging, controllability and EMI: integration of GaN transistors and gate drivers within one package will minimize the effects of parasitic circuit elements. The next step is to integrate GaN transistors and drivers within one chip which has already been demonstrated. To gain the most advantage for power electronic systems, the integration of GaN transistor, gate drivers, auxiliary circuits and DC link filters within one device will allow minimum parasitic circuit inductance and high switching speeds. The EMI can also be improved by the enclosure on low footprint as well as novel active filters.
Concluding remarks. GaN transistors have evolved dramatically in the last ten years and enable power electronic systems with highest efficiencies due to their unipolar device characteristic and low area-specific on-resistance ( figure 35).
The issues discussed in this section will diminish with further research similar to the advances with Si and SiC devices in the last 70 and 20 years, respectively.