Nanoscale phase-change materials and devices

The crystallization temperature (T_x), the lowest temperature at which the crystallization process occurs, is a particularly important parameter. T_x sets a definitive and easily measured bound on the retention versus temperature curve for PCMs, which can be measured by raising the temperature slowly while monitoring the crystallinity [2]. Typically, a high crystallization temperature leads to better thermal stability and longer data retention time [13]. Multiple methods, including doping [35] and various material systems [36, 37], have been attempted to improve the crystalline properties.

Interestingly, correlations have been reported between T_x and the dimension of the PCM. Generally, the T_x of PCMs sandwiched between oxides or nitrides can increase exponentially as the thin film thickness decreases [15, 24, 38], which can be explained by the inhibition of crystallization for very thin adjacent interfacial layers in semiconductor materials [39]. However, different interface materials can strongly influence the T_x in thin films. For instance, metal-induced crystallization can occur in PCMs sandwiched between metals. As a consequence, the crystallization temperature can reduce significantly, reaching 200 °C [30]. The influences on T_x of different interfacial layers are summarized in figure 4. Distinct interface capping materials introduce compressive stress to PCMs, thus strongly modulating T_x [38].

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Crystalline-crystalline phase transition temperatures have been reported to show film thickness-dependent properties in different material systems due to the interfacial free energy, which provides important insight into the multi-level applications of phase-change phenomena [36, 40, 41].

For nanowire devices, the phonon-softening model has predicted that as the diameter of the nanowire decreases, the enhanced phonon softening with an exposed broken band on the heterogeneous surface will suppress the T_x [28]. Measurement on Ge₂Sb₂Te₅ showed that smaller diameter nanowires have lower activation energies, indicating a shorter data retention time [42]. However, Yu et al [43] did not observe a dependence of T_x on the nanowire diameter. For phase-change nanodots, a different trend is observed than that in the thin film, which is explained by the heterogeneous nucleation [44]. In exploring the ultimate size, nanoparticles as small as 2 nm have shown amorphous-crystalline transitions, indicating good scaling properties [45]. Nanocrystalline technology has also been applied to increase the T_x by the internal stress effect [46, 47]. The scaling properties of the crystalline temperature of PCMs shows promising potential for next-generation phase-change technology, and effort is needed to develop unique material systems for specific application requirements [28].

High reset energy has been a bottleneck in the development of phase-change memory. A low PCM melting temperature (T_m) is generally beneficial to the device performance because it indicates a reduction in the power required to reset a phase-change memory device. Fortunately, T_m can vary with composition [48] and dimension. With reduced dimensions, thin films [7], nanowires [20] and nanoparticles [49], have been reported with significantly reduced T_m values (figure 5), mainly due to the increasing ratio of surface atoms to volume atoms.

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PCMs have also been mixed with different substances that have higher melting temperatures. For example, nitrogen doping Ge₂Sb₂Te₅ leads nitrogen to preferentially bond to Ge atoms [48]. Wang et al [44] found that this microscopic phenomenon helps maintain the grain size structure of Ge₂Sb₂Te₅ because the melting temperature of nitrides is higher than that of Ge₂Sb₂Te₅, increasing the overall endurance of the device. Pressure also plays an important role in T_m. Theoretical and experimental investigations have shown that amorphization and crystallization can be achieved under elevated pressure [50, 51], and the internal pressure can be high due to the volume change during phase transition [52]. The melting temperature can increase, leading to an increased 'reset' operation energy [53]. Overall, diminishing dimensions result in the reduction of T_m, which is favorable for decreasing the power of the reset step. Many other microscopic structure effects, such as interfaces and doping, can play important roles in determining the T_m, indicating that the design of PCM systems on the micro- and nanoscale should be deliberate and comprehensive.

PCM devices require temperature-driven phase transitions. Thus, thermal properties play a central role in this technology [34, 54]. Researchers have extended nanoscale heat transfer measurement methods, such as TDTR [55] and 3ω [56], to reveal exciting thermal transport phenomena of PCMs. Thermal transport in PCMs are intriguing because several material phases can coexist depending on the temperature history, geometry, neighboring materials and process details [34, 57, 58]. Moreover, anisotropic thermal conductivity can be an important parameter in the crystalline phase due to the remaining nanoscale amorphous phase near grain boundaries [55]. Phase-change nanowires have also been reported to show rather small thermal conductivities in the amorphous and crystalline phases [59].

In addition, electron and phonon heat transport properties play influential roles in the thermal properties of PCMs. For instance, although atomic vibrations are mainly responsible for heat conduction in the amorphous phase, electron heat transport can become prominent in the crystalline phases of Ge₂Sb₂Te₅ [21, 34, 60]. The difference in heat conductivity in different crystalline phases is well explained by separate electrical measurements and the Wiedemann–Franz law [49, 50].

Thermal boundary resistance (TBR) is another crucial parameter for the performance of nanoscale PCMs, because as dimensions diminish, most excess energy is required to reset the device flow through the interface between the electrode and the PCM [61] and through surrounding materials [50, 62]. The TBR between dielectrics [63, 64], metals [62, 65] and carbon-based materials [51] has been investigated, in which the distinct TBR between different phases of PCMs can be attributed to different acoustic and lattice structures, which can be explained by the phonon diffuse mismatch model [65]. Furthermore, study of the interplay between electrons and phonons through the interface suggests that, in all phases of Ge₂Sb₂Te₅, phonons govern the boundary thermal transport rather than electrons due to the small amount of electron tunneling transport [60]. To localize heat, the dielectric staking method has also been used to minimize the surrounding thermal conductivity [50, 60]. The study of TBR is beneficial for understanding and improving the thermal isolation of PCMs.

The threshold voltage is a parameter of PCMs that describes the applied voltage required to induce an electrical breakdown effect, which has been assumed to be related to the structural instability under a high electrical field [66, 67]. This sudden increase in electrical conductivity enables PCM devices to rapidly and efficiently attain sufficient energy to recrystallize at a moderate voltage. Hence, materials that show threshold switching are essential for phase-change device applications [66–68].

Studies of phase-change devices have shown that the threshold voltage scales linearly with the length from the bridge along the applied voltage direction [5, 69], suggesting a material-dependent threshold field rather than a threshold voltage that should be surpassed for the amorphous material to become conductive, as shown in figure 6(a). However, according to the impact ionization model [70], the scaling law fails when the length is less than 10 nm [43], which is very favorable for scalability because the read current in the circuit may be higher than the reset current through the nanoscale phase-change device. Stochastic network and electrical-temperature fields are applied to explain the scalability of the threshold phenomena at the microscopic level [71, 72]. It has been reported that a sub-threshold electrical field could be applied to accelerate structural modification to modulate the threshold voltage, which is beneficial for control and improvement of the phase-change device performance [29, 73–75]. In addition, contact resistance is an important parameter for threshold voltage in nanoscale devices. With reduced dimensionality, contact resistance plays a more important role in the overall electrical resistance, thus greatly influencing the threshold voltage [76, 77]. Additional detailed information on contact resistance is given in section 3.2.

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To explore microscopic aspects during threshold switching, advanced experimental methods, including in situ TEM, have been applied to observe the phase change process. Meister et al [19] observed void formation during threshold transitions, and theoretical calculations have been conducted to show that electrical field effects may play a significant role in threshold transitions [71]. Furthermore, the relation between the nanostructure-amorphous phase change inside devices and threshold switching has been investigated, indicating a linear relationship between the threshold voltage and the scale of the amorphous domain [46], as shown in figure 6(b). This result can explain the observed variability in PCM switching measurements.

Speed is likely critically important for PCM devices because it sets an upper bound on the potential data rate [2]. Three processes determine the operation speed: read, reset and set. Generally, the set process (amorphous to crystalline transition) takes the longest of these three processes due to the slower kinetics of forming crystalline (lower resistance) state than of forming an amorphous (higher resistance) state [6]. Thus, improving the crystallization speed is central to accelerating the overall speed.

The formation of the crystalline phase involves four steps: (1) threshold switching [66], (2) current-induced heating to an elevated temperature, (3) crystal nucleation [33] and (4) crystal growth. The nucleation step can be slow in so-called growth-dominated materials, whereas nucleation-dominated materials generally have a lower barrier to nucleation [6]. PCMs can be divided into these two groups, depending on the nucleation and growth kinetics; various researchers have been working to reveal and supplement understanding of the microscopic and macroscopic structures of this process [6, 78, 79].

Several factors contribute to the nucleation and growth kinetics in PCMs [6]. Among them, scaling has a strong influence on the crystallization speed. It was reported that the crystallization speed of amorphous Ge₂Sb₂Te₅ can decrease significantly when the device dimensions decrease due to interfacial effects [80, 81]. A superlattice has been introduced to build an interfacial phase-change memory with faster transit speed [82]. In addition, nanostructure engineering technology has been used to investigate and improve the crystallization speed of phase-change devices. In GeTe-based devices, a similar decrease in set speed is observed, and it was argued that the size of the amorphous region may play a critical role in the diminished growth-dominated recrystallization process time [83]. Loke et al [74] showed that applying a weak electrical field can greatly accelerate the recrystallization process to 500 ps due to nanostructure pre-ordering, as shown in figure 7. In addition, crystallization mechanisms different than those of bulk materials, such as hetero-crystallization mechanisms [44] or autocatalytic phase-change processes [84], may play important roles when devices are downscaled and may overcome the limitations between speed and reliable quality [44]. Finally, in contrast to the crystallization model, a purely electronic model for threshold switching has been applied to describe the phenomenon of ultrafast crystallization of Ag₄In₃Sb₆₇Te₂₆, indicating the potential for an ultrafast electronic switch [44]. The device history [26, 81], multi-phase (multi-level) technics [85, 86], temperature [79, 86, 87], and diverse material systems [88, 89] also strongly influence the crystallization speed.

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The ratio between the resistivity in the amorphous and crystalline phases directly determines the on/off ratio of PCM devices and has a strong influence on the amplitude of the set and reset current [2]. Though theoretical studies predict that the resistivity ratio will decrease when the dimensions decrease below a dozen atomic layers [90], nanoscale PCMs do not generally show this phenomenon [78]. However, to meet the demanding requirements of data storage, multi-phase technics may be required to increase the device density. Thus, it would be necessary to manipulate the resistivity ratio to enable multi-phase change switching. Details of the multiphase-switching device are discussed in section 3.3.

PCMs generally demonstrate highly desirable scaling behavior, which can be extended over several generations of technology nodes [11]. Further efforts of scientists and engineers will reveal the microscopic mechanisms of different phase-transition processes and new materials systems to achieve an overall balance and improve the performance of devices through nanostructure-engineering and scaling to precisely manipulate the phase-change properties.

Reset power is closely related to the reset process, in which the crystalline phase of a PCM transitions to the amorphous phase. It was assumed that this transition requires heating the material above its melting temperature, which determines the general power consumption of nanoscale phase-change devices. In general, scaling can greatly decrease the reset power [15, 17, 42]. However, sufficient reset power is still necessary to minimize the feature size of PCMs and increase the data density. As noted in the previous section, the access device current is a major challenge in this aspect, and thus one method for improving the data density of nanoscale phase-change devices is to improve the general capability of the access device [2]. Another solution is to locally increase the current density in the PCM and decrease the switching volume, as presented below.

The industry has proposed brilliant designs using sub-lithographic aperture and doping methods [100, 101]. Among them, contact-minimized cells and volume-minimized cells are two general categories, as shown in figure 8(a) [2]. A contact-minimized cell minimizes the switching energy by introducing a mushroom-like nanoscale amorphous dome of PCM, resulting in an overall high-resistance state. A volume-minimized cell minimizes the volume of the PCM, thus lowering the reset power by scaling. Theoretical calculations suggest that these geometric properties may strongly influence the cell power efficiency [102].

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Recent effort to lower the reset power has focused on improving the thermal efficiency using these two methods by balancing the cell resistance against the programming current [13]. Here, the contact electrode can greatly influence the power consumption [76]. Thus, carbon-based materials, such as carbon nanotubes or graphene ribbons, have been used as electrodes to decrease the overall energy consumption due to their sharp, atomically thin edges. Feng et al [103] presented a significant reduction in power using carbon nanotubes and found scalability between the electrode area and reset power, as shown in figure 8(c). Graphene was added at the interface [104] and electrode [77] between the PCM to aid in efficient Joule heating. Additionally, a superlattice PCM stack has been shown to lower the thermal conductivity [105] and change the switch mechanism to short-range movement instead of order-disorder transitions [106]. This ability has led to reduced power consumption and improved endurance [82]. The performance and power are improved by optimizing the stack design and decreasing the cell size [107, 108]. In addition, small cross-sectional and nanostructure-engineering devices, including phase-change nanotubes, have also been used to lower the switching power [28].

Endurance is one aspect of reliability. Though PCMs generally enable good endurance properties (over 10⁸ cycles), cycling-induced degradation generates early tail-bits that trigger read errors [13]. There are three typical tail-bit behaviors: cell open, stuck-high and stuck-low. These failure mechanisms are related to void formation and phase segregation [19, 109, 110]. Void formation is due to repeated changes in volume during switching by mechanical stress, and phase separation is driven by incomplete melting and recrystallization at the liquid-solid boundary [111, 112]. Thus, complete melting can aid in solving the problem of phase segregation [13]. Another method to avoid phase segregation includes manipulating the electrical pulse to reduce electromigration [113] or rejuvenating stressed PCM cells [114].

Another important aspect of reliability is material retention. To be applicable as a real candidate for nonvolatile memory, the PCM must demonstrate the long-term retention of stored data. The stability of the quenched reset phase dominates the retention issue because the crystalline set state is generally stable at room temperature. Here, thermally activated crystallization of the amorphous phase leads to a reduction in the resistance and causes retention failure. PCM retention measurements are typically conducted at higher temperature to speed up the resistance change. Activation energy has been used to measure the retention ability. For nanowire devices, it has been shown that the activation energy can be a function of nanowire thickness [8, 18], as shown in figure 9. Nanodots have also shown competitive retention properties [23]. A mushroom device has a retention activation energy of 2.6 eV and is adequate for more than 300 years retention time at 80 °C [115]. Different material systems [116–118] and doping [119, 120] also aid in manipulating the retention properties of nanoscale phase-change memory.

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PCMs can be made to undergo multiple transitions by introducing intermediate resistance states, which is another powerful method to reduce the cost per bit and increase the data density. Feng et al [121] used nanoscale amorphous layers with different resistivities to enable multi-level switching. By manipulating the electrical current and heat, an intermediate controllable state can appear, which can be explained by the formation of crystallites embedded in the bulk amorphous phase, as supported by nucleation theory [122–126].

However, when PCM devices are programmed, the resistance tends to increase over time due to resistance drift, as the amorphous phase tends to increase with time, significantly reducing the memory window of multiple state applications. The defect annihilation model, electron-conduction model and distributed Pool–Frenkel (PF) model have been proposed to explain the origin of resistance drift [33, 127–131]. Thus, physical (stress, temperature) methods or chemical (composition change) methods can be used to design drift-insensitive materials [131]. The thermal disturbance method [87, 124, 132] has also been used to study drift behavior relating to temperature. Nanowire devices [112], different material systems [36, 131] and nanostructure engineering [126, 133] have been used to lower the drift resistance phenomenon due to the reproduction of mechanical and chemical environments.