A scaling consideration on mechanical stress-induced hot-carrier effects

Mechanical stress related hot-carrier effects are investigated experimentally by imposing mechanical stress on the Si chip and analytically by using a three-dimensional simulator. The main viewpoints are: (i) applied stress direction dependence, (ii) device scaling, and (iii) degradation mechanisms. The generation of surface states by hot carrier is found to decrease under compressive stress, while V_th shift is enhanced. Consequently, mechanical stress might cause the variation of bond length of Si-O, Si-OH, Si-H, resulting in the enhancement of electron trapping efficiency. In terms of scalability, mechanical stress-induced hot-carrier effect becomes less with scaling of the channel length, L which coincides with the simulated mechanical stress sigma _x which decreases as L is reduced. This is probably due to a spreading effect of localized stress at the gate edge for scaled MOS devices, and will be a positive effect for lateral device scaling. Thus, the mechanical stress was found to influence differently on carrier trapping and N_ss generation. From now on, reliability problems such as TDDB, junction leaks and so forth will have to be re-examined as mechanical stress-related phenomena, which will lead to the realization of more reliable ULSIS.