High-speed all-optical logic gate using QD-SOA and its application

Abstract The scheme to realize high-speed (~250 Gb/s) all-optical Boolean logic gates using semiconductor optical amplifiers with quantum-dot (QD-SOA) is introduced and analyzed in this review. Numerical simulation method was presented by solving the rate equation and taking into account nonlinear dynamics including carrier heating and spectral hole-burning. Binary phase shift keyed signal and on–off keyed signal are used to generate high-speed all-optical logic gates. The applications based on all-optical logic gates such as, all-optical latches, pseudo random bit sequence generation, and all-optical encryption, are also discussed in this review. Results show that the scheme based on QD-SOA is a promising method for the realization of high-speed all-optical communication system in the future.


Introduction
In future high-speed optical communication systems, logic gates will play important roles, such as signal regeneration, addressing, header recognition, data encoding, and encryption (Li, 2015). In recent years, people have demonstrated optical logic using different schemes, including using dual semiconductor optical amplifier (SOA) Mach-Zehnder interferometer(MZI) (Kim et al., 2002;Wang et al., ABOUT THE AUTHORS Hongyu Hu was born in Fuzhou, China, in 1988

PUBLIC INTEREST STATEMENT
The current optical communication system does not work entirely in optical domain. A larger amount of the switches and data processors are made of electrical circuits which limits the ultimate speed of the existing optical transmission system. One promising solution is all-optical packet switching networks in which the header recognizing, payload processing, buffering, and forwarding of optical packets are all carried out in the optical domain, bringing together the wide fiber bandwidth and high routers forwarding capacity. The key building blocks of all-optical switching network are the all-optical circuits.
These proposed and studied all-optical circuits based on next generation quantum dot devices are the building blocks of the future all-optical network. These all-optical circuits design and simulation are of fundamental importance to the future generation of optical communication systems. These designed all-optical circuits are promising candidates to replace the discrete electrical counterparts currently used in communication systems.
The current optical communication system does not work entirely in optical domain. A larger amount of the switches and data processors are made of electrical circuits which limits the ultimate speed of the existing lightwave transmission system. One promising solution is all-optical packet switching networks in which the header recognizing, payload processing, buffering, and forwarding of optical packets are all carried out in the optical domain, bringing together the wide fiber bandwidth and high routers forwarding capacity (Dorren et al., 2003). In addition, the security of information is very important and all-optical encryption and decryption can be used to protect the information for future all-optical communication system. The key building blocks of optical switching and encryption are the all-optical Boolean logic gates, include XOR, AND, OR, NAND, NOT, and functional circuits built using these gates such as optical latches. Thus, it is very important to build all-optical logic gates capable for high speed and high output quality.
In order to further enhance operation speed of all-optical logic gates, besides using QD-SOA, the other method involves in the use of two-photon absorption (TPA) effect which is an ultrafast nonlinear process of SOA. With a high-intensity pump light injected into SOA, a fast changing TPA-induced phase shift becomes dominant in the total phase change experienced by a weak probe signal. As a result, the SOA will quickly respond to the injected short pulse in the active region which makes it suitable for high-speed operation. Several researches have demonstrated that all-optical logic gates based on TPA effect in common bulk SOA are capable of handling data at speed up to 250 Gb/s (Li, Ma, Hu, & Dutta, 2012b;Zhang, Li, Hu, & Dutta, 2015a, 2015b. However, the method using TPA effect needs a very high-intensity pump light usually with ultrashort pulse width Li et al., 2016; which increases the expense and complexity of practical all-optical system. In order to obtain better output quality of all-optical logic gates, binary phase shift keyed (BPSK) signal instead of on-off keyed (OOK) signal can be used to realize all-optical logic gates. Because BPSK signals carry information on the phase part while keeping the amplitude as a constant, the impairments from optical nonlinear effects and amplified spontaneous emission are greatly reduced.

All-optical logic gates based on QD-SOA
In this part, a model which simulates two QD energy level carrier dynamics and nonlinear effects affecting the gain spectrum of the device is presented. Using this model, a more accurate simulation of fast all-optical logic gates including AND, XOR, and NOT is provided. The effect of device induced ASE noise is also discussed.

QD-SOA structure and rate equations
The commonly used QD-SOA is InAs/GaAs, with InAs Stranski-Krastanov (SK) quantum dots embedded in GaAs layer (Akiyama, Wada, et al., 2000;Mukai et al., 1998). This type of device can provide ~15 dB gain at wavelength 1550 nm with noise figure as low as 7 dB (Berg & Mork, 2004). The active layer of the device consists of alternately stacked InAs island layers and GaAs intermediate layers.
This configuration can significantly increase areal dot density and the modal gain of the SOA  and the gain is nearly polarization independent (Ridha, Li, Rossetti, Patriarche, & Fiore, 2008). The density of state of the InAs/InGaAsP/InP QD-SOA (Berg & Mørk, 2003) is shown in Figure 1(a). From the graph, we see the carriers in the QD's are mostly populated on two groups of almost discrete energy levels (simplified here as two discrete states: QD ground state and QD excited state). The wetting layer has a continuous set of energies, supplying the two levels with carriers through interstate transitions and is able to refill itself using external electric current injection. The transition among the wetting layer, the QD excited state (ES), and the QD ground state (GS) is schematically illustrated in Figure 1(b). The GaAs layer is the "wetting layer" in Figure 1 which used to feed the ground state and excited state with carriers through interstate recombination. External current is applied to the device and mostly accumulated in the wetting layer.
Rate equations are used to describe gain and phase dynamics in QD device (Li, Hu, & Dutta, 2013b). The carrier density dynamics can be described as: where w, h, and f are the occupation probabilities of the wetting layer, the QD excited state, and ground state, respectively; Nwm, Nesm, and Ngsm are the maximum possible carrier densities of each state; Г d is the active layer confinement factor, I is the injected current, V is the effective volume of the active layer, a is differential gain, S(t) is photon density in the active region.
The gain dynamics in the QD-SOA include the contribution from the carrier density pulsation dynamics and nonlinear processes including carrier heating (CH) and spectral hole-burning (SHB) effect. Generally, the linear part of gain coefficient is based on the stimulated emission from the QD ground state to the valence band, where N t is the transparent carrier density of the QD ground state. The suppression of the gain coefficient brought by nonlinear CH and SHB effects can be expressed as: To a first approximation, Δg CH and Δg SHB are proportional to instantaneous light intensity S(t).
where ε CH and ε SHB are the gain suppression factors of carrier heating and spectral hole-burning effect, respectively. From Equations (5)-(7), we can get : The injected light and changed temperature result from carrier heating also changes the refractive index of the active region, and thus a phase change to any probe wave injected.
where G l(t) = e g(t)l is the gain factor of the device with l being the effective length of the active layer, α and α CH are the linewidth enhancement factor of the device.

Principles of QD-SOA-MZI-based all-optical logic gates
A QD-SOA-based Mach-Zehnder interferometer can be used to realize all-optical XOR, AND, NOT operations. As is shown in Figure 2, two identical QD-SOAs are in the two arms of the interferometer, three optical data streams carried by different wavelengths are injected into the two arms, where the control beam at λ 2 is symmetrically split into two branches at port C and guided into the two arms separately. The two beams then interact with data stream A, B and will experience a modulated gain and phase via XGM and XPM processes.
The light in two beams will combine and interfere at port D, after screening the other wavelengths using a band-pass filter (BPF), the output power at wavelength λ 2 can be expressed as: where P cb is the control beam power at port C, we can tune the initial phase difference between the two arms 0 by (for example,) adding a tunable phase shifter in one of the arms. For our logic gates used here, we typically tune 0 = π so that Equation (10) becomes: Note: BPF: band-pass filter (central wavelength λ 2 ).
Set control beam as clock wave at the same repetition rate as data A and B, the QD-SOA MZI will function as a XOR logic gate. When A = B = 0 or A = B = 1, the control beams in each arm will see the same cross gain or phase modulation as they go through the QD-SOA. And the output branches of the control beam will have a destructive interference pattern at output because of the initial π phase difference, and the output will be 0 at wavelength λ 2 . When A and B are not the same, the branches of control beam will undergo different gain, we can have a constructive interference at output port if we can change the power of modulating data streams A and B to make 1 (t) − 2 (t) = π, in this case the output will be 1 for wavelength λ 2 .

AND logic gate
In order to realize AND operation, a scheme similar to Dong, Sun, Wang, Dutta, and Jaques (2006) can be used: data A and a continuous wave (CW), both at wavelength λ 1 , are injected into each of the two QD-SOAs. Set the power of the CW so that it is the same as the average background optical power to balance the gain and phase impact from the "0" data components, data stream C at wavelength λ 2 is injected to both arms as control beam, this configuration will provide a process which gives "1" at output at λ 2 only when both data A and C is "1," functionally the same as all-optical AND gate.

NOT logic gate
Similar to XOR gate, if we change data stream B into a clock wave at wavelength λ 1 , we will have the setup of an all-optical NOT logic gate, which gives inversed value of data stream A at wavelength λ 2 at the output.

The role of amplified spontaneous emission (ASE) noise
As the pulse trains go through the amplifier, spontaneous emission will be added to the initial wave pattern in the form of white noise. This noise will reduce the signal to noise ratio, the effect is quantitatively described by the noise figure of the amplifier: With SNR in and SNR out are corresponding to the signal to noise ratio at the input and output, respectively.

Simulation results and output quality study
The simulated result can be obtained by solving rate Equations (1)-(3) and setting input light beam power within non-saturated regime. Results of XOR, AND, OR logic operations are shown in Figures 3-5, respectively (Ma, Chen, Sun, & Dutta, 2010), 2 7 − 1 pseudo random bit sequence (PRBS) data signals are used as input. The output eye diagram is also plotted as inset in each figure to show qualitatively the output quality. Quantitative quality evaluation can be done using quality factor method, as described below.
The quality factor for the output data waveform can be expressed as, Q = (S 1 − S 0 )/(σ 1 + σ 0 ) where S 1 and S 0 are the average value for all the out coming "1" and "0" data's peak power, respectively; σ 1 and σ 0 are their standard deviations. The quality factor is related to the gate's bit-error rate (BER) in Since the mechanism for the three different types of logic gates are basically the same, similar output quality for different gates can be obtained at a certain repetition rate. And the quality of this scheme is evaluated without relating to any specific logic operation.
The calculated quality factor shows significant dependence on injected current density, pulse width, transition lifetime from QD excited state to ground state τ e−g and single pulse energy.
shows the contribution to output quality from injected current and pulse width, at high logic operation bit rate, input single pulse energy is set to 0.5 pJ to make sure the operation takes place in the non-saturated regime of the QD-SOA. From the results we find that at low injected current density level (J < 1.8 kA/cm 2 ), the Q factor is lower and will increase rapidly with increased current density. This can be explained as follows: with increased current density, more carriers are injected to the wetting layer, thus each energy level in the quantum dot can recover faster to initial carrier density level after carrier depletion following optical pulse injection and amplification. This reduces the pattern effect considerably. For very high current density Q values saturate. The smaller pulse width (less energy and hence less carrier depletion) also results in better performance (higher Q value). Figure 7 shows the calculated Q factor as a function of single pulse energy and carrier transition lifetime between QD excited state and ground state. The calculation is done with an injected current density of 1.8 kA/cm 2 . From the results, we see a decrease in output quality (Q factor) with the increase in single pulse energy of the input data and τ e−g . As single pulse energy increases, the carrier density of the active region of the device is depleted more, thus it takes longer to recover to initial level. The transition lifetime determines the speed of gain and phase recovery speed in the active region, thus Q-factor is higher for shorter transition times for high-speed operation.   Gb/s operation.

All-optical logic gates using BPSK signal based on QD-SOA
Although all-optical logic gates using OOK signals based on QD-SOA-MZI have been proved at data rates of ~250 Gb/s the patterning effects and amplified spontaneous emission are very strong for the schemes using OOK signal which will degrade the output quality. Thus, an alternative method of improving the output quality and achieving high-speed all-optical logic operations has been proposed (Li, Hu, & Dutta, 2014;Li, Hu, Zhang, & Dutta, 2015). This method utilizes a QD-SOA-MZI pair each differentially driven by a data input and its complement.

Operation principles of all-optical logic gates using BPSK signal
The proposed scheme accomplishing all-optical XOR operations is shown in Figure 8. It consists of a pair of QD-SOA-MZIs. Each QD-SOA-MZI is differentially driven by data and complement. The arrangement in Figure 8, in contrast to the conventional single SOA-MZI XOR setup, ensures that each QD-SOA receives a nearly constant-power stream of input pulse train. This is also illustrated in Figure 8 using an example of an on-off keyed (OOK) signal A = [101]. Hence, the patterning effects can be mitigated that arise from the fluctuation in the signal optical powers when QD-SOAs are directly modulated by OOK signals without a differential setup. For instance, the most deleterious situation is avoided, where the QD-SOAs receive a long sequence of 1's followed by a long sequence of 0's, or vice versa. Furthermore, because BPSK signals carry information on the phase part while keeping the amplitude as a constant, the impairments from optical nonlinear effects and amplified spontaneous emission are greatly reduced. The working principle as follows: the top QD-SOA-MZI converts the input OOK data streams A and its complement into BPSK signal, exp(jπA). The bottom QD-SOA-MZI similarly outputs a BPSK signal exp(jπB). The conversion of OOK into BPSK was first used for alloptical wavelength conversion of DPSK signals and its process is detailed in Kang et al. (2005Kang et al. ( , 2008. The next step in XOR operation is the linear optical interference between these two BPSK signals. The  interference yields two OOK signals, one is XOR logic and the other is XNOR logic. The intensity envelops of the output signals emerging from the constructive and destructive ports of the 2x2 coupler are calculated using: We can use a similar scheme to realize logic AND and NAND operations as shown in Figure 9. From Boolean algebra, we know Ā XOR Ā + B = A AND B. In this scheme, the top QD-SOA-MZI converts the input OOK data A and its complement A into BPSK signal exp(jπA).The bottom QD-SOA-MZI similarly outputs a BPSK signal exp(jπ (A + B)). Thus, one output after interference is A XOR(A + B) which is the same as A AND B and the other output after interference is A NAND B. A + B is simply realized by an optical coupler.

Numerical simulation results
Simulated results of all-optical XOR, AND, and NAND logic gates using the schemes in Figures 8 and  9 are shown in Figures 10-12 (Li et al., 2014. The output eye diagrams are also plotted to show the output quality. From the simulated results, it is shown that all-optical XOR, AND, and NAND logic gates using BPSK signal, scheme of a pair of QD-SOA-MZIs, @ ~250 Gb/s are feasible and have improved output quality.

All-optical latches using QD-SOA
All-optical latches are important for a wide range of applications including communication systems, optical random access memory (RAM), and encryption. For communication system, it can be used for SONET scrambling and descrambling. The basic optical latches are the Set-Reset latch and the D-Flip-Flop. Both of these types of devices can be built using all-optical Boolean logic operations such as NAND and NOT. These operations are also important for all-optical signal processing such as bit pattern matching, PRBS generation, and label swapping.

Schematic of all-optical latches and QD-SOA structure
The Set-Reset Latch is considered as one of the most basic logic circuit possible. This simple latch is basically a one-bit memory bistable device that has two inputs, one of which will "SET" the device (meaning the output = "1"), and another which will "RESET" the device (meaning the output = "0"). Then the SR description stands for "Set-Reset." The reset input resets the flip-flop back to its original state with an output Q that will be either at a logic level "1" or logic "0" depending upon this set/reset  condition. The simplest way to make Set-Reset Latch is to connect together a pair of cross-coupled 2-input NAND gates. The schematic of Set-Reset Latch and the truth table for the Set-Reset function are showed in Figure 13.
The D-Flip-Flop is also widely used as the building block of a logic circuit. It is also known as a data or delay flip-flop. The D-Flip-Flop captures the value of the D-input at a definite portion of the gate cycle (such as the rising edge of the gate pulse). That captured value becomes the Q output. At other times, the output Q does not change. The D-Flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line. We can use the NAND and NOT gates to make a D-Flip-Flop. The schematic of D-Flip-Flop and the truth table for D-Flip-Flop function are showed in Figure 14.
Because the NAND operation is just a series combination of AND and NOT operations, then we can realize the all-optical logic NAND operation using this QD-SOA-MZI scheme as shown in Figure 15.   The first QD-SOA-MZI serves in the system as an optical logic AND gate. After screening out all other wavelength components using a band-pass filter (BPF), the A AND B output data stream (λ 2 ) is amplified to desired power by an amplifier and guided into port 5 as data to one arm of the second MZI for INVERT operation. In this way, the result centered at λ 1 coming out of port 8 will be the INVERT of signal injected into port 5, which is the same as logic A NAND B. Based on Figures 13 and 14, NAND logic gate is the building block of all-optical latches such as Set-Reset and D-Flip-flop. Thus, we can use the QD-SOA-MZI system in Figure 15 to realize all-optical latches.

Simulation result
Simulated results of logic gate NAND, Set-Reset latch and D-Flip-Flop are shown in Figures 16-18, respectively (Li, Hu, & Dutta, 2013a;Li, Ma, Hu, & Dutta, 2012a). The output eye diagram is also plotted to show the output quality. Based on the simulated results in Figures 16-18, it is proved that all-optical Set-Reset latch and D-Flip-Flop operation @ ~250 Gb/s is feasible.  Notes: The above set of figures is for 250 Gb/s data rate.

All-optical encryption and decryption using QD-SOA
Encryption and decryption has long been used by governments to facilitate secret communication.
It is now commonly used in protecting information within many kinds of civilian systems. For example, encryption can be used to protect data being transferred via Internet, mobile telephones, wireless intercom systems and prevent unauthorized use or reproduction of copyrighted material. In an encryption scheme, the message is encrypted using an encryption algorithm. This is usually done with the use of an encryption key, which specifies how the information is to be encoded. An encryption scheme usually needs a key-stream generator to randomly produce keys. The PRBS can be used as the key for encryption and decryption.
The PRBS using linear feedback shift registers (LFSR), which were first introduced in electronics, are characterized by its simplicity of generation, good repeatability, and statistical properties (Golomb, 1967). It thus received wide application, including in simulation of noise in signal transmission, data encryption/decryption, and in bit error rate testers (BERT) (Zoiros, Houbavlis, & Kalyvas, 2004). The recent achievements in photonics signal processing spurred more interest toward realizing highspeed all-optical PRBS generation. A PRBS can be generated using a linear feedback shift register (LFSR) (Senior, 1985). The PRBS sequence generated with a shift register of length m has a period of 2 m − 1. To generate a stable all-optical PRBS sequence using LFSR, an optical XOR logic gate is needed. A model to simulate the process of high-speed all-optical encryption and decryption is presented in (Li et al., 2013b). The encryption algorithm and the key we used in this model are XOR operation and PRBS. Both of the high-speed all-optical XOR operation and PRBS are realized using the QD-SOA Mach-Zehnder interferometer. Two other kinds of more secure key-stream generators: cascaded design and parallel design were also designed and investigated.

Schematic of all-optical encryption and decryption
The logic XOR operation can be used to realize the encryption and decryption of the message. The message can be encrypted by applying the bitwise XOR operation to every character using a given key. To decrypt the coded message, we merely reapply the XOR operation with the same key which is used for encryption. The schematic of encryption and decryption using the same key are shown in Figure 19. The high-speed all-optical logic operations which are used for all-optical encryption and decryption are realized using QD-SOA-MZI as shown in Figure 2. Notes: The above set of figures is for 250 Gb/s data rate.

Generation of the key
The key used for encryption and decryption is high-speed all-optical PRBS which is generated by a linear feedback shift register (LFSR) composed of QD-SOA-based logic XOR and AND gates, shown in Figure 20(a). An LFSR has m data storing units (optical delay line in all-optical system), each unit is capable of storing one binary data bit for one clock period (Kalyvas, Yiannopoulos, Houbavlis, & Avramopoulos, 2003). The whole system is synchronized with a clock. At each period, the nth and mth bit go through an XOR process (Ma, Li, Hu, & Dutta, 2012). Their XOR result gets reshaped and its wavelength is converted back to system's operation wavelength through an AND gate, and then goes back to the front of LFSR. The output PRBS signals can be tapped from the end of the LFSR. Figure 20(b) shows the design of the logic functional unit. The main parts of this unit are two Mach-Zehnder interferometers (MZI) each arm of which has a semiconductor optical amplifier (SOA) with a quantum dot (QD) active region. The first MZI serves as an all-optical logic XOR gate for the two bits (m, n), while the other MZI serves as logic AND gate.
The PRBS sequence generated using this scheme has a repetition bit period of T = 2 m − 1. Basically, the PRBS sequences are different from truly random bit sequences in that the latter has a continuous spectrum while the former has a discrete spectrum with harmonics . As m increases, the generated PRBS spectrum becomes more and more continuous and the output can better represent a truly random signal. The frequency space between two neighboring lines in the frequency spectrum of PRBS sequences is given by    Notes: The same key stream is used for both encryption and decryption.
where f b is the bit rate. From the above equation, we can see as m increases the frequency space becomes smaller which means the PRBS frequency spectrum becomes more and more continuous. Thus, as m increases the randomness of PRBS sequence becomes better.
Two other kinds of more secure key-stream generators, cascaded design and parallel design were also presented, shown in Figures 21 and 22 (Akiyama, Wada, et al., 2000). The cascaded design consists of three cascaded linear feedback shift registers (LFSR) which can generate all-optical PRBS. The output of the first LFSR can be used as the input of the second LFSR and the output of the second LFSR can be used as the input of the third LFSR. All these three LFSR are realized using the QD-SOA MZIs. The parallel design is composed of three linear feedback shift registers (LFSR), an INVERT gate and a XOR gate. The output of the first LFSR and its invert are used as the input of the second LFSR and the third LFSR, respectively. The final output is the XOR of the output of second LFSR and third LFSR. The three LFSR and all the logic gates are realized using QD-SOA MZIs too.

Simulation results
The simulated results of encryption and decryption for the QD-SOA-based XOR operation are shown in Figure 23 (Li et al., 2013b). Input data are on the top right and a key (chosen any of bots in this case) is shown on top left. The encrypted in XOR of the input data and key is shown on bottom left. The decrypted data which should be the original data is shown on bottom right. Note that top right and bottom right traces are identical as it should be. Thus, it is proved that all-optical encryption and  decryption operation at ~250 Gb/s is feasible. The Q factor was also calculated for the decrypted data in Figure 23. The Q factor is 8.7, which means a good quality of the decrypted data.
The key used for encryption and decryption is high-speed all-optical PRBS. The all-optical PRBS generated by a 7-bit optical LFSR is simulated by modeling the logic XOR and AND operations based on QD-SOAs as shown in Figure 24. The numerical simulation results of cascaded design and parallel design key-stream generators are shown in Figures 25 and 26, respectively. As shown in Figures 25 and 26, the cascaded design and parallel design key-stream generators operating at ~250 Gb/s is feasible. Thus, we can use these two kinds of key-stream generators to produce various more secure keys.

Summary and perspective
The model to simulate high-speed all-optical logic gates using QD-SOA-based Mach-Zehnder interferometer was presented. Results show that QD-SOA-based MZI can perform logic operations such as AND, XOR, NOT, and NAND at high speed up to 250 Gb/s. The impact on the high-speed output