The modified alpha power law based model of statistical fluctuation in nanometer FGMOSFET

Abstract: The modified alpha power law based model of statistical fluctuation in drain current of an unconventional Metal Oxide Semiconductor Field Effect Transistor namely Floating-Gate Metal Oxide Semiconductor Field Effect Transistor (FGMOSFET) has been proposed where the nanometer FGMOSET have been focused. Unlike the previous works, the fluctuation in drain current has been expressed in a per-unit basis which is able to show the true criticality of such fluctuation, and those previously assumed approximations on FGMOSFET’s parameters have not been adopted. The process induced device level statistical fluctuations and the related correlations have been taken into account. Nonlinearity of voltage at the floating gate and dependency on voltage at the drain terminal of the coupling factors have also been concerned. The proposed model can accurately fit the 65 nm 4th generation Berkeley Short-channel IGFET Model (BSIM4) based reference obtained from the Monte-Carlo simulation by using FGMOSFET Simulation Program with Integrated Circuit Emphasis based simulation technique. If desired, it can fit those references based on smaller technologies by using the optimally extracted drain current parameters of those technologies. From our model, the statistical fluctuation reducing strategies of nanometer FGMOSFET can be obtained. Moreover, the application of the model to the candidate nanometer FGMOSFET based circuit has also been shown. *Corresponding author: Rawid Banchuin, Faculty of Engineering, Siam University, 235 Petchakasem Rd., Bangkok 10163, Thailand E-mail: rawid.ban@siam.edu

Asst. Prof. Dr. Rawid Banchuin is a member of council of engineer (Thailand) and has joined the organizing committee of the international conference on ICT and knowledge engineering which is jointly organized by IEEE, since 2012. His current research interests include circuit device with memory, fractance device and state of the art CMOS technology.

PUBLIC INTEREST STATEMENT
A special electronic device namely Floating-Gate MOSFET (FGMOSFET) has been widely used in analog and digital circuits. The performances of these circuits can be deteriorated by the process induced device level statistical fluctuations. This is because such device level fluctuations causes the statistical fluctuations in circuit level parameters. Thus the analytical model of process induced statistical fluctuation in drain current which is the key circuit level parameter, of FGMOSFET has been found to be necessary and some previous models have been proposed. Unfortunately, they have certain flaws caused by their assumed approximations and modeling approach. Therefore the aforesaid model of the nanometer FGMOSFET has been developed in this work according to the reign of the nanometer technology where those flaws have been removed. The proposed model is very accurate and has been found to be beneficial to the analysis and designing of the FGMOSFET based circuit in the nanometer regime.

Introduction
The Floating-Gate Metal Oxide Semiconductor Field Effect Transistors or FGMOSFETs have been widely used in various analog and digital circuits because of their manufacturability in the standard nanometer Complementary Metal Oxide Semiconductor (CMOS) technology (Cao et al., 2012;Ramasubramanian, 2007;Saha, 2007Saha, , 2008Saha, , 2012Schinke, Di Spigna, Shiveshwarkar, & Franzon, 2011). The performances of FGMOSFET based circuits can be deteriorated by the process induced device level statistical fluctuations e.g. statistical fluctuations in threshold voltage and current factor etc., (Kelin, 2011;Pelgrom, Duinmaijer, & Welbers, 1989;Saha, 2010). This is because such device level fluctuations induce the fluctuations in circuit level parameters e.g. drain current (I D ) and transconductance etc., which in turn yield the fluctuations in parameters of FGMOSFET based circuit.
For both conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and FGMOSET, I D has been found to be the key circuit level parameter. This is because it is directly measurable and serves as the basis for determining other circuit level parameters e.g. transconductance and drain to source resistance etc. For MOSFET, the models of process induced statistical fluctuation and mismatch in I D have been proposed in many previous works which the nanometer CMOS technology has also been focused (Hasegawa, Aoki, Yamawaki, & Tanaka, 2011;Kinget, 2005;Masuda, Kida, & Ohkawa, 2009). Since these works have been done without referring to any certain circuit, their results are applicable to any nanometer MOSFET based circuit. For FGMOSFET on the other hand, it can be seen from the previous researches that most of the variability analyses have been performed in the case by case manner based on certain circuit level parameters of certain circuits only (Alejo & Moreno, 2010;Kwok & Merhrvarz, 2001;Mehrvarz & Chee Yee Kwok, 1996;Mourabit, Guo-Neng Lu, & Pittet, 2005;Rodriguez-Villegas, Yufera, & Rueda, 2004;Suresh Babu, Devi, Sekhar, & Baiju, 2009;Zhai & Abshire, 2008). So, the obtain results are not generic as they are applicable only to their dedicated circuits. Therefore the analytical modelling of the process induced statistical fluctuation in I D of a single FGMOSFET which is generic as it is not regarded to any particular circuit, has been proposed by Banchuin (2015). Unfortunately, this model become inapplicable to the nanometer FGMOSFET as it has been derived based on the micrometer CMOS technology by using the traditional square law which is hardly capable to model the nanometer CMOS technology despite the inclusion of short channel effects. According to the reign of the nanometer CMOS technology, the models for nanometer FGMOSFET have been developed by Banchuin (2016) and Banchuin and Chaisricharoen (2017). Unfortunately, the model proposed by Banchuin (2016) is inapplicable to device in the strong inversion region as it has been dedicated to the subthreshold region operated FGMOSFET. On the other hand, the model proposed by Banchuin and Chaisricharoen (2017) is applicable to the nanometer FGMOSFET in strong inversion region as the alpha power law which has been originally proposed by Takayasu and Newton (1990) has been adopted as the basis. Such alpha power law has been successfully applied to the variability analysis of deeply scaled MOSFET (Hasegawa et al., 2011;Masuda et al., 2009). However, only saturation region operated device has been considered in (Banchuin & Chaisricharoen, 2017) where certain approximations on FGMOSFET's parameters which have been assumed by Banchuin (2015), have also been adopted and the second order effects e.g. channel length modulation and mobility degradation etc., have also been neglected. Finally, both previous models proposed by Banchuin (2015) and Banchuin and Chaisricharoen (2017) have focused on the gross value of fluctuation in I D which does not show the true criticality of such fluctuation. This is because the fluctuation in I D may not be critical despite its large gross value if the ideal non fluctuated value of I D is very large and vice versa.
Motivated by these problems and the applicability to FGMOSFET based circuits of the nanometer CMOS technology, the analytical model of process induced statistical fluctuation in I D of nanometer FGMOSFET has been proposed in this research by using the per-unit approach which has been adopted in the previous studies on statistical fluctuation in I D of both MOSFET (Hasegawa et al., 2011) and FGMOSFET (Banchuin, 2016). In order to cover the second order effects formerly neglected by Banchuin and Chaisricharoen (2017), the modified alpha power law has been adopted as the basis. Moreover, the approximations on FGMOSFET's parameters which have been assumed by both Banchuin (2015) and Banchuin and Chaisricharoen (2017), have not been used. Apart from the proposed model and its verification, the model based statistical fluctuation reducing strategies of nanometer FGMOSFET and the application of the model to the candidate nanometer FGMOSFET based circuit has also been shown in this work. In the subsequent section the basic operating principle of the FGMOSFET and the modified alpha power law will be subsequently summarized.

Basic operating principle of FGMOSFET
FGMOSFET is a unique variant of MOSFET with a special additional gate entitled floating gate which is isolated in the oxide (Pandey & Gupta, 2010). A cross sectional view of an N-type FGMOSFET with N inputs implemented as N discrete input gates where N > 1, can be shown in Figure 1. The dimension of any ith input gate where {i} = {1, 2, 3, …, N} determines the magnitude of its input capacitance, C i . The symbol and equivalent circuit FGMOSFET which composes of a MOSFET as the core, N input capacitances (C 1 , C 2 , C 3 , …, C N ), the overlap capacitance between floating-gate and drain terminal (C fd ), the overlap capacitance between floating-gate and source terminal (C fs ) and parasitic capacitance between floating gate and substrate (C fb ), can be depicted in Figure 2.
Mathematically, the voltage at the floating gate, V FG can be given by (Pandey & Gupta, 2010) where V i , V D , V S and V B denote the input voltage at any ith input gate, the voltage at drain terminal, the voltage at source terminal and the bulk voltage respectively. Moreover, C T which denotes the total capacitance of the floating gate, can be defined as Alternatively, V FG can be given by (3) where k i , k fd , k fs and k fb stands for the coupling factor of any ith input gate, drain terminal, source terminal and bulk respectively. From (1) and (3), it can be found that these coupling factors can be defined as k i = C i /C T , k fd = C fd/ C T , k fs = C fs /C T and k fb = C fb /C T . It can also be seen that V FG is depended on V i , V D , V S and V B . For the FGMOSFET in triode region, V FG is a nonlinear function of V D (Saha, 2012). Since C fb depends on V D , so does C T thus k i , k fd , k fs and k fb are functions of V D since they depend on C T . For the device in saturation, C T is independent of V D as C fb does. Therefore k i , k fd , k fs and k fb are also independent of V D and V FG become a linear function of V D instead.

The modified alpha power law
The modified alpha power law can be simply thought of as the alpha power law with some further modification for covering the aforementioned second order effects. Such modification is to include the second order effect related parameters i.e. the channel length modulation coefficient (λ) and the mobility degradation coefficient (θ). As a result, the original alpha power law based analytical expressions of I D of the MOSFET in triode and saturation region which can be respectively given by (4) and (5) (Hasegawa et al., 2011;Takayasu & Newton, 1990), become (6) and (7) where α, β, V DS , V DS,sat , V GS and V TH denote the velocity saturation index, current factor, drain to source voltage, drain to source saturation voltage, gate to source voltage and threshold voltage respectively.
(3) It should be mentioned here that the linear model of mobility degradation (Hong, Cheng, Roy, & Cumming, 2011) has been used for deriving (6) and (7) simplicity. In the subsequent section, the proposed model will be derived.

The proposed model
The derivation of the proposed model has been performed in a per-unit approach which has been chosen because the per-unit fluctuation in I D is defined as the fluctuation in I D normalized with respected to the ideal non fluctuated value. Therefore it is able to show the true criticality of the fluctuation as large value of per-unit fluctuation in I D refers to large fluctuation in I D compared to the aforesaid ideal non fluctuated value and vice versa. The process induced device level statistical fluctuations and the related correlations have been taken into account. Moreover, nonlinearity of V FG and dependency on V D of k i , k fd , k fs and k fb which are the important features of FGMOSFET in triode region (Saha, 2012), have also been concerned. In the next subsection, part of the model for triode region operated FGMOSFET will be presented.

Triode region part
Before proceed further, I D of the nanometer FGMOSFET in triode region must be firstly derived by letting V GS in (6) be replaced by V FG −V S . According to Banchuin (2015), V FG of the FGMOSFET in triode region can be given by where α im , α dm , α sm and α bm denote the coefficients of mth terms of the series expansion of k i , k fd , k fs and k fb respectively.

Saturation region part
Similarly to the previous subsection, I D of the nanometer FGMOSFET in saturation region must be firstly formulated. For doing so, V GS in (7) must be replaced by V FG -V S . Unlike the previous work of Banchuin (2015) and Banchuin and Chaisricharoen (2017), it has not been assumed here that k fs << 1.
As k i , k fd , k fs and k fb of the device in this region are independent of V D , (3) (28), the sensitivity terms of (29) can be given as follows (27) ΔX∕X,ΔY∕Y =

E[(ΔX∕X)(ΔY∕Y)]
ΔX∕X ΔY∕Y (28) Similarly to those of (11) which can be given by (12)-(25), the above sensitivity terms of (29) are also deterministic as they have also been derived by using the nominal FGMOSFET's parameters. Despite this, (29) is capable to model the randomness of ΔI D /I D of the FGMOSFET in saturation region as such randomness is caused by those of ΔV TH /V TH , Δβ/β, ∆k i /k i , ∆k d/ k d , ∆k s /k s , ∆k b /k b , ∆α/α, ∆λ/λ or ∆θ/θ which are random variables. This also yields the validity of the proposed model.
From (29), it can be observed that the fluctuation in V DS,sat does not affect I D of the FGMOSFET in saturation region because I D is not a function of V DS,sat as can be seen from (28). Similarly to that of the device in triode region, ΔI D /I D of the nanometer FGMOSFET in saturation region has also been found to be a zero mean random variable as each corresponding ΔX/X is. However, it can be also seen that ΔI D ∕I D is nonzero. This is because ΔX∕X 's which are now referred to the standard deviations of ΔV TH /V TH , Δβ/β, ∆k i /k i , ∆k d/ k d , ∆k s /k s , ∆k b /k b , ∆α/α, ∆λ/λ and ∆θ/θ, are nonzero. As a result, ΔI D ∕I D can be obtained by taking the statistical correlations of such corresponding ΔX/X's is into account as given by (39) which the first nine terms have been contributed by ΔX∕X 's and the others are caused by the statistical correlations. (34)

The model verification
In this section, the accuracy of the proposed model will be verified under the assumption that C i >> C fd , C fs and C fb which has been adopted in many previous works on FGMOSFET (Banchuin, 2015;Banchuin & Chaisricharoen, 2017;Pandey & Gupta, 2010;Rodriguez-Villegas et al., 2004;Suresh Babu et al., 2009). Unlike the previous work on nanometer FGMOSFET proposed by Banchuin and Chaisricharoen (2017) which verified the result by using 90 nm technology node, the model verification of this work has been performed based on the smaller 65 nm CMOS technology. Moreover, both N-type and P-type nanometer FGMOSFET have also been considered. For both triode and saturation region operated devices, N = 2, k 1 = k 2 = 0.5, the 4th generation Berkeley Short-channel IGFET Model (BSIM4) and the necessary parameters extracted by Predictive Technology Model (PTM) have been adopted. Noted also that L = 65 nm and W/L of 9/6 and 29/9 have been used for N-type and P-type device respectively. These aspect ratios have been chosen as they provide the best fit of (6) and (7) to the BSIM4 based I D of 65 nm MOSFET of both N-type and P-type operated in triode and saturation region respectively.
The accuracy verification has been performed by comparing ΔI D ∕I D to its BSIM4 based reference ( ΔI D ∕I D | | |ref ) obtained by using the Monte-Carlo simulation of the BSIM4 based model of FGMOSFET with 1000 runs by using Simulation Program with Integrated Circuit Emphasis (SPICE). Such BSIM4 based model can be obtained by using the equivalent circuit depicted in Figure 2 with the core MOSFET modelled with BSIM4. For solving the convergence problem, the simulation methodology with SPICE proposed by Ramirez-Angulo, Gonzalez-Altamirano, and Choi (1997) has been adopted.
Since ΔI D /I D is dimensionless and can be expressed in percentage because of its definition stated above, ΔI D ∕I D and ΔI D ∕I D | | |ref also employ these features. Therefore both of them which are expressed in terms of percentage, have been comparatively plotted against the magnitude of the voltage at the 1st and 2nd input denoted by |V 1 | and |V 2 | respectively. Noted that |V 2 | = 0 V in the comparative plots with respected to |V 1 | and vice versa. Moreover, the minimum values of |V 1 | and |V 2 | have been chosen so that the strong inversion operation of the device has been ensured. Apart from the comparative plot we also calculate the average deviation of ΔI D ∕I D from ΔI D ∕I D | | |ref (δ avr ) which can be mathematically defined as where N S denote number of the uniformly distributed sampled data points which is given by 500. Moreover, ΔI D ∕I D ,j and ΔI D ∕I D | | |ref ,j stand for ΔI D ∕I D and ΔI D ∕I D | | |ref at arbitrary jth data point respectively. Finally, it has been assumed that all ΔX∕X 's are given by 1% and the magnitude of all ρ ΔX/X,ΔY/Y 's are given by 0.5 which is a reasonable estimated value as mentioned by Khu (2006). In the following subsections, the model verification results will be presented.  (25) for triode part and (30)-(38) for saturation part, must be inspected. This is because these sensitivities determine the influence of each device level fluctuation to the fluctuation in I D .

Nanometer N-type FGMOSFET
Firstly, it can be seen from (15) to (32) that the influence of statistical fluctuation in β cannot be reduced by any mean. It can be interpreted from (12) that the influence of statistical fluctuation in V DS,sat can be minimized by letting V DS approaches V DS,sat with V DS < V DS,sat be satisfied for maintaining the FGMOSFET operates in triode. From (17) to (34), it has been found that the influence of statistical fluctuation in λ can be reduced by choosing the device with low λ. As the influences of these device level statistical fluctuations have been reduced, the reduction of statistical fluctuation in I D can be obtained.
At the very low voltage operating condition which the fluctuation in I D become critical, it has been found from the inspection of (13), (14), (16), (30), (31) and (33) that for the nanometer FGMOSFET in both regions. This implies that the influences of the statistical fluctuations in α, θ and V TH can be simply reduced by minimizing the ideal non fluctuated values of α, θ and V TH . As a result, the reduction of the fluctuation in I D can be achieved. Moreover, it has also been found by inspecting (18)-(25) and (35)-(38) that the influences of the statistical fluctuations in coupling factors are relatively insignificant at very low voltage condition because the coupling factor related sensitivities become extremely small. Therefore, for the nanometer FGMOSFET operated at very low voltage, the variability aware designing of the core MOSFET have been found to be more crucial than those of the input capacitors. In the subsequent section, the application of the proposed model to the candidate nanometer FGMOSFET based circuit will be demonstrated.

Application to the nanometer FGMOSFET based circuit
Here, we let the nanometer FGMOSFET based summing squarer developed by Ramasubramanian (2007) which the circuit level parameter of interested is the outward current (I out ), be our candidate circuit. This summing squarer can be depicted in Figure 7. Since I out depends on I D of F1 (I D1 ) and that of F2 (I D2 ), the per-unit process induced statistical fluctuation in I out (ΔI out /I out ) can be found as as shown in Figure 8 where the magnitude of ΔI D1 ∕I D1 ,ΔI D2 ∕I D2 has been assumed to be 0.5 which implies a reasonable medium degree of correlation between ∆I D1 /I D1 and ∆I D2 /I D2 . Moreover, A I = 1 which implies that the current mirror neither amplifies nor attenuates its input current, has been adopted. From this figure, it can be seen that ΔI out ∕I out is increased with respected to both ΔI D1 ∕I D1 and ΔI D2 ∕I D2 .
Moreover, it can be seen from (48) that reducing A I yields a reduction in ΔI out ∕I out . For illustrations, it has been found that ΔI out ∕I out = 20.785% which is due to A I = 1, ΔI D1 ∕I D1 = 11.9% and ΔI D2 ∕I D2 = 12.1%, can be reduced to ΔI out ∕I out = 15.488% and ΔI out ∕I out = 13.084% by using A I = 0.45 and A I = 0.15 respectively. However, the excessive reduction of A I causes I out with excessively low magnitude which may be covered by noise.
Before we conclude the paper, it should be mentioned here that the proposed model is also applicable to the classical long channel FGMOSFET by simply letting α = 2 and discarding λ, θ, Δα/α, Δλ/λ and Δθ/θ. This is because such long channel device has no second order effects and its behaviors can be analytically modelled based on the traditional square law which is equivalent to the alpha power law with α = 2 (Takayasu & Newton, 1990

Conclusion
The modified alpha power law based analytical model of statistical fluctuation in I D of nanometer FGMOSFET has been proposed in a per-unit basis. Unlike (Banchuin, 2016), our proposed model is dedicated to the strong inversion nanometer FGMOSFET. Unlike (Banchuin & Chaisricharoen, 2017), both triode and saturation regions have been considered, the second order effects have been taken into account and the approximations on FGMOSFET's parameters which have also been assumed in Banchuin (2015), have not been adopted. The process induced device level statistical fluctuations and their correlations, have been concerned where nonlinearity of V FG and dependency on V D of k i , k fd , k fs and k fb have also been considered. Since the proposed model has been derived without referring to any nanometer FGMOSFET based circuit, it can be applied to any of those circuits and therefore generic.
It has been found that this model can accurately fit the 65 nm BSIM4 based reference obtained by using the FGMOSFET simulation technique with SPICE and Monte-Carlo SPICE simulation. Moreover, our model can also fit those references based on deeper scaled CMOS technology nodes if the optimal parameters (6) and (7) extracted by using the data of such deeper scaled technologies have been applied. From the proposed model, the strategies which yield the reduction of fluctuation in I D , can be obtained. This is because those parameters which affect the influences of the device level statistical fluctuations can be precisely known. Moreover, the application of our model to the candidate nanometer FGMOSFET based circuit has also been demonstrated in this research. Compared to that of Banchuin and Chaisricharoen (2017), our model is able to fit those references obtained from a deeper scaled technological basis. With a simple modification, the proposed model is also applicable to the long channel FGMOSFET. So, our work has been found to be beneficial to the variability aware analysis and designing of any FGMOSFET based circuit in the nanometer regime.