Performance evaluation of efficient combinational logic design using nanomaterial electronics

Abstract: Scaling down trend of CMOS transistor is approaching its lowest point, the rational substitute for the CMOS technology to attain advance improvements in terms of size, low power, and device density usage is an imperative essential. Due to the several physical limitations and circuit bounds of CMOS technology, it is the requirement of a new possible consistent model, that has small area, high device density and low power consumption. Quantum-dot Cellular Automata (QCA) is a novel approach in this direction. This paper presents a new design of 2:4 Decoder, 2:1 Multiplexer, D-Flipflop based on QCA. In addition, a nano communication circuit has been proposed which is proficient as compared to previous designs. Hamming distance approach has been used to perform the power calculations of the proposed circuits. To authenticate the functionality of the proposed designs computational simulation results has been performed using the QCAdesigner tool. *Corresponding author: Md. AbdullahAl-Shafi, Institute of Information Technology (IIT), University of Dhaka, Dhaka, Bangladesh E-mail: alshafi08@gmail.com


PUBLIC INTEREST STATEMENT
Quantum-dot Cellular Automata is a unique computation methodology which is founded on semiconductor substantial. This standpoint article depicts four imperious circuit model of decoder, multiplexer, nano-communication circuit and reversible D flip-flop. The main meaning of the proposed layouts is designing without wirecrossing as well as consumed less number of QCA cell and area. Furthermore, the layouts are significantly lessened in terms of majority voters, cell intricacy, and latency. The proposed outlines achieved immense enhancement compared to earlier outlines. Power dissipation by the layouts indicates that all designs depleted extremely low energy. The multiplexer layout can be expended to realize complex communication system or computer memory, decoder can be used in memory system, chips and instruction decoding. The proposed nano-communication circuit can be used for protected communication.

Methodology
QCA provisions logic cases not as voltage phases but rather based on the point of separate electrons. The central features are QCA wire, inverter and majority gates.

QCA cell
Cells are the elementary entities of QCA based circuit and they are usually constituted of four quantum dots positioned at the corners of a square pattern. Each cell is charged with two supplementary electrons which channel from one low potential state to another across a high potential direction and a back plane voltage switches the cell occupancy. The electrons will be located in transversely to each other owing to reciprocal repulsive electrostatic power, possessing the utmost distance between them. A remote cell may be in one of two corresponding energy positions. These positions are called cell polarizations P = +1.00 and P = −1.00 as shown in Figure 1 (a) p = 0 denotes an unpolarized cell which covers no information. A cell polarization P is −1 if the electrons are involved the locus 2 and 4, in the same way, a cell polarization P is +1 if electrons are involved the position 1 and 3. The cell polarization equation (Lent et al., 1993) is presented below.
where, the charge at dot i denoted by ρ i (1)

QCA wire
QCA wire encompasses of series of cells where the cells are united one after another (Abdullah-Al- Abu Arqub, 2015;Islam et al., 2016). QCA wire is employed to transfer signal from one position to another in a circuit. Logical charges are moved from cell to cell because of the coulomb contacts. There are two modes of alignments in a QCA wire namely binary wire and inverter chain. QCA wires can be either originated up of 45° cells or 90° cells as shown in Figure 1(b) and (c). In case of inverter, if two cells point at 45° with regard to each other their contact will be reverse and for that, these cells are mostly employed for coplanar wire crossings.
Binary wire transfers signal with similar polarity from one place to another, while inverter chain reverses the input cell polarity when odd figures of cells are employed in it.

Majority gates
Majority gate is assembled of five QCA cells; a central cell, one output, and three inputs. Polarity of the middle cell, as identified as device cell is imposed, by the coulomb repulsion to be equivalent to the output cell. The device cell at the center of the gate has its least energy when it accepts the polarization of the majority of the three input cells since this is the formation where the repulsion among the electrons in the three inputs cells and the electrons in the device cell is the lowest. So, an arrangement of inverter and majority voter is appropriate to construct an extensive logic set for scheming any circuit.
Majority voter can operate as AND or OR logic gate depending on the static polarity of the third input of the majority voter presented in Figure 1(d) and (e). Logical 2-input AND and 2-input OR functions can be executed using majority voter by putting one input cell to binary "0" and "1", subsequently. The logical equation of the 2-input majority gate can be stated as follows.
The satisfying attainment of realizing a 3-input majority voter with five QCA cells inspired the analysts to hypothesize an inventive configuration for 5-input majority voter. Later, a specific layer (Abdullah-Al-Shafi & Bahar, 2016b) 5-input majority voter utilizing ten cells executed in a precise cell layout which is displays in Figure 1(f). The logic equation of the 5-input majority voter can be expressed as follows.

QCA inverter
The inverter is a pattern of cells that reverse the input topology from one logic to another. Usually, two categories of inverter are applied (Abdullah-Al-Shafi, 2016b) that has been operated for the realization of several structures as an essential cell (Abdullah-Al- Shafi & Bahar, 2016c;Islam et al., 2015). The inverter can be designed by fixing QCA cells at 45° position (Abdullah-Al-Shafi & Bahar, 2016b) as appeared in Figure 1(g) which is potent and mostly used in circuit design. The logic values 0 and 1 transformed to 1 and 0 because of electrostatic repulsion.

QCA clocking mechanism
To form more complicated QCA devices, the location of QCA cell is not only essential also needs to coordinate the information, so that evade having a signal extending a logic gate and proliferating before the other inputs move the gate. This specific characteristic is particularly imperative in QCA circuits, ensuring its accurate function and this aspect are attained by QCA clock. The clock is an electrical region that switches the channeling barriers within a cell, therefore retaining control when a cell may or may not be polarized. QCA clocking is produced of four periods lagging by π/2 (Hennessy & Lent, 2001) as shown in Figure 2 which generates an innovative way to conceive nano-circuit distinct from the regular CMOS circuits (Walus, Dysart, Jullien, & Budiman, 2004). In each region, a certain potential can adjust the barriers between the dots and the organization of clock zones allows a group of QCA cells to construct a particular calculation and then its positions are stationary and its outputs can be applied as inputs to the following clock zone.
Switch period: the barrier between dots of QCA cell is elevated and the dots are motivated by the electron of its adjoining as well as electron begins channeling between dots. Thus, the cell turns into polarized.
Hold period: cell barrier stays high and electron cannot channel between dots and the cell keep its existing position.
Release period: barrier between dots are decreased, the electron can channel within dots and cell comes to be unpolarized.
Relax period: barrier remains at lowered and cell stays in unpolarized position.

Proposed QCA outlines
An assay is fulfilled to acquire the required devices and selected to realize the suggested design. The composition level is permitted applying a number of approximate simulators as the nonlinear approximation methods and bistable simulation device. However, these approximate do not develop the specified measures because these methods are iterative. In time, the QCA Designer is preferred simulation tool (Walus et al., 2004). The Bistable simulation tool has been occupied in the simulation interface between cells, clearly, the contact force linking two cells decomposes contrariwise with the fifth power of the length untangling them. During this estimation, not all the cells impact are counted and cell within the radius of R are being measured. For cell i, the scientifical pattern is depicted by the following Hamiltonian.
where P j is the polarization for cell j, E k i,j is the k ink energy between the cells (i and j) and ϒ is the channeling energy. For every cell i, the amount of the hamiltonian is over all cells (viz., j) in its radius of effect R. The Jacobi algorithm has been utilized to obtain the eigenvectors and eigenvalues of the Hamiltonian. At the layout level, small QCA block is designed and simulated for analysis its precision. Later these QCA blocks are unified together through QCA wire to manage the proposed composition. Finally, the consistency of the design is surveyed by the QCA Designer. The simulation outcome the essential waveform for the logical circuit and during simulation, it created few criterion that contains default standards as the cell size, layer separation, relative permittivity, samples number etc. (4)

2:4 decoder
The proposed 2:4 decoder uses four-periods clocking zones in QCA. The QCA layout of the proposed decoder circuit is shown in Figure 3(a) using four majority voters and three inverters. The logical expression of 2:4 decoder is described as. The input signals (X, Y) are decoded as:

2:1 Multiplexer
The proposed 2:1 multiplexer has two inputs in1 and in2, one address line s and single output state. If address line s = 0, input in1 is selected, and when s = 1, input in2 performs at the output. The majority voter illustration of the function is as followed.

Nano communication circuit in QCA
The proposed complex circuit is designed using a parity checker and parity generator function. Parity initiator or generator selects bit data as an input signal and produces parity bit. Through transmission channel, the bit data and generated parity bit are directed to parity checker. Then the bits are verified by checker circuit which was covered within the message for fault detection. If the parity bit is not odd, then a fault is arises all through the transmission. The QCA layout of the proposed circuit is presented in Figure 3(c).

Reversible D flip-flop
The inputs of reversible D flip-flop is defined as in (t + 1), in2, in1 and the corresponding outputs lines are out (t), out, out1. The input arrangements from "000" to "111" allow one to one correlation with the outputs. The logical expression can be derived as in (t + 1) = out (t), in2 = out, and in1 = out1. The straight interactions between the output and input cells are presented in Figure 3(d). The proposed figure shows one to one correlation so only with certain delay, the inputs should shift the outputs unaffected.

Simulation results and performance analysis
Simulation results functionally have been obtained using the QCA Designer (Walus et al., 2004) that is a popular engine for QCA circuits. The simulation results of the proposed outlines are shown in It is very essential to create an operationally firm layout in QCA and there are certain concerns realized into account to rise the design stability. When building models in QCA, a substantial attempt should be made to maintain the wire length in a specified clocking region to a minimum.
In Figure 4(a), the input X and Y to the output signals of R 3 , R 2 , R 1 , R 0 in this unit goes through four clock levels, so the delay is an entire clock cycle. Hence the output, R 3 , R 2 , R 1 , R 0 is presented single clock cycles after X and Y have been affected. The output value of R 0 is up when the input X = Y = 0 if the input is X = Y = 0 then the output value of R 1 is low. The starting position of the output line R 0 and R 1 is shown by arrows in the figure.
In the multiplexer outline, input in1, in2 and address line s is 01010101, 00110011 and 00001111 correspondingly. The result is 01010011 as presented in Figure 4(b). From the figure, it can be studied that for the primary four clock cycles address line is zero the output is following the input in1 for these four cycles, and when address line is 1 for succeeding four clock cycles, the result is following input in2. Figure 4(c) explains the nano communication architecture, when the input bits to the transmitter are in1 = in2 = in3 = 0, then the corresponding output will be Pout = 1. In the recipient section, if the inputs are in1 = in2 = in3 = 0, the output will be Cout = 0. Similarly, others bit streams can be formed. The output Pout and Cout perform after the second cycle as indicated by arrows in the figure.
The outcome of proposed reversible D flip-flop is presented in figure 4(d) where the outputs out = out(1) = out(t) is low if all the inputs in1, in2 and in (t + 1) are low. Inputs are functional at "0" clocking region and outcome are gained at following clock zone so, the outcome is consistent and firm.
The layout intricacies in terms of the majority voters number, QCA cells, circuit thickness and the clocking zones applied to devise the circuits as presented in Table 1.
The overall enhancements of proposed decoder, multiplexer, and nano communication circuit are demonstrated in Figure 5, correspondingly.

Power consumption of the proposed outlines
The dissipation of power by each QCA cell in a circuit is identical (Abdullah-Al- Shafi & Bahar, 2016b, 2016c. Therefore, in a range of connected QCA cells, the total dispelled power can be projected by adding the dispelled power of each cell within the range. The circuit's power consumption is reliant on the logic gates operated in constructing the circuit. Apply a larger quantity of logic gates, involves larger power dissipation by the circuits. The dispelled energy of the circuit is the total of the power dissipated by all the majority voters, inverters, and the range of QCA cells. This paper, mathematical  analysis of Hamming distance based assessment of power dissipation is applied to achieve the power dissipation of the proposed circuits. The assessment is achieved using the similar temperature (i.e. T = 2.0 K) and the similar channeling energies (i.e. 0.25E k , 0.75E k , etc.). It has been described (Liu et al., 2012) that for a shift in the Hamming distance between inputs to the circuit, the energy dispelled will also be differ.
In the case of the inverter, 1 → 1 or 0 → 0 input switching means Hamming distance "0", and the inverter has dispelled the power of 0.8 meV at γ = 0.25E k and 2.7 meV at γ = 0.5E k . A ceiling Hamming distance of "3" is measured for the majority voter for 000 → 111 input switching, that affects the ceiling dissipated the energy of 41.0 meV by the majority voter at γ = 0.25E k and 41.2 meV at γ = 0.5E k . Correspondingly, dissipation of power by the majority voter and inverter for several Hamming distances was testified in. The QCA design of the proposed decoder consists of three inverters and four majority gates. Each of these majority voters has one stable input polarization. Therefore, the Hamming distance for these majority voters is measured to be "2", respectively. For maximum energy dissipation, Hamming distance "1" is measured for each of the inverters. Applying the Hamming distances related to the input to logic gates and counting the QCA arrays perform in decoder as shown in Figure 3(a), the power dissipation of the proposed decoder is analyzed. The results are shown in Table 5. An equal method is applied for figuring the power dissipation by the multiplexer and nano communication circuit and the outcomes are denoted in Table 5. Table 5 illustrates that the power dissipated by the decoder at γ = 0.25E k is 156.4 meV and at γ = 1.0E k , it is 206.8 meV. Similarly, dissipated power by the other outlines is formed which is presented in Table 5. These outcomes show that all the circuits dissipate very little heat energy. The results are also outlined in Figure 6.