Optimal configuration for cascaded voltage source multilevel inverter based on series connection sub-multilevel inverter

Abstract: In this study, a new configuration for cascaded voltage source multilevel inverter based on series connection of improved sub multilevel inverter module is presented. An algorithm is proposed to determine the magnitude of dc voltage source to generate a large number of output voltage levels with reduced device count. It is especially suitable for of renewable energy applications. To demonstrate the advantages of proposed configuration, the comparative analysis provided with other multilevel configurations in term of a number of switches, gate driver circuits and blocking voltage on switches. The comparison results confirm that the proposed configuration offers less number of components. Moreover, the magnitude of blocking voltage on switches and losses are lower in the proposed configuration. Multicarrier based sinusoidal pulse width modulation scheme is adopted for generating switching signals using dSPACE real-time controller. To validate the performance of proposed topology under steady state and dynamic condition are carried out using simulation on MATLAB/Simulink and experimental implementation. *Corresponding author: Kishor Thakre, Department of Electrical Engineering, National Institute of Technology Rourkela, Odisha 769008, India E-mail: thakrekishor26@gmail.com


PUBLIC INTEREST STATEMENT
Multilevel converters have created a new height of interest in the industrial application and research. While the conventional topologies have proved to be an applicable alternative in a wide range of high power medium-high voltage applications, there has been an effective interest in the optimal progression multilevel inverters. Reduction in a number of devices as compared to the conventional multilevel inverters (MLI) has been an important objective in the recently introduced MLI topologies. In this paper, a new configuration for cascaded voltage source multilevel inverter based on the series connection of improved sub multilevel inverter module is presented. An algorithm is proposed to determine the magnitude of dc voltage source to generate a large number of output voltage levels with reduced device count. The comparison results confirm that the proposed configuration offers less number of devices. It is especially suitable for of renewable energy applications.

Introduction
Voltage source multilevel inverters (VS-MLI) play an important role for medium and high voltage applications such as AC drives, FACTS, static VAR compensators, hybrid electric vehicles and renewable energy sources. Because of its advantages such as low total harmonic distortion (THD), less voltage stress, better electromagnetic interference and high-quality output voltage waveform (Azeez, Dey, Mathew, & Mathew, 2014;Buticchi et al., 2014;Rodriguez, Bernet, Wu, Pontt, & Kouro, 2007;Rodriguez, Lai, & Peng, 2002;Song & Huang, 2010). However, VS-MLI suffers from saviour drawbacks such as the number of power switches with related gate driver circuits and protection circuit increases with increase in the number of voltage levels. This increase system complexity, inverter cost, reduces the reliability and efficiency of the inverter. In general, there are three types of topologies for MLI; Neutral point clamped (NPC), or diode clamped, flying capacitor (FC) and cascaded H-bridge multilevel inverters (CHB-MLI) are discussed in Chavarria, Biel, and Guinjoan (2013), Khajehoddin, Bakhshai, and Jain (2008), McGrath and Holmes (2008). The CHB-MLI is most popular topology among three conventional topologies based on its modular struture and less number of componetnt. A CHB-MLI is series connection of H-bridges with isolated DC sources. The magnitude of dc source categorisied in to two configurations, symmetric and asymmetric MLI. In symmetric MLI the magnitude of dc sources are equal, on the other hand the magnitude of dc sources are unequal in the asymmetric MLIs (Lu, Marieethoz, & Corzine, 2010;Veenstra & Rufer, 2005). An asymmetric inverter increases the number of output voltage levels for same number of switches. There are two configuration for calculating the magnitude of dc voltage source, i.e. trinary and binary confirgurations. The trinary configuration generates high number of voltage level as compared to binary configuration (Gupta & Jain, 2012). Another hybrid MLI, have presented in Babaei and Gowgani (2014), Rech and Pinheiro (2007). consist of different MLI topologies with unequal dc volatge source and different switching schemes.
A topology introduced in Babaei (2008) to overcome the mentioned issue (Babaei et al., 2007;Haque, 2004), but topology uses only single H-bridge which is bound for high voltage applications. Moreover, this configuration needs a large number of bidirectional switches and MBV is high. Another configuration presented in Ebrahimi et al. (2012), which composed of series connection of sub-module with H-bridge for generating the great number of voltage levels. It needs lower number of switches as compare to Babaei (2008) and same MBV. In Shalchi Alishah et al. (2015), a new cascaded MLI has been presented with fewer numbers of switches as compared to Babaei (2008), Ebrahimi et al. (2012). The main drawback of MLIs are requires a high number of switches, gate drivers and MBV across the switches.
This study presents a new configuration for VS-MLI, which can be a solution of all above discussed issues.

Proposed configuration
The proposed configuration for a voltage source multilevel inverter is shown in Figure 1. This configuration consists of one H-bridge and a basic unit cell. The basic unit contains p bidirectional auxiliary switches, which have been presented in Gautam, Gupta, and Kumar (2015), Gautam, Gupta, and Sahu (2016), Odeh and Agu (2016), Raushan, Mahato, and Jana (2016) and (p + 1) dc sources. Table 1 shows the look-up table for switching states for different output voltage in proposed sub-MLI; its magnitude of isolated dc source is uniform. Therefore, this MLI is called symmetric VS-MLI. In the proposed configuration the number of output voltage levels, number of switches and gate drivers can be calculated as follows.
where p is the number of auxiliary switches in the basic unit. In the proposed VS-MLI the maximum output voltage V 0,max is (1) Figure 2 shows the generalised configuration of proposed cascaded VS-MLI for generating higher voltage level with reduced switch count. The output voltage of cascaded VS-MLI is summation of each sub-MLI voltages, which can be calculated using The proposed cascaded VS-MLI consists of n number of sub-MLI with unequal magnitude of dc voltage source. However, in each sub MLI having same magnitude of dc voltage source. The magnitude of the dc source for each sub MLI must be chosen from the following algorithm; Sub MLI-1: In this sub MLI-1, the peak amplitude of output voltage (V 01,max ) is obtained as follows (4)   Thakre et al., Cogent Engineering (2016) Sub MLI-2: Therefore, the peak amplitude of output voltage (V 02,max ) is given by Sub MLI-3: Sub MLI-n: The number of output voltage levels can be calculated by the following equation: In the proposed configuration, the number of power switches including auxiliary switches and unidirectional switches is given by By using the proposed algorithm, the maximum amplitude of the output voltage (V 0,max ) is expressed, as follows:

Maximum number of voltage levels with constant number of switches
The main objective of a multilevel inverter is to generate higher voltage levels with minimum number of switches. The product of number of voltage levels, whose sum is constant, when the numbers of auxiliary switches are same in each basic unit.
Using (13) and (15) can write The value of p must be determined. Using (12) and (15), the maximum number of output voltage level will be determined as follows: Considering (16) and (17), can express Figure 3(a) shows the variation of (2p + 3) {1/(p + 4)} vs. p. It clear that maximum number of output voltage levels is obtained for p = 2. Thus, cascaded VS-MLI consisting of two auxiliary switches can produce the maximum output voltage levels.

Maximum number of voltage levels with constant number of isolated dc sources
As seen from Figure 2, the proposed configuration consist of n sub MLIs and each of them consist of (p n + 1) isolated dc sources (j = 1, 2, … , n). Thus, the number of dc sources can be obtained by: Using (17) and (20), the maximum number of output voltage levels can be written as: Figure 3(b) shows the variation of (2p + 3) 1/(p + 1) vs. p. Thus, the configuration consisting of sub MLIs with one dc source can generate maximum output voltage levels.

Minimum number of switches with constant number of voltage levels
In this part, the question is which configuration can generate N level with minimum number switches? Using Equation (18), the total number of switches can be obtained as follows: Since N level is constant, N switch will be minimised. Figure 3(c) shows that the minimum number of switches is provided for p = 2.

Minimum number of gate drivers with constant number of voltage levels
In the suggested configuration for cascaded VS-MLI the total number of switches and gate driver circuit are equal. Hence, the minimum number of gate drivers using Equation (22) can be written as follows:

Minimum blocking voltage across the switches with constant number of voltage levels
An essential problem in multilevel inverters is the rating of circuit switches. In all MLIs, current through all switches are same as rated load current. But, this is not for the voltage across the switches. The aim is to find the configuration for cascaded VS-MLI with minimum blocking voltage which can generate constant number of output voltage levels. The maximum magnitude of blocking voltage (V switch ) is expressed as follows: where V switch,A and V switch,B are the maximum magnitude of blocking voltage across the auxiliary and unidirectional switches, respectively. Also V switch,a,j and V switch,b,j shows the maximum value of blocking voltage across auxiliary switches in jth sub MLI and unidirectional switches in the jth H-bridge, respectively. Hence, Equation (25) can be considered as a criterion to compare different MLIs from the view point of the peak value across the switches (Babaei, 2008;Ebrahimi et al., 2012;Shalchi Alishah et al., 2015). The lower value of the criterion indicates that a minimum voltage across the switches. As conclude from Figure 2, peak value of blocking voltage across the auxiliary switches in jth sub MLI can be expressed, as follows: Therefore, the peak value of the blocking voltage across the auxiliary switches can be calculated, as follows: In the Equations (26) and (27), S is determined by the following expression: From (5)-(12), (15), (27) and (28), the maximum voltage across auxiliary switches in basic units can be written as follows: The maximum value of the blocking voltage across the unidirectional switches in the jth H-bridges can be given as follows: The maximum value of blocking voltage across the H-bridge switches can be expressed as follows: Hence, the MBV across all the switches of proposed configuration using (24) can be expressed, as follows: The curve is drawn between {S/(2p + 2)}+1 and p is shown in Figure 3(d). As seen this curve, V switch is minimum at (p = 1) for proposed cascaded MLI.

Minimum number of ON-state switches with constant number of voltage levels
In the proposed configuration, the number of ON-state switches (N ON-SS ) can be calculated by: Using (15)-(17) and (35), the number of ON-state switches is given as follows: As shown in Figure 3(e), the minimum number of ON-state switches to generate maximum number of output voltage levels is obtained for p = 1.

Switching scheme
The multicarrier based modified pulse width scheme have been used for the proposed topology, the associated signals are shown in Figure 4. A modulating signal, F m (t) is a sinusoidal waveform of magnitude A m with frequency F m = 50 Hz and fourteen (N L −1) triangular signal used as carrier F cr (t) with frequency f cr = 2KHz for SPWM. Here amplitude of carrier A cr and carrier above the zero reference are denoted as F + cr,j (t) and those below the zero reference are denoted as F − cr,j (t), {j = 1 to m}. Carrier signals are arranged such that the band occupy contiguous, in phase opposition disposition level-shift multicarrier SPWM. The amplitude modulation index (M a ) and frequency modulation index (M f ) are defined as Each carrier is compared with a modulating wave, the carrier signals above the zero reference, each comparison gives "ON" if the reference signal is greater than the carrier signal and "OFF" otherwise. For all carrier signals below the zero reference, each comparison gives "OFF" if the reference signals greater than the carrier and "ON" otherwise.
The generated signals from comparator are added so as obtained as "combined signal" denotes as The combination signal "g comb (t)" that acquires the same wave shape as that of the staircase output voltage waveform is shown in Figure 4, the actual switching signals are obtained from combined signal by comparing the desired level signals and generated look-up table.

Calculation of losses
The reduction in the number of switches has a significant effect on the inverter losses as the conduction loss depends on ON-state voltage drop of power switches and equivalent resistance and the switching losses depend on the non-ideal operation of power switches. The power losses are calculated as follows.

Conduction loss
The conduction loss occurs during the ON-state switch. Therefore the conduction loss is determined by product of ON-state voltage drop and current through the device (Raushan et al., 2016). The knee voltage of the auxiliary switch as shown in Figure 1 is the sum of knee voltage of two diodes and a MOSFET. Therefore, ON-state voltage drop across the auxiliary switch can be calculated as follows: where V T and R T are ON-state voltage and the equivalent resistance of MOSFET, respectively. β is a constant dependent on MOSFET parameters. V D and R D represents ON-state voltage and resistance of the diode, respectively. If the MLI operating at large number of voltage level, the load current can be assumed is almost as a sinusoidal. The instantaneous conduction loss (P c,A (t)) can be given as: In the proposed VS-MLI, p numbers of auxiliary switches are present accompanied by H-bridge unidirectional switches i.e. MOSFET with body diode. Hence, the instantaneous conduction loss of the unidirectional switches (P c,U (t)) can be calculated as To calculates the total conduction loss, it is required to define the switches count, N S (t) and diodes, N D (t) at any instant in H-bridge. It is noticeable that, output voltage level and operating conditions (in the current direction) affect the quantity of ON-state switches that is time-variant. Considering (P Cn,A (t)) as instantaneous conduction loss of nth auxiliary switch, The average conduction losses are written as follows

Switching losses
To calculate the total switching loss of the proposed inverter, the energy loss during ON and OFFstate of a typical power switch with the body diode is considered first and then that amount is applied to the proposed inverter. Suppose that the voltage and current varies linearly during ON and OFF time a switch can be expressed as follows.
where E on and E off are ON-state and OFF-state loss energy and t on and t off are the ON and OFF-state period of the switch respectively. I is the current through the switch and V sw is voltage across the switch before turned-OFF or turned-ON. The total switching loss can be obtained as follows.
where f is the fundamental frequency. N on is the number of ON-states and N off is the number of OFFstates. The total power losses of proposed inverter can be obtained using (46) and (49) as In this study, following parameters are considered to determine the power loss of proposed cascaded VS-MLI: R T = 0.25 Ω, R D = 0.11 Ω V T = 2.5 V, V D = 1.2 V, β = 1, t on = t off = 1 μs, f = 50 Hz. Each isolated DC voltage source has magnitude 12 V. The load resistance is 15 Ω. The mathematical calculation is carried out for each switch (MOSFET) for one cycle using Equations (42)-(50) and total power loss for one second is obtained as 3.624 mW.
(50) Total power losses, P Loss = P C,Avg + P sw

Results and discussion
To verify the performance of proposed configurations, the simulation using MATLAB Simulink environment and experimental studies are presented, for 15-level inverter based on single sub-MLI as shown in Figure 1 and 25-level inverter using cascaded VS-MLI as shown in Figure 2.

Simulation results
The equivalent circuit of 15-level inverter of proposed configuration is depicted in Figure 6(a), the circuit consist of six auxiliary, four unidirectional switches and seven DC sources with the magnitude of 12 V, which produce the staircase voltage waveform of maximum output voltage 84 V. A series

Experimental results
To validate the simulation and effectiveness of the proposed configuration, a prototype of proposed single phase 15-level and 25-level inverter have been developed in the laboratory. The hardware implementation of 15-level inverter is shown in Figure 8. It consists of IRF540 MOSFETs, which are driven by MCT2E optocouplers. The load parameters are used same as in simulation study. dSPACE DS 1104 real time controller has been used for real-time simulation for switching control design in MATLAB/SIMULINK environment. The developed code of Simulink model of switching algorithm is electronically generated by real time of MATLAB in conjunction with real-time interface of dSPACE. The generated C-code is downloaded into dSPACE hardware for implementation and generation of switching signals for MOSFETs switches. A digital oscilloscope of TEKTRONIX TPS 2014C and power analyser (FLUK-434) are used for recording all the waveforms. The output voltage and load current waveforms of implemented 15-level and 25-level inverter at 2 kHz carrier frequency with harmonic spectrum are shown in Figures 9 and 10. The experimental results have corroborated with simulation results.
To analyse the dynamic performance of the proposed configuration, the change in load at output terminals and a step change in modulation index at input side are considered for 15-level inverter. The response is shown in Figure 11 for a variation in load. The load variation is obtained by adding extra resistance and thereby load current is changed in inverter. It is observed that the change in load current does not influence the output voltage. A step change in modulation index (m = 0.6 and 0.3 for 0.02 s) in 1 cycle (20 ms) is applied as shown in Figure 12(a). The output voltage levels are reduced to 5-level from 15-level and also load current has been decreased during change in modulation index as depicted in Figures 12(b) and (c).

Conclusion
In this study, an optimal configuration for cascaded VS-MLI has been presented. In comparison with other mentioned topologies, the proposed configuration needs the least components count. The reduction in number of components leads to reduce the installation area, cost economy, simple modulation control and less power loss which improves the efficiency of inverter. In addition, the voltage stress on switches has reduced, and also maximise the higher voltage levels. A modified multicarrier based pulse width modulation scheme has presented for proposed 15-level inverter. The performance of proposed cascaded VS-MLI under steady state and dynamic conditions has been verified through simulation and experimental on single phase 15-level and 25-level inverter prototype. The proposed cascaded VS-MLI is to be suitable for high voltage application due to reduced voltage stress on switches.