Optimized design and performance analysis of novel comparator and full adder in nanoscale

: In a vastly rapid progress of very large scale integration (VLSI) archetype, it is the requirement of moment to attain a consistent model with swifter functioning speed and low power utilization. Quantum-dot Cellular Automata (QCA) is an inimita-ble transistorless computation approach that is based on semiconductor substantial and a substitute for customary CMOS and VLSI archetype at nanoscale point which comprises a better switching frequency, enhanced scale integration and small extent. In the design of digital logic, a comparator is the essential forming component which implements the resemblance of two numbers and a binary full adder is a major entity in digital logic systems. This paper deals with an expanded layout of reversible 1-bit comparator and proficient full adder without wire-crossing in QCA. The proposed lay-outs are significantly declined in terms of area and cell complexity, assessed to other layouts and clock cycle is retained at least. Quantum costs of the proposed circuits are estimated and compared, that shows the proposed QCA layouts have lesser quantum cost equated to regular designs and the energy depletion by the circuits endorses the view of QCA nano-circuit attending as a substitute level for the completion of reversible computing. Under thermal unpredictability, the constancy of the proposed designs is evaluated which show the operating efficacy of the designs. The simulation outcomes in QCADesigner tool approve that the presented designs performs properly and can be operated as an extreme performing design in QCA technology.

ABOUT THE AUTHORS Md. Abdullah-Al-Shafi received his BSc (Engg.) in Information and Communication Technology in 2015. Currently pursuing a MS in Information Technology (IT) in Institute of Information Technology (IIT), University of Dhaka, Bangladesh. He has authored papers in international journals and conference. His research area includes Distributed Computing, Quantum-dot Cellular Automation, Intelligent System and Wireless Sensor Network. https://www.researchgate.net/ profile/Abdullah_Al-Shafi.
Ali Newaz Bahar is currently working as assistant professor in the Department of Information and Communication Technology (ICT), Mawlana Bhashani Science and Technology University, Bangladesh. He has more than 25 research publications. His research area includes Quantum-dot Cellular Automation, Big Data Analysis, Distributed Computing and Fuzzy Logic. https://www.researchgate.net/profile/Ali_Bahar5.

PUBLIC INTEREST STATEMENT
Here has been cumulative concern in recent years that the limits of what can be attained with current approaches to improving device performance will soon be reached. Quantum-dot cellular automata (QCA) have been proposed as a means of getting around these limitations of CMOS technology. This standpoint article depicts two imperative QCA designs of comparator and full adder. The main significance of the proposed model is designing without wire-crossing where its top counterparts designed through wire crossing. Quantum cost of the proposed comparator is only five which is much reduced than existing and other proposed designs and attained 44.45% improvement compared to existing layout. Power dissipation analysis indicates that both design depleted extremely low energy.

Introduction
In the proximate future, it is predictable that the usual CMOS archetype extends to the culmination of its roadmap due to numerous thoughtful disputes as impurity discrepancies, elevated outlay of lithography and more notably (Lent, Tougaw, Porod, & Bernstein, 1993;Tóth & Lent, 1999;Wilson, Kannangara Geoff Smith, Simmons, Raguse, & Raguse, 2002). Various technological prototype for instance Resonant Tunneling Diode, Field Effect Transistor (FET) based on Carbon Nanotube and Quantum-dot Cellular Automata have been come out to explain the revealed complications (Amlani et al., 2000;Rumi, Walus, Wang, & Jullien, 2004). As per the international technology roadmap for semiconductors (ITRS) statement that proposes a precise brief of potential archetypes, QCA is one of the pledging upcoming solutions (The International Technology Roadmap for Semiconductors, 2001) and in recent times has been accepted as one of the eminent six evolving archetypes with potential utilizations in forthcoming computing. QCA prototype is centered on a precise primitive fact, termed coulomb repulsion that utilizes position of electron sets rather than voltage points for logical approaches. The data is embodied by polarizations of the cell, which are organized by inputs and clock phases (Tougaw & Lent, 1994;. A main improvement of QCA nano-device is the simple interconnection that is feasible with this archetype. As the cells connect merely with their adjacent neighbors, there is no necessity for extensive interrelation lines. Separate phases like algorithmic and material based models are analyzed in QCA. In top level outlines, consideration is on the algorithmic and rational outline along with the material outline. Though, physical connections can be problematic in device operation and organize of the physical connections is an obligatory difficulty in the actual QCA circuit outlines, particularly in outsized systems (Cho & Swartzlander, 2007). The QCA circuits have been formed and enhanced in the terms of area, complexity, and latency (Abdullah-Al- Shafi & Bahar, 2016a;Al-Shafi, 2016). Several logical designs as adders (Cho & Swartzlander, 2005;Hashemi, Tehrani, & Navi, 2012;Navi, Farazkish, Sayedsalehi, & Rahimi Azghadi, 2010;Rumi et al., 2004;Shams & Bayoumi, 2000;Vetteth, Walus, Dimitrov, & Jullien, 2002) and sequential circuits (Kummamuru et al., 2003;Momenzadeh, Huang, & Lombardi, 2005;Niemier & Kogge, 2001;Walus, Jullien, & Dimitrov, 2003;Yang, Cai, Zhao, & Zhang, 2010) are applied in QCA archetype. This paper proposed a new QCA comparator and full adder layout in single layer which is enriched in term of cell and area complexity in contrast to other designs (Abedi, Jaberipur, & Sangsefidi, 2015;Angizi, Alkaldy, Bagherzadeh, & Navi, 2014;Basha & Kumar, 2012;Cho, 2006;Cho & Swartzlander, 2009;Das & De, 2015;Dehghan, Roozbeh, & Zare, 2014;Hänninen & Takala, 2010;Hashemi & Navi, 2015;Kianpour, Sabbaghi-Nadooshan, & Navi, 2014;Kim, Wu, & Karri, 2007;Navi et al., 2010;Pudi & Sridharan, 2012;Vetteth et al., 2002). The quantum costs and power depletion by the proposed designs are assessed besides constancy of the circuits under thermal roughness is evaluated in this paper. The outcomes of the simulation are verified with abstract values, indicating the exactness of the proposed circuits.
This article is prepared as follows. A concise explanation of QCA structure is explored in Section 2. The proposed circuits and their QCA designs are organized in Section 3. Section 4 deals with simulation outcomes, comparisons and discussions. The energy dissipation and constancy of the proposed designs under thermal roughness are explained in Section 5. Finally, in Section 6 the conclusion with future work of this article is drawn.

Methods and materials
Quantum-dot cellular automata is a recent device outline that is suitable for the micrometer scale. This section, specific supportive background resources in appreciation the rest of this paper are presented.

QCA architecture
QCA is founded on the contact of bi-stable cells composed from four quantum dots. A top-stage outline of two polarized cells is displayed in Figure 1. All cells are composed from four quantum dots organized in a square outline (Tougaw & Lent, 1994;Tougaw et al., 1993). The cell is incited with two electrons, which are able to tunnel between neighboring quantum dots. The electrons be liable to engage antipodal positions accordingly of their reciprocal electrostatic revulsion. Hence, there remain two equally dynamically marginal compositions of the two electrons in the cell. These configurations are expressed as cell polarization P = −1 and P = +1 individually. Binary information can be encoded by applying polarization P = −1 to characterize logic "0" and P = +1 to characterize logic "1".
The binary data is transferred from one input position to output position in a wire due to the coulombic interfaces between QCA cells (Abdullah-Al- Shafi, Shifatul, & Bahar, 2015;Al-Shafi, 2016). This is an effect of the structure trying to resolve to a ground status. Whichever cells alongside the wire that is anti-polarized to the input site would be at an upper energy stage and would shortly resolve to the precise ground status. The conduction in a 90° wire is presented in Figure 2(a). Except the 90° wire, a 45° wire can also be applied as displayed in Figure 2(b). In this perspective, the conduction of the binary data rotates between the two polarizations. Besides, there is an ostensible non-linear wire, where cells with 90 o direction can be sited next to one another, except off center.
The majority voter acts a three pins logic function (Islam, Shafi, & Bahar, 2016). If the inputs are A, B and C then the function of the majority voter is, By arranging the polarization of one input as logic "0" or "1", an AND gate and OR gate can be realized correspondingly (Abdullah-Al- Shafi, 2016;. More complicated circuits can be assembled from AND gate and OR gate. Two forms of majority gate are shown in Figure  2(c) and (d), separately which are rotated and Original majority gate. Because of electrostatic revulsion among the electrons of the cells, the inner cells of both majority voters influence the outcome to the durable polarization. A five input majority voter consist of five inputs and one output cell. The inputs cell named A, B, C, D and E and the output cell is disclosed by output as presented in Figure  2(e). The input cells have static polarization however, output and central cells are allowed to alteration. Because of the effects among input and central cells, the majority result of inputs is moved to the output and forms the five input majority voter, proficiently.
QCA inverter is another construction part which has several outlines in QCA circuit design (Abdullah-Al- Shafi, 2016;Amlani et al., 2000;Lent et al., 1993). As per the coulomb revulsion, the smallest energy level for two transversely neighboring cells is when they hold reverse polarities. The inverter gate in Figure 2  For identification of the circuit effectiveness, specifically when the input move to the object statuses, the clocking signal procedure is utilized (Abdullah-Al- Shafi & Bahar, 2016a). As the entries of the majority voter that the values have to move at the uniform period into them. Usually QCA cells are separated to four time sections, in the signal clocking. Every sections, also named clock zone, supplements to one of the four segments: switch, hold, release and relax as showed in Figure 3. Interdot blocks are let down and transmission of data follows through electron channeling, throughout the switch level. The cells become polarized by steadily lifting the barriers. The barriers are sustained top in the hold level so the cell upholds the polarization and the outcome can be applied as inputs to the later segment. The cells begin to drop their polarization by declining the barriers throughout the release and relax levels and next they keep at in an unpolarized status. The power depletion of QCA is minimal as just two electrons are affecting. Maximum of the power needed by circuits will be consumed by the clocking mechanism (Vetteth et al., 2002).

QCA crossing over
Two special arrangements of crossover are existing in QCA circuit design. The coplanar and multilayer crossovers are presented in Figure 4(a) and (b) individually. As illustrated in Figure 4(a), two separate signals in a coplanar outline can individually be transferred, because of hardly communication between normal and rotated cells when the two are positioned next to each other. Meanwhile this layout has few complications like crosstalk, other approaches have to be applied for resolving such complications. In the multilayer approach the signal permits through the higher level which some extends profits like tolerance to cell movement deficits and decreased extent occupation, presented in Figure 4(b). The multilayer crossover is required three layers for implementation as per coulomb repulsion.

QCA comparator and full adder design
Comparator can be described as a combinational circuit which completes the assessment of two numbers and defines if one of them is identical to, bigger than, or less than another number. The procedure is comparable to deduct micro-operation, distant from that the variation is not transferred to a focus register; just the status bits are influenced. If the numbers are A and B, then the result is stated by A = B, A > B, or A < B as presented in Figure 5(a) and can be marked as follows. The mathematical table is presented in Table 1. (2)

(a) (b)
By joining the operational variety of Feynman and TR logic gate, the reversible comparator can simply be realized as presented in Figure 5(b). Single Feynman and TR circuit are needed to outline the 1-bit comparator. The outline constructs three succeeding outputs. The proposed comparator is design using regular cells and without wire crossing. It takes 117 cells and four clock levels to form precise results. In contrast to earlier outline the proposed comparator resulted in major changes in terms of cell and area complexity, and has a moderated quantum cost.
Binary accumulation is the very basic arithmetical process. Other computer mathematical strategies as multiplication and deduction are frequently performed by adders and the significance has encouraged different outlines for binary adder arrangements (Angizi et al., 2014;Bahar & Waheed, 2016;Cho & Swartzlander, 2009;Navi, Roohi, & Sayedsalehi, 2013;Rahimi Azghadi, Kavehei, & Navi, 2007;Roohi, Khademolhosseini, Sayedsalehi, & Navi, 2014;Sayedsalehi, Moaiyeri, & Navi, 2011;Wei Wang, Walus, & Jullien, 2003). The logical meanings of the adder can be stated as follows. The designed binary full adder is carry out in single layer and only 63 cells with four clock levels is used to produce accurate outputs shown in Figure 6. In contrast to previous model the designed adder developed in considerable progresses in terms of area and cell complexity, wire crossing, and has an identical organization in terms of clock delay. Simulation outcomes part compares all earlier outlines and displays the achievement of the proposed layouts.

Simulation and experimental results analysis
The simulation are attained employing a recent specific-resolution tool, QCADesigner (Walus, Dysart, Jullien, & Budiman, 2004) ver. 2.0.3. The list of features applied for bistable and coherence vector simulation is presented as follows where most of the features are stable in QCADesigner. The dimension of the quantum cell is 18x18 and diameter 5 nm, 0.0001 convergence tolerance, 65.00 nm radius force, 9.800e22 clock high-level, 3.800e23 clock low-level, 100 highest iterations per sample, 1.00e016 time phase, 7.00e011 complete simulation period, 2.00 amplitude factor and 11.50 layer division. Figure 7 presents the simulation results of comparator and full adder finalized in QCA and the outcomes are confirmed with abstract knowledge. For comparator if inputs A and B are both zero, then the output values for X, Z and Y are 0, 0, and 1, respectively. Similarly, for full adder if the input points are A = C = 0 and B = 1, then the outcomes are sum = 1 and carry = 0, correspondingly. The red arrow in output Y, Figure 7(a) define the initial point which is one clock level delay for output bits. In Figure 7(b), the red arrow denotes the initial point of output S and C.  Table 2 expresses the design complexity of the proposed comparator. The design is realized with eight majority voters, 117 cells with area of 0.18 μm 2 , and four clocking phases which is considerably better than earlier layout. The proposed comparator has cell improvement of 63.32% and area improvement of 47.52%.  max: 1.00e+000 B min: -1.00e+000 max: 1.00e+000 A min: -1.00e+000 max: 9.67e-001 X min: -9.66e-001 max: 9.54e-001 Z min: -9.54e-001 max: 9.50e-001 Y min: -9.50e-001 (a) max: 1.00e+000 A min: -1.00e+000 max: 1.00e+000 B min: -1.00e+000 max: 1.00e+000 C min: -1.00e+000 max: 9.88e-001 C min: -9.88e-001 max: 9.49e-001 S min: -9.49e-001 (b)

Quantum cost of the proposed comparator
The cost of the logic circuit can be achieved by total number of AND, NOT, and XOR operation. The proposed 1-bit comparator design as indicated in Figure 5(b) needed only one Feynman and one TR gate. Therefore, the comparator has circuit cost as (1 x 4 + 1 = 5) as presented in Table 3. The compatible quantum cost of the proposed comparator is evaluated in Table 2. The proposed 1-bit comparator has 44.45% improvement in terms of quantum cost compared to existing design. The design has 61.54 and 54.55% development in terms of quantum cost over present NEW gate and DG gate based comparator (Dehghan et al., 2014), correspondingly. Equally the proposed comparator has improvement over Toffoli, Peres and Fredkin gate based comparator (Basha & Kumar, 2012). The general estimation is presented in Table 3. Table 4 presents the layout complexity of the proposed single layer binary full adder. The design is achieved with single five-input majority voter, 63 cells with area of 0.05 μm 2 , and four phases of clock which is significantly worthier than earlier designs.

Comparison results among QCA full adders
An assessment between the proposed full adder and existing full adder outlines studied in this paper is achieved to analyze the formations of proposed QCA full adder. Table 5 synopses that proposed design has meaningful enhancements in terms of area and cell complexity with clock delay retained at the minimum level in contrast to the earlier designs. A relative analysis of proposed binary full adder with previous outlines is shown in Figure 8.
As per Figure 8, the proposed full adder directs to about 78.42% enhancement in cell and 91.94% enhancement in area complexity in contrast to the full adder outline generated with inverters and three-input majority voters in (Vetteth et al., 2002). In similar way, other improvements are shown in Figure 8.

Power consumption and consistency of proposed QCA layouts
The power depletes from a particular cell rest on the level of transform of the clock and the channeling energy (Abdullah-Al- Shafi & Bahar, 2016b). The depleted power of a QCA outline in a particular clock level can be analyzed by totaling the power depleted by every inverter and majority voter (Liu, Srivastava, Lu, O'Neill, & Swartzlander, 2012). Power depletion of a circuit can be measured by Hamming distance.
For an inverter if the input pin is altered from 0 → 0 to 1 → 1, then Hamming distance will be zero, and the dissipation by inverter at T = 2.0 K and γ = 0.25 E k is 0.8 meV while for γ = 1.0 E k , it will be 8.0 meV (Liu et al., 2012). For majority voter, dissipation is least, while the inputs are altered from 000 → 000 that is Hamming distance is zero, and the dissipation is top while polarization of all inputs are altered that is input polarization are altered from 000 → 111, Hamming distance is three. The  (Liu et al., 2012) is applied to result the dissipation of the proposed circuits at temperature T = 2.0 K in separate channeling energy. The power depleted by the proposed circuits are summarized in Table 6.
The temperature impact on the output polarization of proposed comparator and full adder are performed. The output polarization is captured at several temperature with QCADesigner engine. The average output polarization (AOP) for every cell is analyzed from (Pudi & Sridharan, 2011) and presented in Figure 9. The designs performs proficiently in temperature scale of 1-6 K, and the AOP for every cell is altered very slight in this scale.