A detection for patent infringement suit via nanotopology induced by graph

: The aim of this paper was to generate nanotopological structure on the power set of vertices of simple digraphs using new definition neighbourhood of vertices on out linked of digraphs. Based on the neighbourhood we define the approximations of the subgraphs of a graph. A new nanotopological graph reduction to symbolic circuit analysis is developed in this paper. By means of structural equivalence on nanotopology induced by graph we have framed an algorithm for detecting patent infringement suit.


Introduction
The theory of nanotopology proposed by Lellis Richard (2013a, 2013b), is an extension of set theory for the study of intelligent systems characterized by in sufficient and incomplete information. The purpose of the present work was to put a starting point for the nanotopological graph theory. Most real-life situations need some sort of approximation to fit mathematical models. The

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Lellis Thivagar introduced nanotopological space with respect to a subset X of an universe which is defined in terms of lower and upper approximations of X. The elements of a nanotopological space are called the nano-open sets. But certain nanoterms are satisfied simply to mean "very small". It originates from the Greek word "Nanos" which means "Dwarf" in its modern scientific sense, an order to magnititude-one billionth of something. Nanocar is an example. The topology recommended here is named so because of its size, since it has atmost five elements in it. The purpose of the present work was to put a starting point for the nanotopological graph theory. We hope these new results will further assist to comprehend the concept of nanotopological space in various applied fields.
beauty of using nanotopology in approximation is achieved via approximation for qualitative subgraphs without coding or using assumption. We believe that nanotopological graph structure will be an important base for modification of knowledge extraction of processing. In this section, we define graphical isomorphism (Diestel, 2010;Jensen & Shen, 2007) is a related task for deciding when two graphs with different specifications are structurally equivalent, that is whether they have the same pattern of connections. Nanohomeomorphism (Bonikowski, Bryniarski, & Wybraniec, 1998) between two nanotopological spaces are said to be topologically equivalent. Here, we are formalizing the structural equivalence of basic circuit of the chips from the graphs and their corresponding nanotopologies generated by them.

Preliminaries
This section represents a review of some fundamental notions related to nanotopology and graph theory.
(ii) The union of elements of any sub collection of R (X) is in R (X).

(iii) The intersection of the elements of any finite sub collection of
forms a topology on  the nanotopology on  with respect to X. We call ( , R (X)) as the nanotopological space. The elements of R (X) are called nano-open sets. Bonikowski et al., 1998;Diestel, 2010): A graph G is an ordered pair of disjoint sets (V, E), where V is nonempty and E is a subset of unordered pairs of V. The vertices and edges of a graph G are the elements of V = V(G) and E = E(G), respectively. We say that a graph G is finite (resp. infinite) if the set V(G) is finite (resp.finite). The degree of a vertex u ∈ V(G) is the number of edge in a graph contains a vertex u, then u is called an isolated point and so the degree of u is zero (Lellis Thivagar & Richard, 2013b). An edge which has the same vertex to ends is called a loop and the edge with distinct ends is called a link (Jensen & Shen, 2007).

Definition 2.3
( Bonikowski et al., 1998;Diestel, 2010): A graph is simple if it has no loops and no two of its links join the same pair of vertices. A graph which has no edge called a null graph. A graph which has no vertices is called a empty graph (Jensen & Shen, 2007;Lellis Thivagar & Richard, 2013b).
(iv) The outdegree of a vertex 'v' is the number of vertices 'u' such that ��� ⃗ vu ∈ E(G).
Throughout this paper the word graph means direct simple graph.

Approximations via neighbourhood
In this section, we will define lower and upper approximation of subgraph H of a graph G [V, E]. Some properties of these concepts are studied.
Definition 3.1 Let G(V, E) be a graph, v ∈ V(G). Then we define the neighbourhood of 'v' as follows, Then we define (i) The lower approximation operation as follows: L: (ii) The upper approximation operation as follows: U: Definition 3.3 Let G be a graph, N(v) be neighbourhood of v in V and H be a subgraph of G, as the nanotopological space induced by a graph.

Theorem 3.6 Let G[V, E] be a graph, H and K are two subgraphs of a graph G, then
In a similar manner we can also prove that Therefore .□

Formalizing structural equivalence
Here we are formalizing the structural equivalence for the graphs and their corresponding nanotopologies generated by them.
Remark 4.1 In this section we define graphical isomorphism is a related task for deciding when two graphs with different specifications are structurally equivalent, that is whether they have the same pattern of connections. Nanohomeomorphism between two nanotopological spaces are said to be topologically equivalent. Here we are formalizing the structural equivalence for the graphs and their corresponding nanotopologies generated by them.
Then there exists a function f :  f(V(H)). Since f is a bijection clearly, it follows that is 1-1 and onto.

Computer chip intellectual property rights
Based on the structural equivalence of graphs and the corresponding nanotopology induced by them, we have made an attempt to check whether the chip produced by a company have striking operational similarity produced by the another company.
Suppose that not long after Corporation  develops and markets a computer chip, it happens that the Corporation  markets a chip with striking operational similarities. If Corporation  could prove that Corporation 's circuit is merely a rearrangement of the Corporation  circuitry that is the circuitries are isomorphic], they might have the basis for a patent infringement suit.

Algorithm to detect patent infringement suit:
Step 1: Given the electrical circuit of the chips manufactured by two companies. An electrical network is an interconnection of electrical network elements such as resistances, capacitances, inductances, voltage and current sources, etc., We also assign reference direction by a directed edge results in the directed graph representing the network. Step 2: Convert the electrical circuits C 1 and C 2 into graphs G 1 and G 2 .
Step 3: Check whether G 1 and G 2 are isomorphic, and their corresponding nanotopologies induced from their vertices are homeomorphic.
Step 4: , N (f (V(H))] then the corresponding circuitries have striking operational similarities, and the company  can claim on the basis for a patent infringement suit.
Step 5: Otherwise, we can conclude that both the chip produced are entirely different.
Step 1: Consider the following basic circuit of the chip manufactured by two companies Corporation  and Corporation . Using the above algorithm we can prove whether these two circuits have functional similarities via nanotopology induced by the vertices of its subgraphs (Figure 4).
Step 2: The graphs are good pictorial representations of circuits and capture all their structural characteristics. Transform the basic circuit C 1 and C 2 of the chip produced by Corporation  and Corporation  into graphs G 1 = [V 1 , E 1 ] and G 2 = [V 2 , E 2 ], respectively ( Figure 5). Step 3: From the following graph we define a function f : V 1 → V 2 such that f(1) = b, f(2) = a, f(3) = c, f(4) = d and clearly f is an isomorphism. Since G 2 can be obtained by relabelling the vertices of G 1 , that is, f is a bijection between the vertices of G 1 and those of G 2 , such that the arcs joining each pair of vertices in G 1 agree in both number and direction with the arcs joining the corresponding pair of vertices in G 2 .
Then we also have to check : Since f is a bijection clearly, it follows that is 1-1 and onto.
] is a homeomorphism. This holds for every subgraph H of G 1 (Table 2).
Step 4: From the above process, we can conclude that the graph of the circuits and their corresponding nanotopologies generated by the vertices of the subgraphs are homeomorphic.
Step 5: Thus we can characterize that the chips manufactured by Corporation  is just a rearrangement of Corporation  and also they have striking operational similarities and Corporation  can also claim for his patent infringement suit.
Observation: Using the above structural equivalence technique we can check whether two circuits are equivalent and we can also extend our theory in many industrial products for patent infringement suit.