Design and Evaluation of Binary-Tree Based Scalable 2D and 3D Network-on-Chip Architecture

Abstract Network-on-Chip (NoC) has been developed as a most prevailing innovation in the paradigm of communication-centric technology. It solves the limitations of bus-based systems, with the incorporation of 3D IC technology, and it reduces packaging density and improves performance of Multiprocessor System-on-Chip. There is need of suitable NoC topology for these applications and desired performances. This paper proposes a scalable binary tree-based topology for 2D and 3D NoCs. The average degree of the proposed network is reduced around 40% of the torus whereas the diameter also reduced significantly, as compared to other topologies.


Introduction
Advancements in the semiconductor technology have increased the integration of many heterogeneous components on single chip with Multiprocessor Systemon-Chip (MPSoC). On the single chip, many features are demanded such as high performance and high

Related Works
Most of the NoC uses the mesh-based topology for implementation as it has regular and simple structure but the drawback in mesh topology is that it requires more resources, like, more links required for larger size network which results in needless area and energy overhead [7].
A cross-by-pass-mesh (CBP-Mesh) topology has been proposed which reduces the diameter and average hop counts [8]. It has high scalability and is based on mesh topology architecture. The extra bypass links provide small route to destination from the source, and this results in improvement in the performance of the NoC, but at little complexity and cost of power and energy requirement.
With the emergence of 3D IC technology, 3D NoC is a compelling option for chip interconnection. As 3D Recursive Network Topology (3D RNT) was given in [9], it has partial vertical links by using TSVs and also proposed the routing algorithm for the topology. But the issue of heat dissipation is still an issue with it.
In [10], an optimization technique, the ant colony optimization (ACO) was applied to 3D networks having torus, mesh, and hypercube topologies for routing protocols. The 3D Ant Colony Routing (3D-ACR) and the another optimization technique used in [11] is based on Hopfield Neural Network (HNN) for 2D mesh topology, and they have some shortcomings like the scalability of the algorithm and chip area overhead problem for implementation.
In [12], exhausted survey of 3D NoCs is given. The transistor scalability issues can be solved by using the 3D NoC which is well suited for heterogeneous multiprocessor SoC.
From the various current papers and articles, we can say that there is still more focus on designing a 2D and 3D NoCs' architecture which can give better scalability and performance improvement and to overcome the issues of area overhead, energy, or power consumption and to reduce the number of links.
The proposed topology is the combination of binary tree and ring topology for 2D and 3D NoCs' architecture, that drastically removes the number of links. The less links means reduction in chip resources which saves area and energy consumption. The average degree of the proposed network is reduced around 40% of the torus which reduces the router cost and complexity. The diameter also reduced significantly, as compared to other topologies which give shorter routing paths and the advantage for the latency of the routing, and the scaling of the network improves as the diameter of the topology directly linked with it.

Proposed Topology
A binary tree is a well-established structure in which each node has two child nodes named as left child node concepts, which reduces the cost of communication and time-to-market.
3D NoC has the advantage of 3D integrated chip (IC) and combines it with NoC. This gives an option to connect many heterogeneous chips vertically with the small vertical links. For vertical connection on different chip layers, Through-Silicon-Vias (TSVs) are mostly used, as it consumes less power and have low delay and high bandwidth.
The physical structure of NoC is decided by its topology. Regular and fixed topologies like mesh, torus, ring, etc. are commonly used in NoC. Mesh is mostly used because of its simple and regular structure, but it has many limitations, for example, for a larger network, the links' requirement is more, which requires extra area and power of the chip. By reducing the links, there is an advantage of both the area and power in NoC. Several topologies have already been proposed topologies such as torus and mesh [1] are mostly used. Torus topology overcomes the large diameter of the mesh topology. The 3D torus topology has been shown in Figure 1, it has long wrap-around links and complex that can be seen from the figure. Quadrant-based routing designed for 3D torus in [2], it used few TSVs in place of all vertical connection.
It suffers from long wrap-around links causing more delay, which was reduced by using folded torus topology. Hierarchical binary tree [3] have small bisection width through better management. Fat tree overcome small bisection bandwidth of binary tree but the problem of high-degree node comes [4]. Mesh of tree is the hybrid of mesh and tree architecture [5]. Binary search tree-based ring topology was proposed and that had drastic reduction in degree and meter of network [5]. The proposed topology is the combination of binary search tree and ring topology which drastically removes the number of links used in [6]; thus, the proposed topology has the advantage of both area and power saving on chip along with reduction in degree.
The remaining part of this paper is organized as follows: Section 2 presents the related works, Section 3 presents the proposed topology and its characteristics, in Section 4, discussion, comparison, and analysis are presented, and in final section, conclusions are presented. and right child node originated from a core node. Binary search tree-based ring topology was proposed in [13]. The basic module of it consists of tree nodes that can communicate directly with each other as shown in Figure 2. Although this topology drastically reduces in the diameter and degree of the node, it has higher number of links. As the number of nodes increases, more levels of BST-ring topology are needed, which gives rise to redundant links, and that adds to unnecessary area and power consumption of the NoC architecture. In this work, a combination of BST and BST-ring topology is proposed which gives the significant improvement in the node degree with the less number of communication links. The proposed topology is shown in Figure 2.
For level L = 1, Nodes total degree:  The degree of the proposed topologies is compared with torus topology and ring-based tree topology as shown in Figure 5. It has found to be better than them, and value of degree of the proposed topology is around 40% less than the torus topology. The possible distribution of the cores and nodes are shown in Figure 3 and Figure 6. It shows the layout of the proposed topology.
We can have a generalized expression as follows for level L = n as: where k ≥ 0, m = 1 and N = n − 1, when L = n is even and m = 2 and N = n − 1, when L = n is odd.
From the above Equations (2) and (4), we can find the average degree (d a ) of the network as:

Discussion and Analysis
The performance and scaling property of the networkon-chip can be analyzed by theoretical and mathematical modeling of the network. Analysis of proposed network parameters is given in Table 1. In scaling property, the performance is highly dependent on the diameter of the network. Diameter (D N ) measures the number of maximum nodes traveled from source node to destination node. Graphical analysis shown in Figure 4 represents comparison of the diameter (D) of proposed topology and exiting topologies such as mesh and WK-recursive [14]. From the Figure 4, it can be seen that the proposed topology has the lowest diameter among other topologies. At level 5, number of nodes are 93, the mesh has diameter 17.28 whereas proposed topology has diameter 9. (4)

Conclusion
Topology is the basic building block for designing the NoC; it decides the roadmap for traversal of the packets. Performance, complexity, and scalability mainly depend on the topology of the network. Various metrics of the proposed topology are explored and compared with the other existing most common topologies. It is found that diameter of the proposed topology is considerably small compared to other topologies such as mesh and WK-recursive. The degree of proposed topology is significantly lower than the other existing topology. This results in lower number of links required that not only save the area overhead but also reduce the complexity and cost of router.
With the extension of the topology for 3D NoC, the number of TSVs required is reduced which is important while designing 3D ICs. As extension to present work in future, it is planned to design routing algorithm that can deal with the faults and congestion and to calculate the power consumption.

Disclosure statement
No potential conflict of interest was reported by the authors.