Oxide thin-film transistors based on i-line stepper process for high PPI displays

Indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with a 1 um channel length were successfully fabricated by i-line lithography with a stepper process, resulting in high throughput. The a-IGZO TFT with a channel length of 1 μm exhibits high mobility of 8.77 cm2/Vs with an on/off current ratio of >3 × 1010. The stepper lithography process is capable of defect-free patterning given its precise layer-to-layer alignment and high image resolutions of the types required for large-area high-PPI displays. Consequently, IGZO TFTs can be fabricated on an 8-inch wafer with only minor electrical property deviations in the turn-on voltage, mobility, and on/off ratio. These results indicate that i-line lithography with a stepper process is a promising process for use in cutting-edge large-area electronics industries.


Introduction
Amorphous silicon (a-Si) has been the dominant active material for thin film transistors (TFTs) in the display industry over the past few decades. However, electrical properties of a-Si are not suitable for state-ofthe-art, high-resolution displays. Oxide semiconductors, especially amorphous In-Ga-Zn-O (a-IGZO), have attracted considerable attention since Nomura et al. initially reported their properties in 2004 [1]. Oxide semiconductors show higher mobility and lower leakage current compared to a-Si as well as good large-area uniformity, since this type of semiconductor has an amorphous structure and can be fabricated in ways compatible with existing conventional semiconductor fabrication processes [2,3]. Based on these advantages, a-IGZO has been successfully commercialized as the active material used in the TFT backplanes of liquid crystal display (LCD) or organic light-emitting diode (OLED) panels [4,5].
Beyond high-definition, high-frame-rate flat-panel displays, augmented reality (AR) and virtual reality (VR) devices, which break down the walls between what is virtual and what is real, are emerging as next-generation displays. Both VR and AR deliver immersive experiences with real-time interaction across multiple disciplines, such as education, healthcare, engineering, and gaming, among others. Because the displays of VR and AR devices are close to what the human eye sees, smaller pixels are needed. The resolution of the human eye increases as the distance between the object and the viewer becomes smaller. This can be expressed as follows;

Resolution of Human Eyes
where L is the distance between the human eye and the display and 1 is the minute of the arc, referring to the visual acuity of the human eye. If the pixel density is not dense enough, a dizziness-inducing screen-door effect will occur, preventing prolonged use. Generally, for VR/AR devices, a resolution of more than 1000 pixels per inch (PPI) is needed to prevent the screen-door effect. Therefore, reducing the pixel size is one of the main challenges of AR/VR technologies [6]. Lithography has been widely utilized in the microfabrication of various thin-film patterns. It can be classified according to the light source used, since it determines important characteristics such as the resolution. Although e-beam and x-ray types of lithography can create small patterns, problems arise when attempting to resolve issues such as damage to the underlying layer, high cost, low throughput, and other issues [7]. An ultraviolet (UV) light source is the least expensive source, and the lithography process using UV has matured. In optical lithography, the resolution of the pattern is strongly related to the wavelength of the light source. There are several wavelengths normally used for photolithography, such as the g-line (436 nm), h-line (405 nm), and i-line (365 nm) wavelengths [8,9]. Generally, most lithography patterning focuses on Si semiconductor devices. To fabricate a high-PPI display, the oxide TFTs used should be small and can be fabricated by photolithography using a light source with a short wavelength. Most of the reported studies on sub-micron channel length TFTs fabricated using oxide semiconductors use processes that are difficult to mass-produce, including laser and nanoimprint lithography [10][11][12]. On the other hand, the stepper process with built-in reduction capabilities can form feature sizes smaller than 1 μm with an i-line UV source. This method easily integrates the projection lens, which can significantly increase the resolution without forming pattern-induced defects [13]. Consequently, possible resolutions can be improved compared to when the aligner process is used.
In this work, good electrical properties and stability of a-IGZO TFTs as a function of the channel length are demonstrated using a-IGZO TFTs with various channel lengths in the range of 1 ∼ 10 μm fabricated by i-line lithography patterning. The effects of downscaling on the TFTs were investigated by comparing the turn-on voltage, subthreshold swing, on/off current, and mobility. Finally, positive bias stress (PBS) and negative bias stress (NBS) tests were conducted to a-IGZO TFTs to confirm the short-channel effect on stability.

Experimental details
To fabricate the short-channel IGZO devices, a Si wafer with wet-thermally-grown 300-nm-thick SiOx was used as a substrate. Aluminum (Al) was deposited as the gate electrode using a sputtering system. A 300-nm-thick SiO 2 film was subsequently formed by plasma-enhanced chemical vapor deposition (PECVD) as the gate dielectric. This was followed by depositing 30-nm-thick IGZO active layers via sputtering at room temperature using an IGZO target (In:Ga:Zn = 1:1:1 at%). The working pressure was fixed at 2 m Torr, with Ar and O 2 gas flow rates at 50 and 5 sccm, respectively. Finally, a 150-nm-thick source and drain Al electrode were deposited by sputtering. Thermal annealing was conducted at 300°C for one hour in ambient air after completion of all deposition processes.
The channel width (W) was fixed at 50 μm and the length (L) was varied from 10 to 1 μm. In order to form small-sized patterns up to a width of 1 μm, an i-line UV source (365 nm) with a stepper process was utilized for photolithography processes. A dry etch process was used to form the gate electrode and gate oxide pattern. When patterning the active layer and the source/drain electrode, a liftoff process was applied to prevent damage to the underlying layer.
The transfer characteristics and stability of the TFTs under negative and positive bias stress were measured using a Keithley 4200A-SCS parameter analyzer in the dark and at room temperature. TFTs were measured under a vacuum to avoid the back-channel effect. The field-effect mobility values were extracted using the maximum transconductance (g m ) at a drain voltage (V DS ) of 0.1 V with the following equation [14] where L is the channel length, W is the channel width, g m is the maximum transconductance, C ox is the capacitance of the oxide, and V DS is the drain voltage. The turn-on voltage (V on ) was considered as the voltage at which I DS = 1 nA.  Figure 1(d) presents an illustration of the lithography technique with the stepper process. Unlike e-beam lithography, which uses a scan-type exposure, the stepper-type exposure is a high-throughput process that is suitable for use in large-scale industries [15,16]. Figure 2(a,b) shows the typical transfer characteristics of a-IGZO TFTs with an identical channel width of 50 μm and various channel lengths of 1, 3, 5, and 10 μm. The extracted transfer properties, collected from 20 different devices from different spots on the 8-inch wafer, are summarized in Table 1. For all channel lengths, the a-IGZO TFTs show excellent large-area uniformity with small electrical property deviations. The a-IGZO TFT with 1 μm channel length shows mobility of 8.77 cm 2 /Vs, a subthreshold swing of 0.47 V/dec, a V on of −0.49 V, and an on/off ratio exceeding 3 × 10 10 . There is no major deterioration of the electrical properties when the channel length is reduced. These electrical properties are also comparable to previously reported short channel IGZO TFTs with conventional lithography process, which means that the i-line stepper is a practical process of choice to fabricate IGZO TFTs [17][18][19]. Moreover, the 1 μm a-IGZO TFT shows a small drain-induced  barrier-lowing (DIBL) effect without any significant change in V on when V DS increases from 0.1 to 5.1 V. It has been reported that DIBL can occur due to an oxygen deficiency in the channel layer adjacent to the source/drain contacts [20,21]. By optimizing the oxygen flow (5 sccm) rate during the IGZO deposition process, the short-channel effects can be suppressed. Figure 2(c) shows the output curves of a-IGZO TFT with 1 μm channel length. The a-IGZO TFTs fabricated using the i-line stepper process show the output curves with Ohmic-like contact and without current crowding even at a short channel of 1 μm.

Results and discussions
To confirm the short-channel effects, the contact resistance (R S/D ) of the fabricated a-IGZO TFT devices was estimated using the transmission line method (TLM) and a series of TFTs with different channel lengths [22,23]. The contact resistance is calculated using the following equation:  where R Tot is the total TFT resistance, r ch is the channel resistance, and R S/D is the series resistance at the S/D contact. These values are normalized by the channel width while the extracted value of R Tot is plotted as a function of various channel lengths for different V GS .
R S/D is obtained from the y-axis intercept of the linear fit to R Tot . R Tot decreases with an increase in V GS due to the increased carrier density in the channel and near the interface, indicating that the TFTs are operating, as shown in Figure 3(a). Figure 3(b) and the inserted figure show the extracted contact resistance and the reduced channel length ( L) [24]. R S/D is reduced to 4.71 cm when V GS equals 30 V, which is lower compared to previously reported values [25]. Stepper lithography does not cause a defect during the patterning process, so an excellent interface and low contact resistance can be achieved [26,27]. In addition, the extracted value of L is very small (0.22 μm), allowing for stable characteristics even in 1 μm devices. These results indicate that an a-IGZO TFT at 1 μm fabricated using the i-line stepper lithography process can be a promising technology for future high-PPI display industries.
To demonstrate electrical stability, positive bias stress (PBS) and negative bias stress (NBS) tests were performed on IGZO TFTs with various channel lengths. In the NBS case, the applied gate voltage (V G ) and drain voltage (V DS ) were −10 and 0.1 V, respectively. For PBS, the applied V G and V DS were 10 and 0.1 V, respectively. All stress tests were conducted in a vacuum at room temperature for 1 h. Figure 4(a,b) shows the transfer characteristics of IGZO TFTs with 1 μm channel length. The inset of Figure 4(a,b) shows the V on shift of the PBS and NBS stress results for a-IGZO TFTs with various channel lengths as a function of time. All a-IGZO TFTs including 1μm channel length show V on shift within ±3 V throughout the PBS and NBS tests. Here, the a-IGZO TFT with the shortest channel length (1 μm) shows similar V on shift value in PBS compared to that with the longest channel length (10 μm), and this is likely due to the minimized shortchannel effect, as confirmed in Figure 3. However, relatively large V on shifts were observed in the NBS test.
Research is underway to expound on the origin of this phenomenon.

Conclusions
In this work, a-IGZO TFTs with short-channel lengths were successfully fabricated using i-line photolithography with a stepper process. An a-IGZO TFT with a 1 μm channel length displays the following electrical properties: field-effect mobility of 8.77 cm 2 /Vs, SS of 0.47 V/dec, V on of −0.49 V, and an on/off ratio exceeding 3 × 10 10 . These results indicate that i-line lithography with a stepper process shows significant potential as a fabrication technology for next-generation high-PPI displays. chemical and gas sensors, analysis of electronic structure, and