Brain-inspired computing via memory device physics

–In our brain, information is exchanged among neurons in the form of spikes where both the space (which neuron fires) and time (when the neuron fires) contain relevant information. Every neuron is connected to other neurons by synapses, which are continuously created, updated and stimulated to enable information processing and learning. Realizing the brain-like neuron/synapse network in silicon would enable artificial autonomous agents capable of learning, adaptation and interaction with the environment. Toward this aim the conventional microelectronic technology, which is based on complementary metal-oxide semiconductor (CMOS) transistors and the von Neumann computing architecture, does not provide the desired energy efficiency and scaling potential. A generation of emerging memory devices, including resistive switching random access memory (RRAM) also known as the memristor, can offer a wealth of physics-enabled processing capability, including multiplication, integration, potentiation, depression and time-decaying stimulation, which are suitable to recreate some of the fundamental phenomena of the human brain in silico. This work provides an overview about the status and the most recent updates on brain-inspired neuromorphic computing devices. After introducing the RRAM device technologies, we discuss the main computing functionalities of the human brain, including neuron integration&fire, dendritic filtering, short- and long-term synaptic plasticity. For each of these processing function we discuss their proposed implementation in terms of materials, device structure and brain-like characteristics. The rich device physics, the nano-scale integration, the tolerance to stochastic variations and the ability to process information in-situ make the emerging memory devices a promising technology for future brain-like hardware intelligence.

post-synaptic current (EPSC) across a synapse. This is different from the conventional artificial neural networks (ANNs) used in artificial intelligence (AI) accelerators for computer vision and speech recognition, where the information is synchronous and based on the amplitude of the signal, instead of its time. 4 Most SNNs generally relies on the complementary metal-oxide-semiconductor (CMOS) technology, with two main significant advantages: First, the CMOS technology is widely available in the semiconductor industry ecosystem, including design, fabrication, and qualification, therefore creating the conditions to make CMOS-based neuromorphic engineering a mature topic. Second, the CMOS transistor can scale down according to the Moore's law, where a reduction of the lithography feature size allows for a larger density and a better performance of the circuit. On the other hand, there are significant limitations in CMOS technology. For instance, timedependent functions such as spike integration in an artificial neuron generally requires large capacitors in CMOS technology, therefore limiting the cost effectiveness of neuromorphic circuits. 5 Synaptic weights are generally stored in static random access memory (SRAM), which are volatile, i.e., all synaptic values are lost when the circuit is switched off. 6 In addition, SRAM devices are large and binary, i.e., they can only store 0 and 1, thus they are not suitable for gradual potentiation and depression which are typical of synaptic plasticity phenomena. [7][8][9] To overcome these limitations, neuromorphic materials and devices are intensively explored to complement CMOS technology. The aim of this new wave of research is to reproduce bioneurological phenomena typical of the human brain with device physics. For instance, phase change materials have been shown to accumulate applied voltage spikes and consequently change their resistivity, which can be used as the physical mechanism for integrate-and-fire (I&F) neurons without capacitors. [10][11][12] The fire process of the typical I&F neuron can be reproduced in a nanoelectronics device by abrupt current switching at the onset of the negative differential resistance (NDR) region, such as the electronic threshold switching in ovonic threshold switch (OTS) elements 13 or ferroelectric transition in HfO2. 14 Similarly, all other key mechanisms in the biological neural network can be emulated by specifically-engineered devices through their physics. The objective is the recreation of a brain-like circuit system with extremely low power consumption and compact, scalable architecture.
This work provides an overview about the status on the development of neuromorphic devices that emulate biological neural processes by device physics. The work will focus on the resistive switching random access memory (RRAM) as the device technology for the implementation of various neuromorphic functions, including artificial synapse, neuron and dendrite. Circuits demonstrating the full neuromorphic function, such as unsupervised learning and pattern recognition, will also be presented. The rest of the paper is organized as follows: Sec. 2 will illustrate the major categories of RRAM devices in terms of switching mechanism and device structure. Sec. 3 will provide an overview of the neuromorphic processes and their implementation in RRAM devices. Sec. 4 will deal with artificial neurons with integration, fire, oscillations and dendritic filtering capability. Finally, Sec. 5 will focus on artificial synapses including learning functions via plasticity and sensing/computation via short-term memory. modification of the active material, thus serving as scalable nonvolatile memories for standalone and embedded memories. [23][24][25] Among the novel emerging memory technologies, RRAM has attracted strong research interest partly due to the simple structure that allows for a relatively straightforward fabrication in academic labs and integration within industrial CMOS process. RRAM has been recognized as a potential technology for synaptic connections in ANNs and SNNs, thanks to the small size, easy integration and scalability that allows for high connectivity within the neural network. 26 The high synaptic density is further supported by the ability of 3D integration by array stacking 27 of vertical structures. [28][29][30][31][32] The programming energy of RRAM is generally low thus enabling energy-efficient computation and reconfiguration of the neural network. 31 Fig. 1 shows a schematic illustration of 2-terminal RRAM device, including a filamentary switching RRAM (a) and a uniform switching RRAM (b). While both devices are based on a metal-insulatormetal (MIM) structure with a top electrode (TE), a bottom electrode (BE) and at least one dielectric layer, the switching mechanisms is fundamentally different. In the filamentary structure, a forming process is first applied, by applying a relatively large voltage that leads to soft breakdown of the MIM. 22 The breakdown spot, consisting of a filamentary path with low resistivity, is then subjected to set/reset processes by the application of voltage pulses. Typically, the RRAM device shows a bipolar switching characteristic, where the applied electric field across the conductive filament causes ionic migration and a consequent change of resistance. 33 For instance, a negative voltage applied to the TE leads to the migration of positively-ionized defects toward the TE, thus resulting in depletion of defects at the BE side with an increase of resistance, or reset transition. 34 A positive voltage applied to the TE results in migration of the defects toward the BE, thus refilling the depleted gap and causing a decrease of resistance, or set transition. 34 Filamentary set transition is generally abrupt due to the positive feedback in the gap filling process: As the defects start migrate toward the gap, the electric field increases, thus causing an acceleration of the ionic migration. To avoid uncontrolled filament growth during the abrupt set transition, usually a transistor is added in series with the RRAM device to enable current limitation below a certain compliance current IC. 35 Fig. 2a shows typical I-V characteristics for a HfO2 RRAM device with 1T1R structure. 36 As IC increases, the device conductance in the low resistance state (LRS) increases thus indicating a larger size of the conductive filament. The reset current correspondingly increases, as a result of the larger filament size. The adoption of the onetransistor/one-resistor (1T1R) structure of the RRAM device thus allows for low current operation and tight control of the device conductance, which is beneficial for analogue in-memory computing. 36  This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset.

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resistance state (HRS). (b) Uniform switching RRAM, where the device resistance is controlled by a switching layer, usually a metal oxide, which shows a high resistance, due to a low concentration of defects, in the HRS, or a low resistance, due to high concentration of defects, in the LRS.  Depending on the electrode materials, the conductive filament can be stable for long time even at high temperature, 37 or be metastable due to defect diffusion after the set transition. [38][39][40][41][42][43][44] In particular, RRAM with Ag TE generally tend to display this type of volatile behavior due to the spontaneous diffusion of Ag from the filament location. This was attributed to surface diffusion of Ag to minimize the total energy of the filament by minimizing the surface to volume ratio. 45 Fig. 2b shows the typical pulsed programming characteristics for Ag/SiO2 RRAM device. 44 Under a triangular pulsed of applied voltage, the device shows a set transition, marked by the abrupt rise of current to the IC level. After the pulse, the read current remains active for a finite retention time tR of about 1.5 ms, thus revealing the spontaneous decay of the conductive filament diameter f (see simulation results at the bottom of Fig. 2b). 44 Such a volatile behavior has been proposed for selector elements in crosspoint device, 46 thanks to the steep switching slope and extremely large on/off ratio exceeding 10 orders of magnitude. 42 However, due to the relatively long retention time in the range between 1 µs and several ms, the device is most suitable as a physics-based neuromorphic device to implement transient biological phenomena, such as short-term memory 47 and spike-timing dependent plasticity. 41 The filamentary set/reset process causes intrinsic variability issues due to individual defect diffusion and instability. [48][49][50][51] Variations include cycle-to-cycle changes of conductance, due to the variability in filament shape and volume, 48 and device-to-device variations due to the difference in structure and geometry among various RRAM devices. 49 Generally, device-to-device variation plays the key role in technology reliability, due to the sensitivity to local defect concentration, dielectric film microstructure, interface roughness and filament shape originating from the breakdown event at forming. 50 In addition to programming variations, read variation causes the device resistance to vary even after the device has undergone the set/reset process. The resistance can in fact display time-dependent fluctuations such as random telegraph noise (RTN) and random walk due to defect instability. 51 The conductance variations can cause a degradation This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset.

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of neural network accuracy, 52,53 although some stochastic computing algorithms may take advantage from noise. [54][55][56][57][58][59] Note that variations are not intrinsic to filamentary switching, rather they arise generally in most types of memory technologies. For instance, PCM displays programming variations due to the stochastic nature of nucleation and growth in the crystallization process. 60 Similarly, FERAM shows variations in the multilevel conductance due to the stochastic switching of individual ferroelectric domains. 61 However, filamentary RRAM is more critically affected by post-programming fluctuations of the resistance, as a result of the localized conduction at atomically-thin channels, where trapping, detrapping and atomic relaxation can induce a strong variation in the device resistance. 62 To mitigate the cycle-to-cycle variations, a new concept of filamentary switching RRAM was developed, where the conductive path originates from threading dislocations within epitaxially-grown SiGe layers on Si substrates. 63 The materials-based approach to induce switching at predetermined channels is extremely promising for reducing the programming variations, although post-programming variations at the dislocation filament may still be a concern for reliability. The conductance variations and their impact on the neural network accuracy can be mitigated by the uniform switching RRAM in Fig. 1b. The conductance in this device changes as a result of oxygen vacancy exchange at the interface between two oxide layers, the dielectric layer and the switching layer. 64 For instance, the switching layer can consist of an interfacial oxide layer between an active electrode, e.g., Sm, and a relatively-high conductive oxide layer, such as La0.7Ca0.3MnO3 (LCMO). 65 Fig. 3 shows a possible implementation of a uniform switching device with vertical structure. 30 The device stack includes a Ta TE, TaOx, TiO2 and Ti BE. The bipolar switching takes place by the oxygen exchange between the TaOx and TiO2 layers. Fig. 3c shows the I-V curves of the uniform switching device, indicating a smooth and gradual change of resistance. 30 Thanks to the gradual set/reset dynamics, the uniform switching is suitable to perform pulsed potentiation/depression for analogue artificial synapses. 30,66 Also, the low conductance around 100 nS in uniform switching allows for an extremely low energy per spike below 10 fA. 31

3-terminal devices
The need for analogue conductance, low variation and low energy in neuromorphic circuits has stimulated the study of advanced 3-terminal devices based on ionic migration. Fig. 4a shows a 3terminal device called electro-chemical random access memory (ECRAM). 67 The ECRAM displays a transistor structure with gate, source and drain contacts, where the read path is from source to drain, while the programming takes place by gate pulses. Application of positive/negative gate pulses results in the migration of ionized defects from a reservoir, close to the gate terminal, to the channel between source and drain. Defects can be either Li + impurities, 68-70 H + 71, 72 or oxygen ions/vacancies. 73,74 Li + intercalation and oxygen exchange within the channel can change its conductivity, thus resulting in weight potentiation or depression. ECRAM devices, also referred to as redox transistors or ionic transistors, are characterized by extremely low conductance in the range from few nS 69 to few µS, 73 thanks to the low mobility and low carrier concentration in the channel material, e.g., WO3. Such a low conductance is essential to minimize the signal current within the synaptic array, thus enabling low parasitic IR drop 67 and small size of the circuit periphery to handle the output current, including select transistors and integrating capacitances. Most importantly, the potentiation and depression characteristics are extremely gradual and linear, thanks to the bulk conduction mechanism in the device 74 and for accurate integration in I&F neurons. On the other hand, the ECRAM technology usually requires selector devices to properly execute program and read operations. 72 Fig. 4b shows the mem-transistor device, where the channel consists of a 2D semiconductor region with atomic thickness. 75,76 The drain current of the device can be modulated by applying a suitable gate voltage, thanks to the semiconductor properties of transition metal dichalcogenides (TMDs) such as MoS2. 77 In addition, the application of a large drain bias can lead to a persistent modification of the channel conductivity due to migration of defects such as grain boundaries 75,76 or Li + impurities. 78 The mem-transistor thus allows in principle both transistor effect (by gate stimulation) and memory effect (by drain stimulation), which can support various neuromorphic functions, such as synaptic potentiation/depression and spike dependent plasticity. 75

Neuromorphic processes by device physics
Memory devices allow to embody neurobiological processes within a single device with extremely compact size and highly bio-realistic properties. This is made possible by the rich physics of the emerging memory devices, where electric/magnetic polarization, phase structure and local chemical composition contribute to the electrical conductance, which is in turn affected by This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset.

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atomic/ionic drift/diffusion, electro-chemical redox reactions, phase transitions, dielectric breakdown phenomena, and ferroelectric/ferromagnetic transitions. Fig. 5 shows a summary of neurobiological features and functions and their respective implementation in resistive memory devices. Generally, neurons in the biological neural network of the human brain consists of soma, dendrites and an axon. The temporal spikes containing the incoming information are collected by dendrites and processed by the soma. Depending on the incoming stimulation and the type of information processing, e.g., I&F with a characteristic threshold, the neuron can fire, i.e., send an output spike through the axon toward the receiving neurons. The spike transmission from a neuron axon to other neuron dendrites takes place via a synapse, called axo-dendritic synapse, each having a specific weight and a corresponding weight update behavior. The synaptic weight describes the efficacy of an input spike to stimulate the receiving neuron. Synapses display synaptic plasticity, namely the ability to change their weight in response to the stimulation. Although the synaptic plasticity mechanism is not yet fully understood, several plasticity rules have been proposed, including spike-timing dependent plasticity (STDP) 7, 9, 79-81 and triplet-based plasticity, 8,82,83 where the timing of spikes, e.g., their respective delay or relative frequency, dictates the potentiation or depression of the synapse. Synaptic plasticity controls learning within the human brain, thus it is of utmost importance in all neuromorphic circuits. To implement the individual elements of Fig. 5, several devices, circuits and their respective physics can be adopted. The summation and integration functions of the soma can be implemented in hardware by matrix vector multiplication (MVM) in crosspoint arrays and integration in nanoscale memory devices. Time-dependent dendrite filtering and synaptic plasticity effects can be described by the switching properties of RRAM devices. The rich physics of memory devices and their combination can thus be used to reproduce neuro-biological phenomena at the nanoscale, which benefits the massive connectivity, high scalability and lowcost of neuromorphic circuits. This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset.

Hardware neurons
The neuron soma can be described by the popular McCulloch-Pitts model, 84 where the neuron input is given by the weighted summation of the incoming spike, while the output signal is given by a suitable nonlinear activation function. This can be expressed by the formula: where yi is the output of post-synaptic neuron i, f is the activation function, wij are the weights of the synapses connecting presynaptic neurons j with postsynaptic neuron i, and xj is the signal of pre-synaptic neuron j. While other models, such as the Hodgkin-Huxley (HH) model, 85 are more accurate in the description of the temporal shape of the spike and the bio-chemical details of Ca and K ion transport, the McCulloch-Pitts model provides a simple mathematical description to elaborate the interaction between presynaptic and postsynaptic neurons. The weighted summation of the McCulloch-Pitts model can be well described in hardware by the matrix-vector multiplication (MVM) in a crosspoint memory array, which is depicted in Fig. 6. In the crosspoint array, each resistive memory device is preprogrammed with conductance Gij. The application of a voltage vector Vj at the array columns thus results in the generation of currents GijVj at the memory element with coordinates (i,j) via Ohm's law. All these currents are then collected at the array rows by Kirchhoff's law, thus yielding a total row current Ii given by: which is line with the argument of the activation function in Eq. (1). The output current is then typically converted into voltage by transimpedance amplifiers and passed through an activation function to fully emulate the neuronal information processing. The significant advantage of the crosspoint array circuit is that it allows to accelerate MVM by simultaneous multiplication and summation by physical laws, in contrast with the iterative multiply-accumulate (MAC) algorithm for MVM execution in digital processing units. [86][87][88] Another strong advantage is the ability to process information within the memory, thus eliminating any data transfer between the memory and the separate processing unit which would be affected by the memory bottleneck of von Neumann architectures. 89,90 On the other hand, in-memory MVM is executed in the analogue domain, which raises a number of concerns such as electronic noise, limited precision of the conductance values Gij, non-linear memory characteristics and parasitic IR drop along the This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset.

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row/column lines in the array circuit. 67 Nonetheless, MVM has been demonstrated in several applications, such as neural network acceleration, 49, 91-94 sparse coding, 95 mixed-precision computing, 96 compressed sensing, 97 solution of differential equations 98 and the solution of linear matrix problems such as matrix inversion 99 and linear regression. 100

Neuron integration
Biological neurons are also known to have a memory effect, where input spikes are integrated, instead of being summed simultaneously. The incoming signals from synapses cause the increase of a local graded potential (LGP) in the dendritic membrane. The neuron then generates an action potential if the LGP reaches a threshold, otherwise relaxes to its resting state if the LGP is below the threshold. The neuron can thus conduct the signal-processing functions by information integration and the threshold firing. 101 This functionality of the biological neuron is expressed by the concept of I&F neuron, where spike integration causes the increase of an internal state variable, generally named membrane potential Vm. As the membrane potential reaches a given threshold Vth, then the neuron responds with a fire, i.e., by sending an output spike. 102,103 In addition to this simple I&F concept, many other bio-plausible models have been proposed to implement artificial neurons, such as the leaky I&F model 104 and the biophysical HH model. 105,106 The I&F neuron is usually implemented by relatively large CMOS circuits containing tens of transistors 6, 107 and large integrating capacitors. 108 For instance, a memory capacitor Cmem with capacitance of 432 fF was reported to have a layout area of 244 µm 2 in 0.35 µm CMOS technology for injection currents of the order of tens of picoamperes. 108 A larger capacitance may be needed in the case of larger synaptic currents, which might be the case for memory-based neural networks. [109][110][111] To reduce the circuit area for I&F neurons, one can take advantage of device physics of memory devices, typically in hybrid combination with CMOS transistors, to fully realize integration, firing and bursting modes of biological neurons. To reduce the area of the neuron integration circuit, it is possible to take advantage of pulse accumulation processes in nanoscale memory elements. For instance, the application of voltage pulses across a PCM can lead to incremental crystallization due to local Joule heating and a consequent increase of conductance, which can be used as an equivalent membrane potential. [10][11][12] This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset.

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Similar pulse accumulation processes in FERAM 14 and RRAM [112][113][114][115] can be used for compact spike integration, thus allowing to minimize the neuron area. Fig. 7 shows the implementation of I&F artificial neuron by using a Pr0.7Ca0.3MnO3 (PCMO) RRAM, where the integration function is performed due to the gradual conductance increase during set process. 112 Fig. 7a shows the structure of the PCMO RRAM device, where 70 nm-thick PCMO layer is inserted between a Ti BE and a W TE. Fig. 7b shows the measured current in response to applied pulses of fixed width and increasing amplitude. In general, the current shows an initial gradual increase, which can be understood as the integration phase, followed by a steep rise, representing the fire response. The non-linear current response is the result of the ion migration dynamics in PCMO, where the field-driven defect migration lead to an increase of conductance. Fig. 7c shows the measured current in response to the application of a sequence of 5 voltage spikes. The conductance first gradually increases under the stimulations of repeated set pulses (i.e., integration function), followed by an abrupt increase of spike current once reaching a threshold (i.e., fire function). Subsequently, a reset pulse is used to reset the RRAM device to the initial conductance. The experimental results of current transient support the feasibility of I&F neuron based on PCMO RRAM. 112 Similarly, the neuron integration function can be performed in a SrTiO3 based memristor device with uniform switching. 115

Neuron fire
In general, devices exhibiting intrinsic threshold switching allow to perform the fire function in a simple way, i.e., within a nanosized device instead of using bulky comparators and pulse generators. In fact, firing, bursting and oscillating functions of the neurons have been reported by using threshold-switching devices based on Mott transition [116][117][118] and RRAM. [119][120][121][122][123] Fig. 8a illustrates a typical implementation of an artificial I&F neuron, consisting of a volatile RRAM device or diffusive memristor based on SiOxNy:Ag and a parallel capacitor. 120 In the figure, the diffusive memristor with volatile behavior executes the fire function by threshold switching, while the capacitor conducts the integration function through the charging process. Additionally, a resistor in series with the artificial neuron is adopted as artificial synapse and to monitor the output current versus time. Fig. 8b shows the experimental response of the artificial neuron to a sequence of sub-threshold stimulations. 120 By applying the super-threshold pulse train on the I&F neuron, the capacitor is charged with a typical time constant, resulting in the increase of voltage across the diffusive memristor, thus serving as the LGP state variable. This integration process results in a negligible current during the first several pulses in the experimental data. Once the LGP reaches the threshold after a certain number of pulses, the volatile RRAM device switches to the highconductance state, thus resulting in a fire output signal with high current. The delay time between the arrival of input spikes and the fire operation depends on the RC time constant and the internal Ag dynamics of the memristor. After fire, the device spontaneously relaxes to a low conductance state, corresponding to its resting state, as a result of the discharge of the capacitor and the volatile behavior of the RRAM device. The results in Fig. 8b supports the feasibility of the artificial I&F neuron enabled by the volatile RRAM physics. Similar I&F neuron implementations were reported by using a vertical MoS2/graphene threshold switching memristor. 124 In some cases, RRAM devices with capacitive effect, referred to as memcapacitors, are also used to replace the common capacitor to implement the I&F neurons. [125][126][127] For instance, I&F neurons with various neuron functions were reported using single RRAM devices based on GaTa4Se8 128 and a stack of Ag/FeOx/Pt. 129 The combination of I&F functions in nanoscale memory device is the most promising to improve the scalability of artificial spiking neurons.

Oscillating neurons
Threshold switching in volatile RRAM devices provides the basis for generating self-sustained oscillations, thus enabling bio-plausible artificial neurons. Fig. 9 illustrates an oscillating neuron based on the Mott insulator NbO2. 116 As shown in Fig. 9a, the application of a voltage close to a characteristic threshold voltage VT causes the NbO2 layer to switch from a high resistance (off) state to a low resistance (on) state, followed by a fast recovery of the initial off state. This threshold switching effect was explained as due to internal Joule heating triggering a higher conductance due to Poole Frenkel transport [130][131][132][133] or insulator-metal transition typical of Mott insulators 134 or by a coexistence of these phenomena. 135 To describe the complex dynamics of Na + and K + ion channels in the HH neuron model, two elements are used in the HH neuron circuit of Fig. 9b each including a parallel combination of a NbO2 RRAM device and a capacitor. These two ionic channels are stimulated by pulses with opposite polarity bias and coupled to each other by the load resistor RL2, while the load resistor RL1 serves as input resistance. The parallel combination of the threshold switching device and a capacitor is able to induce oscillatory spike trains with various shapes. Assuming a constant input current, a time-oscillating response can be obtained by the HH circuit. Fig. 9c shows experimental results of the output of the HH neuron circuit, compared to circuit simulations for a constant input current of 20 µA. The inter-spike time interval can be controlled by the value of capacitances C1 and C2. Similar oscillatory HH neurons have been developed based on other types of devices exhibiting threshold switching, such as other Mott insulators VO2 136 and TaOx, 137 and chalcogenide glass GeSe. 13 Oscillatory neurons have also been demonstrated by using SiOxNy:Ag volatile RRAM, which is capable to controlling the oscillation frequency by the conductance value. 138 Threshold switching in a HfO2 layer with Pt/Ag nanodot top electrode and Pt bottom electrode was reported to display low operation voltage (<0.6 V) and ultralow power consumption (<1.8 μW), thus enabling low voltage/low power oscillatory neurons. 123

Dendritic filtering
In the biological nervous system, dendrites are important components of neuronal units that extend from the cell body of neurons and play a critical role in information processing. [139][140][141] Dendrites are generally considered to be passive elements that merely transmit synaptic currents This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset.

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to the soma. They can integrate synaptic inputs and output signals nonlinearly and filter out insignificant background information. [142][143][144] Recently, several CMOS-based circuits have been reported to emulate the dendrite functions . 145,146 Implementing the dendrite function in nanoscaled devices is thus highly desirable for neuromorphic engineering. Dendritic integration was shown by using starch-based electrolyte-gated oxide transistors. 147 Spatiotemporal dendritic integration and linear/superlinear dendritic algorithms were demonstrated within transistor structures. 148,149 Fig . 10 illustrates the analogy between the ionic channel in a biological synapse (a) and the twoterminal RRAM device (b), which provides the foundation to implement the key dendritic functions. 150 To implement dendritic nonlinear integration and filtering functions, a volatile RRAM with Pt/TaOx/AlOδ/Al stack was proposed, where a positive voltage stimulus leads to conductance increase followed by a gradual relaxation to the initial high-resistance state as the voltage bias is removed. Fig. 10c shows the measured electric characteristics of the artificial dendritic device, indicating a nonlinear current response to a linearly increasing voltage from 0 V to 5 V, which is similar to that of N-methyl-d-aspartate (NMDA) channels in the biological dendrite. Fig. 10d shows that the RRAM device can filter out sub-threshold input signals smaller than the threshold of 3 V and performs nonlinear integration of input signals larger than the threshold voltage, resulting in a continuously increasing current response over time. The filtering effect can be explained by the energy barrier for oxygen ion migration. Only the input signals with amplitude larger than the threshold voltage can induce the oxygen ion migration toward the Al electrode, resulting in a decrease of the barrier height and an increasing current response to the applied voltages. On the other hand, the sub-threshold input signals are filtered out. Fig. 10e and f shows the measured current during the inference process of a neural network for various input patterns with and without artificial dendrites, respectively. The pattern recognition accuracy and power consumption are significantly improved by including the dendritic devices into the neural network, thanks to the filtering effect.

Hardware synapses
Synapses in the biological neural system are responsible for the weighted transmission of spikes from a pre-synaptic neuron to a post-synaptic neuron, as depicted in Fig. 11a. 151 Most importantly, the synaptic weight should be able to adjust depending on the history of spiking stimulation, a phenomenon known as synaptic plasticity which is regarded as the basis for learning and memory functions. Synaptic plasticity can be realized in hardware via the conductance change in memory device, such as the set and reset processes in RRAM devices which have been widely developed to mimicking biological synapse. [151][152][153][154][155] The close emulation of synaptic functions is a critical step to achieve a neuromorphic system with the ability to learn and adapt in response to environmental changes. Generally, the synaptic plasticity can be categorized into long-term plasticity and shortterm plasticity depending on the retention time, representing the permanent and temporary synaptic modification, respectively 47,155,156 Various long-and short-term synaptic functions have been demonstrated by utilizing memory devices, such as STDP, spike-rate-dependent plasticity (SRDP), paired-pulse facilitation (PPF) and paired-pulse depression (PPD). 47,151-159

Long-term potentiation and depression
Long-term potentiation (LTP) and long-term depression (LTD) consist of the permanent increase or decrease, respectively, of the synaptic weight as a result of the spiking stimulation. LTP and LTD is possible in nonvolatile memory devices by the pulse-induced change of the conductance according to the input pulse shape and number. 155 Both digital (binary) and analogue (multilevel) conductance change are reported. [160][161][162] Binary states are more suitable for memory storage due to the clear difference between high-resistance state (HRS) and low-resistance state (LRS). 163 On the other hand, analogue states are ideal for synaptic devices with incremental weight update. [151][152][153][154][155] In particular, analogue-type conductance states with linear and symmetric LTP/LTD are essential in hardware accelerators of inference and training. 49,93,94,[164][165][166] Non-linear and asymmetric LTP/LTD are commonly observed in most synaptic devices. 67,94,167 Algorithmic and engineering methods should be identified to compensate the intrinsic linearity of synaptic weight update.
The linearity of the update characteristics can be improved by optimization of the programming pulse, 168 utilization of defects engineering 169 and adoption of three terminal devices such as the ECRAM. 68,74 Fig. 11b shows the LTP and LTD behaviors of a Pr0.7Ca0.3MnO3 (PCMO) based memristor under the programming spikes with different pulse scheme. 168 The A-type behavior is a typical update characteristic with nonlinear LTP and abrupt LTD, which was obtained by using spikes with constant voltage amplitude. The update linearity of LTP/LTD can be clearly improved by adopting spikes with incremental amplitude (type B) and pulse width (type C). These results indicate that nonidentical pulses are most effective in controlling and improving the synaptic update linearity. This is because the increasing amplitude/pulse-width compensate the typical saturating behavior of the conductance for constant pulses. 94 However, note that the increasing amplitude and increasing width methodologies are not compatible with the outer product scheme of weight update, where the whole crosspoint array is updated simultaneously by applying voltage vectors at the rows and columns with variable pulse widths. 169 The increasing amplitude and width thus results in more complicated updated schemes requiring longer update time and larger energy consumption. The LTP/LTD linearity can be also enhanced in ECRAM devices thanks to the bulk-type of switching and to the separation between the programming path (between gate and channel) and the read path (across the channel between source and drain). This allows for better controllability of the device conductance by field-induced migration of impurities, such as Li ions in inorganic ECRAM [68][69][70] or protons in organic ECRAM. 71

Spike-timing-dependent plasticity (STDP)
STDP, namely the weight modification relying on the temporal order of pre-and post-synaptic spikes, is regarded as one of the essential learning rules for unsupervised learning. 7,9,154,155 Thus, implementing STDP rules in hardware SNNs is a critical step toward achieving neuromorphic systems capable of learning and adaptation. For the typical STDP rule, the synaptic weight undergoes LTP if a pre-synaptic spike occurs earlier than a post-synaptic spike, i.e. it the spike delay Dt = tpost-tpre between the post-synaptic spike time tpost and the pre-synaptic spike time tpre is positive. Conversely, LTD takes place for the case Dt < 0. 154,155 To achieve the above STDP function, the synaptic device usually needs to satisfy the requirement of gradual conductance change and fast response to individual spikes.
Various STDP methods have been reported for both digital-and analogue-type memory devices. 154,155,[170][171][172][173] A typical approach for STDP is the overlap method where the neuron spike is designed such that the Dt-dependent overlap between pre-and post-synaptic spikes leads to the desired LTP or LTD. 154,172,173 Fig. 12 shows typical examples of overlap-type implementations of STDP for HfO2-based RRAMs. 173,174 The pre-and post-spikes can be designed as series of 6 pulses, where the first negative pulse is followed by 5 positive pulses with decreasing amplitude, as shown in Fig. 12a. An important design principle is that each individual spike is unable to induce a conductance change DG, i.e., all pulses should be below the threshold for set/reset processes. However, the overlap between pre-spike applied at one electrode and the post-spike applied to the other electrode causes a voltage drop across the memory device that is large enough to change the conductance. As illustrated in Fig. 12a, when the pre-spike is applied earlier than the post-spike (Dt > 0), the overlapping spikes result in a positive pulse with a relatively large amplitude, hence LTP. 173 On the other hand, for Dt < 0, the overlapping spikes cause a negative pulse with large amplitude, hence LTD. Most importantly, Dt controls the amplitude of the resulting pulse amplitude, hence the degree of conductance change DG. Fig. 12b shows the measured DG as a function of the spike timing, indicating that the amplitude of positive and negative DG decreases for increasing delay |Dt|, in agreement with the STDP rule. 173 Previous work suggests that the correlation between DG and Dt can be tuned by adjusting the pulse shape and the programming scheme. 175 Various types of STDP curves where obtained by the overlap approach in various synaptic devices, including RRAM, 176, 177 PCM, [178][179][180] STT-MRAM 181 and FERAM. 172 This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset. The overlap STDP scheme may suffer from a relatively large variation of DG, since there is no compliance current to control the growth of conducting filament during the LTP process. To overcome this issue, the 2-transistor/1-resistor (2T1R) synaptic circuit structure was proposed to implement STDP function in RRAM 174 and PCM. 183 As shown in Fig. 2, a series MOS transistor can limit the current during the set transition for better controlling the resistance in RRAM. 35,184 The additional transistor also provides a multiple-input control for handling the various synaptic functions, i.e., spike transmission, LTP and LTD. Fig. 12c illustrates the 2T1R synapse, where the PRE spike is applied to the RRAM TE, while the POST spike is applied to the fire gate (FG). Additionally, a short positive pulse is given to the communication gate (CG) of the second transistor for synaptic transmission. The coincidence of the PRE spike with amplitude VTE and the POST spike with amplitude of VFG can induce the set and reset transition of resistive switching memory, thus leading to LTP and LTD, respectively. Importantly, the filament growth is controlled by the VFG, which in turn depends on the spike timing thus enabling time-dependent potentiation according to the STDP function. Fig. 12d shows the resulting STDP characteristics, namely the relative change of conductance R0/R, where R0 is the resistance before the spike application and R is the final resistance, for various initial states R0 obtained for various IC. the results indicate LTD for Dt < 0 and LTP for Dt > 0, where the change of conductance tends to vanish at increasing |Dt|, which is in line with the observed biological STDP. 7 A simplified STDP synaptic circuit was reported by adopting a 1-transistor/1-resistor (1T1R) structure with RRAM synapse. 111,185 This was later extended to a four-transistor/one-resistor (4T1R) structure to demonstrate the SRDP. 186,187 Although the overlap method allows for efficient STDP function with local activity, it does not fully account for the observed biological STDP, where overlapping spikes are generally not necessary for weight update. To overcome this limitation, the second-order memristor was proposed to execute LTP/LTD according to the STDP rule without any overlap between pre-and post-spikes. 188 The second-order memristor consists of a RRAM device where the conductance change is not only determined by the first variable, e.g., the filament size or interface barrier, but also by a second variable, e.g., the local temperature or oxygen mobility, which impacts the dynamics of the first variable. 41,155,188,189 The second variable usually displays a transient dynamics, such as a spontaneous decay after stimulation, which is similar to the Ca2+ dynamics in the biological synapse. As a result, the second-order memristor can display non-overlap, biorealistic emulation of STDP rule and other synaptic learning functions. 41,155,188,189 Fig. 12e illustrates the pre-/postspikes, including a programming pulse with high amplitude and a heating pulse with long pulse width. By applying the pre-and post-spikes at the TE and BE, the interaction between the applied electric field and the local temperature can lead to a Dt-dependent conductance change, as indicated by the STDP characteristic for a Ta2O5−x/TaOy second-order memristor in Fig. 12g. Similarly, a second-order memristor consisting of a Pt/WO3−x/W stack was reported, where the two variables are the Schottky barrier and the oxygen ion mobility. 177 Second-order memristor were experimentally demonstrated for various material systems, such as InGaZnO, 155 Ta2O5−x/TaOy, 188 WO3−x, 177,189 SrTiO3, 190, SiOxNy:Ag. 41 and TiO2:Ag. 191

Spike-rate-dependent plasticity (SRDP)
In the human brain, there are two main types of information coding, namely time coding and rate coding. While STDP is most suitable for learning in the presence of time coding, SRDP can serve as learning rule for rate coding. 192 Frequency dependent LTP/LTD have been extensively reported in memory devices with dynamic effects, e.g., oxygen diffusion. 193,194 SRDP generally relies on the Bienenstock-Cooper-Munro (BCM) learning rule as a high-order function of SRDP. [195][196][197] According to the BCM rule, spike trains with a frequency larger than a certain threshold induce LTP, while spike trains with a lower frequency lead to LTD. A threshold slide effect has been reported, where the threshold frequency changes depending on the learning experience, thus enabling a historydependent synaptic adaptation. 83,198 Many efforts have been made to realize the BCM rule by using the rate-based pre-spikes in the second-order memristors. 189,199 In these schemes, the forgetting effect of the learning experiences and the potentiation effect induced by the rate-based pre-spikes were compared, thus achieving the BCM learning rule with monotonic trend. The effect of tunable forgetting rate on the BCM curve was studied for SrTiO3-based RRAM devices. 200 However, monotonic SRDP is not consistent with the "tick" shape of BCM rule in biological systems. Also, the BCM rule should represent the long-term characteristics rather than the shortterm modification implemented in some studies. 189,200 This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset. Compared to the standard STDP with paired spikes, a third spike is introduced in the triplet-STDP, thus resulting in a triplet of interacting spikes. The interaction of paired spikes with the third spike leads to the multiplicative term to enable the BCM rule. In biological systems, there are two types of triplet STDP, namely, the first-spike-dominating rule and last-spike-dominating rule. The former was demonstrated in a Pt/SrTiO3/Nb-STO stack RRAM exhibiting synaptic suppression triplet-STDP. 115 Last-spike-dominating triplet-STDP was reported for a Pt/WO3−x/W second-order memristor. 199,201 This is shown in Fig. 13a reporting the typical triplets of 'post-pre-post' and 'prepost-pre' for stimulating the WO3−x synaptic RRAM device. Fig. 13b shows the conductance change as a function of the first and the second spike delay in the post-pre-post triplet, Dt1 and Dt2, respectively, while Fig. 13c shows the same for the pre-post-pre triplet. Fig. 13d shows the measured DG as a function of Dt1 for increasing spiking rate, indicating that plasticity depends on both the pre-spike rate rx and post-spike rate ry. Based on these results, the BCM learning rule can be implemented by designing a proper triplet-STDP scheme. Fig. 13e illustrates the tripletbased BCM learning rule by extracting the data from the diagonal line of quadrant II in Fig. 13b and defining the post-spike rate as given by ry = 1/(|Dt1| + | Dt2|). The experience-dependent sliding threshold characteristic is also demonstrated by tuning the initial conductance G0 in such BCM implementation, resulting in a close emulation of the biological BCM curve. 199 This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset.

Short-term synaptic plasticity and memory
While long-term plasticity can last for the entire lifetime, short-term plasticity or short-term memory (STM) in the human brain can be as short as milliseconds to minutes. [148][149][150] Several typical types of STM have been realized in hardware memory devices, including the excitatory postsynaptic current (EPSC), PPF/PPD and SRDP. 47,[155][156][157]193,194 Usually STM is implemented by directly taking advantage of the inherent transient behavior of volatile memory devices. For instance, Fig. 14 shows the analogy between the transient dynamics of the EPCS 202 and the volatile nature of an Ag filament in a HfO2-based RRAM device. 203 In a biological synapse of Fig. 14a, a pre-synaptic spiking stimulation induces the release of neurotransmitter from synaptic vesicles into the synaptic cleft. The neurotransmitter, e.g., L-glutamate, then binds to the receptor to activate an ion channel, thus triggering the ionic inflow of Na + and Ca 2+ into the post-synaptic neuron, which is responsible for the EPSC. 202 The opening of the ion channels has limited duration in time, which accounts for the transient nature of the EPSC. In a volatile RRAM, the electrical pulse results in the formation of an Ag filament, which then serves as a conductive bridge for electrons across the RRAM. Both the EPSC and the conductive filament remain active for a short time, typically in the range from few ms to several minutes. The physics of the volatile RRAM can thus serve as a basis for replicating STM in hardware via a small-scale device, i.e., without the need for large capacitors to emulate relatively-long time constants. Volatile memory effects have been used to naturally emulate the EPSC in several two-and 3terminal memory devices. 41,155,[204][205][206][207] Similarly, volatile memory devices can also mimic the PPF induced by paired spikes. [204][205][206][207] In a biological PPF, the second spike can generate much larger change of synaptic weight than the first spike, thus resulting in a strong spike interaction and correlation of spikes in the Ca 2+ dynamics. On the other hand, paired spikes may also cause synaptic depression, hence PPD, which has been also mimicked in several memory devices. 157,208,209  This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset.  According to our daily experience, it is known that STM is capable to transition to long-term memory (LTM) by repeated training, as illustrated in Fig. 15a. 47 Ag2S-based volatile RRAM, also called atomic switches, can replicate a similar function. Fig. 15b depicts a simplified memory model to implement the transition from STM to LTM transition in a volatile RRAM synapse, where the memorization level can increase from the sensory memory (SM) to STM and LTM by increasing the number of stimulations, similar to repeated rehearsals in the human experience. Fig. 15c shows that data retention is clearly enhanced by repeated stimulations, supporting the transition from STM to LTM in the Ag2S RRAM device. Similar to the Ag2S RRAM device, the transition from STM to LTM has been extensively reported for various memory devices. 155,156,210,211 5.5 Cognitive computing functions enabled by STM STM is an essential function in the human brain that is functional for several sensing and recognition functions, such as the recognition of speech, movement and other types of dynamic information. Fig. 16 shows an example of the use of volatile RRAM for the movement recognition and direction selectivity similar to the human retina. The biological visual system is capable of fast motion detection by direction-selective (DS) ganglion cells. 212 As shown in Fig. 16a, the retina includes bipolar cells and starburst amacrine cells (SACs) with receptive fields capable of stimulating the ganglion cells with excitatory and inhibitory inputs, respectively. 203 The combination of excitatory and inhibitory signals causes an EPSC into the ganglion cells, which enables the recognition of various moving directions under sight. Fig. 16b shows receptive field stimulated by a moving light bar, which first induces excitatory current spikes, followed by inhibitory current spikes. The comparison between the transient excitatory and inhibitory currents result in an EPSC with large positive current, which exceeds a threshold thus triggering the detection of the preferred direction. The transient excitatory and inhibitory currents was replicated in hardware by volatile RRAM with Ag TE and HfO2 as switching material. 203 Fig. 16c schematically shows the circuit with several volatile RRAM to enable the averaging of stochastic excitatory and inhibitory currents. The overall EPSC, obtained as the subtraction of excitatory and inhibitory currents, shows a positive peak for the preferred direction (left to right, Fig. 16d) and negative peak for the non-preferred direction (right to left, Fig. 16e). Fig. 16f shows the distribution of preferred and non-preferred EPSCs, indicating that the two directions can be efficiently discriminated by comparing the EPSC to a threshold. The same concept can be extended to the full range of movement directions ( Fig. 16g and h), thus enabling fast direction sensitivity by direct current sensing in the analogue domain. 203 STM is also at the basis of reservoir computing (RC) systems, 214,215 which are widely utilized to implement temporal and sequential data processing. Generally, a RC system consists of a reservoir network for mapping the input stimuli into a high-dimensional feature space and a readout network for the analysis of the response from the reservoir states and final inference. Volatile memory devices with intrinsic STM behavior offer an ideal platform for brain-inspired implementing RC systems. For instance, volatile WOx-based RRAM with STM dynamic effect were used to implement a RC network for image recognition. 213 Fig. 17 shows the network architecture of the RC system for digit recognition using 5 volatile RRAM devices. Each digit is mapped into 20

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PLEASE CITE THIS ARTICLE AS DOI:10.1063/5.0047641
pixels, as shown in Fig. 17b for the case of digit 2. The 20 pixels are divided into 5 rows, each row stimulated with a sequence of 4 consecutive spikes applied to one of the 5 RRAM synapses. As a result, each RRAM device is stimulated by a 4-spike timeframe input stream. The image is thus represented by a spatiotemporal coding, i.e., not only using the spatial location in the rows but also the temporal sequence of the stream. For the readout function, a fully-connected network with 5 input neurons and 10 output neurons is employed to measure the conductance states of the 5 memristors in the reservoir network and recognize the digit. The recognition of the ten digits is executed only using 5 memristors, which is far less than the 200 weights in a conventional neural network. Similar spatiotemporal RC networks based on RRAM have been shown for handwritten digit recognition, 213 solution of second-order nonlinear tasks, 213 spoken-digit recognition 214 and autonomous chaotic time-series forecasting. 214 Besides top-down memory devices fabricated with conventional microelectronic technology, bottom-up approaches have been proposed. For instance, volatile switching was demonstrated in a network of switching nanowires capable of learning via homo-synaptic and hetero-synaptic plasticity. 215 This concept might pave the way for hardware implementation of unconventional computing paradigms in selforganizing stochastic networks of nanowires.

Technological challenges and potential solutions
While RRAM devices offer a wealth of physical properties that are attractive for neuromorphic computing primitives, there are several technological challenges that currently prevent the widespread adoption of RRAM for memory and computing.
A major technological limitation is given by the programming and read variations that prevent repeatable, reliable storage of data. This is a strong issue especially for MLC storage where the drift and fluctuation of the conductance cause time-dependent retention failure. 51 For instance, DNNs adopting MLC weights for MVM are heavily affected by fluctuations and drift that can cause a significant drop of accuracy during time. 49,217 Programming variations can be improved by accurate program-verify algorithms, based on voltage-or current ramping during the set or reset operation. In particular, current-based approaches appear most promising thanks to a relatively shallow programming characteristics, compared to voltage-based techniques. 218 Relaxation effects might be mitigated by redundancy techniques, where averaging among various devices allow for a better robustness toward individual fluctuations and noise. 219 It has been observed that low-current LRS are more affected by drift and variations after programming, as a result of the smaller size of the conductive filament. 220 Therefore, one may configure the network algorithm in such a way that the number of intermediate weights is minimized, whereas the presence of HRS and full LRS with high stability is maximized. 221 RRAM technologies with higher stability, such epitaxial 63 and uniform-switching RRAM 64-66 might also improve the immunity to resistance fluctuations for high precision in-memory computing. On the other hand, neuromorphic computing appears less affected by variations and stochasticity, thanks to the self-adaptation and continuous learning, where a change in the device parameters can be compensated in real time. However, note that variability in neuromorphic circuits does not affect only the synaptic weight but also all other brain-inspired properties such as neuron integration and retention time of shortterm synapses.
Another key issue for RRAM is the excessive read current, which is due to the filamentary conduction across a metallic path across a nanometric length in the active oxide. Typically, the LRS shows a conductance in the range between 10 kW and 100 kW, which corresponds to a synaptic current between 1 µA and 10 µA for a typical read voltage of 0.1 V. While this current is reasonable for typical memory applications, aimed at fast read in presence of large parasitic capacitances within large arrays, it represents a critical limitation for MVM implementations in DNNs and other neuromorphic applications. For instance, assuming a crosspoint array of size 128x128 in Fig. 6 with an average synaptic current of Iread = 10 µA, the current in an individual row/column would reach 640 µA, which requires a decoder transistor with the proper channel size for sensing and amplification. In addition, the large read current may lead to a significant voltage drop, also known as IR drop, along the row/columns of the crosspoint array. For instance, assuming a cell-to-cell wire resistance of r = 1 W in the array columns/rows, 222 the total voltage drop would be approximately given by Δ ≈ 1234 6 /2, which gives Δ ≈82 mV, which contributes an error around 82% with respect to the applied voltage. Reducing the operating current in the device typically requires LRS at relatively small filament size, which are in turn less stable with respect to drift and fluctuations. At architecture level, the IR drop issue is addressed by adopting crosspoint arrays, also referred to as tiles, with relatively small size, e.g., below the 32x32 range. 223 Sparsity, which is typical of the human brain, hence of many hardware neuromorphic circuits, can alleviate the IR-drop problem, as it reduces the number of active synapses within the array. Alternative device concepts, such as uniform-switching RRAM [64][65][66] or ECRAM 67-74 characterized by bulk-type conduction, appear more promising in reducing the read current, thus enabling a larger size of the neuromorphic array.
More on the technological side, provided that synaptic currents can be substantially reduced, a significant issue is the development of high density crosspoint array, possibly with 3D integration. The brain is in fact characterized by a high connectivity, where each neuron is connected, on average, to 10,000 neurons. 224 Achieving such a large connectivity thus requires arrays with extremely large numbers of rows and columns, which makes 3D integration mandatory to fit the neuromorphic circuit within a single chip. Recently, 3D crosspoint arrays with 8 layers of RRAM devices with vertically-aligned electrode have been demonstrated for DNN implementation, 27 although the extension of this technology to brain-inspired cognitive circuits has not been reported yet. In this regard, a significant challenge is the RRAM selector, since the 3D integration of CMOS transistors is not straightforward. Several non-linear selectors with the capability of 3D integration have been reported, including Mott insulator, 225-227 chalcogenide glasses, 228,229 mixed ion-electron conduction (MIEC) devices, 230 multilayer tunnel junctions, 231 and threshold vacuum switches. 232 The resulting one-selector/one-resistor (1S1R) structure is extremely compact and suitable for 3D integration, thus being very attractive for both memory 233 and computing applications. 67 3D-integrated, monolithic circuits capable of hetero-integration of various RRAM technologies, each serving a different function for sensing, neurons and synapses, would provide the ideal technology platform for neuromorphic system scapable of paralleling the brain computing functionality via device physics.

Conclusions
Neuromorphic computing requires a set of ad-hoc hardware capable of harnessing device physics to recreate the neuron and synapse functions in the human brain. RRAM offers a range of physical phenomena, arising from electrical transport, switching and ion migration, that can be used to approximate neuromorphic functions, such as neuronal integration, fire, oscillations, dendritic filtering and synaptic plasticity according to various spike-time, spike-rate learning rules experimentally observed in the brain. Ionic diffusion allows for short-term plasticity and STM, which form the basis of direction selectivity, RC and other emerging cognitive computing concepts. While many of these phenomena have individually been demonstrated by proof of concept, their combination into full neural networks and their extension to alternative architectures, such as multiterminal devices and bottom-up nanostructures, may further develop this field of neuromorphic devices into a mature technology for manufacturable cognitive computing hardware.

Acknowledgments
This work was supported by the Italian Ministry of Foreign Affairs and International Cooperation (grant number PGR01011) and by Chinese MOST (grant number 2018YFE0118300).

Data Availability
Data sharing is not applicable to this article as no new data were created or analyzed in this study.
This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset.